ez iCoupler Isolated Interface Development Environment€¦ · Plug and play system evaluation ....

Hardware User Guide UG-400

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

ezLINX iCoupler Isolated Interface Development Environment

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | of 20

FEATURES Plug and play system evaluation Easy evaluation of 8 isolated physical layer communication

standards Open source hardware Open source software iCoupler and isoPower technology ADSP-BF548 Blackfin processor running uClinux Sample PC application Sample embedded uClinux application 64 MB RAM 32 MB flash Extender connector for additional functionality

APPLICATIONS Isolated interfaces

EVALUATION KIT CONTENTS EZLINX-IIIDE-EBZ Power supply ezLINX software DVD USB A to mini USB B cable

EZLINX-IIIDE-EBZ

1064

9-00

1

Figure 1.

GENERAL DESCRIPTION The ezLINX™ iCoupler® isolated interface development environment provides developers with a cost-effective, plug and play method for evaluating eight digitally isolated physical layer communication standards (USB, RS-422, RS-485, RS-232, CAN, SPI, I2C, and LVDS). The Blackfin® ADSP-BF548 processor runs the uClinux® operating system and allows for easy customi-zation through the open source hardware and software platform. Development time is significantly reduced for embedded designers and system architects who are designing and evaluating isolated communication standards. The interfaces on ezLINX use Analog Devices, Inc., isolated transceivers with integrated iCoupler and isoPower® digital isolator technology.

The hardware of the ezLINX iCoupler isolated interface develop-ment environment contains the ADSP-BF548 Blackfin processor with 64 MB of RAM and 32 MB of flash memory. The isolated physical layer communication standards are implemented using Analog Devices isolated transceivers with integrated iCoupler and isoPower technology. Devices used to implement these isolated physical layer communication standards include the following:

• Isolated USB using the ADuM3160

• Isolated CAN using the ADM3053 signal and power isolated CAN transceiver

• Isolated RS-485 and RS-422 using the ADM2587E signal and power isolated RS-485/RS-422 transceiver

• Isolated RS-232 using the ADM3252E signal and power isolated RS-232 transceiver

• Isolated I2C using the ADuM1250 and ADuM5000 • Isolated SPI using the ADuM3401, ADuM3402, and

ADuM5000 • Isolated LVDS using the ADuM3442, ADuM5000,

ADN4663, and ADN4664

This evaluation board contains multiple parts with isoPower technology, which uses high frequency switching elements to transfer power through the transformer. Special care must be taken during PCB layout to meet emissions standards. See the AN-0971 Application Note, Recommendations for Control of Radiated Emissions with isoPower Devices, for board layout recommendations. The ezLINX PCB layout has not been verified to pass radiated emissions specifications.

http://www.analog.com/ADSP-BF548



http://www.analog.com/ADuM3160

http://www.analog.com/ADM3053

http://www.analog.com/ADM2587E









http://www.analog.com/ADN4663


http://www.analog.com/AN-0971

www.analog.com

UG-400 Hardware User Guide

Rev. 0 | of 20

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Evaluation Kit Contents ................................................................... 1 ezLINX-IIIDE-EBZ .......................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 System Architecture ......................................................................... 3

Isolated CAN ................................................................................. 4 Isolated RS-485 and RS-422 ........................................................ 5 Isolated USB .................................................................................. 6 Isolated RS-232 ............................................................................. 7

Isolated I2C .....................................................................................8 Isolated SPI .....................................................................................9 Isolated LVDS ............................................................................. 12 Power Input ................................................................................. 14 3.3 V Power Supply .................................................................... 14 1.2 V, 2.5 V, and 5 V Power Supplies ........................................ 15 Extender Connector ................................................................... 16 RS-232 Console .......................................................................... 17 LEDs ............................................................................................. 18 Jumper Configurations .............................................................. 19

REVISION HISTORY 8/12—Revision 0: Initial Version


Rev. 0 | of 20

SYSTEM ARCHITECTURE The system architecture block diagram of the ezLINX hardware is shown in Figure 2. An extender connector, Hirose FX8-120P-

SV(91), is added for additional functionality. The Ethernet option is not fitted on the standard ezLINX hardware.

1064

9-00

2

AD

uM34

42

SPO

RT2

AD

uM31

60

USB

SMC

EBU

I

ISO

LATE

DLV

DS

ISO

LATE

DU

SBET

HER

NET

JTAG

JTAG HIROSE FX8-120P-SV(91)

PPIO GPIO SPORT3 TW0 CAN1 SPI1 UART0 GPIO

LEDs

RESET

EBU

ID

DR

RTC

32M

BFL

ASH

64M

BD

DR

32.7

68kH

z

25MHz

FACTORYRESET

ADSP-BF548

ADuM3401ADuM3402

SPI2

ISOLATEDSPI2

ADuM1250

TW1

ISOLATEDI2C

ADM3053

CAN0

ISOLATEDCAN

ADM2587E

UART2

ISOLATEDRS-485

ADM3252E

UART3

ISOLATEDRS-232

ADM3202

UART1

CONSOLE

ADuM3401ADuM3402

SPI0

ISOLATEDSPI

*ETHERNETNOT FITTED

Figure 2. ezLINX Hardware Block Diagram


Rev. 0 | of 20

ISOLATED CAN The isolated CAN port is implemented using the ADM3053 signal and power isolated CAN transceiver. The ADM3053 connects to CAN0 of the ADSP-BF548 and is capable of functioning at data rates of up to 1 Mbit/sec. Figure 3 shows a circuit diagram of the implementation of the ADM3053 on the ezLINX hardware.

The CAN node can be configured using Jumpers JP17 and JP18. When both Jumpers JP17 and JP18 are fitted, the CAN node is split terminated with 120 Ω and a common-mode capacitor of 47 nF. If termination is not required, remove JP17 and JP18. Table 4 shows the jumper configurations for all the interfaces on ezLINX.

The 5 V supply is connected to the VCC pin (Pin 8) to power the isoPower isolated power supply of the ADM3053. This generates an isolated 5 V on the VISOOUT pin (Pin 12) of the ADM3053 and must be connected to the VISOIN pin (Pin 19). The 3.3 V supply is connected to the VIO pin (Pin 6) to power the iCoupler signal isolation of the ADM3053. This is to ensure compatibility with

the 3.3 V logic of the Blackfin ADSP-BF548. The RS pin (Pin 18) is connected through a 0 Ω resistor to CAN_ISO_GND to deactivate slew rate limiting.

A 4-pin screw terminal connector, J8, is used for easy access to the CANH (Pin 1 of J8), CANL (Pin 3 of J8), and CAN_ISO_GND (Pin 2 and Pin 4 of J8) signals.

The AN-1123 Application Note, Controller Area Network (CAN) Implementation Guide, provides more information about imple-menting CAN nodes.

The ADM3053 contains isoPower technology that uses high frequency switching elements to transfer power through the transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. Refer to the AN-0971 Application Note, Recommendations for Control of Radiated Emissions with isoPower Devices, for details on board layout considerations.

1064

9-00

3

5V

GND

3.3V

GND

3.3V CAN_ISO_5V

CAN_ISO_GND

CAN_ISO_GND

5V

GND

CAN_ISO_5V

CAN_ISO_GND CAN_ISO_GND CAN_ISO_GND

CAN0RXCAN0TX

C1610.1uF

U17

ADM3053

GND11

NC2

GND13

RxD4 TxD5

VIO6

GND17

VCC8

GND19

GND110

GND211

VISOOUT12

GND213

VREF14

CANL15

GND216

CANH17

Rs18

VISOIN19

GND220

C1600.01uF

C1580.01uF

C15910uF

R670R

++ JP17

C1630.1uF

J8

SCREW_4

1

2

3

4

C16547nF

C16210uF

C1570.1uF

R6860R4

++JP18

R6960R4

C1640.1uF

Figure 3. ADM3053 Isolated CAN Implementation














Rev. 0 | of 20

ISOLATED RS-485 AND RS-422 The isolated RS-485 and RS-422 port is implemented using the ADM2587E signal and power isolated CAN transceiver. The ADM2587E connects to UART2 of the ADSP-BF548 and is capable of functioning at data rates of up to 500 kbit/sec. Figure 4 shows a circuit diagram of the implementation of the ADM2587E on the ezLINX hardware.

The RS-485/RS-422 node can be configured using Jumpers JP3, JP4, JP19, and JP40. To configure the node as a half-duplex RS-485 node, connect JP3, JP4, and JP40. When JP3 and JP4 are fitted, A to Y are connected and B to Z are connected. When JP3 and JP4 are removed, the node is configured as a full-duplex RS-422 node. When JP19 is fitted, the A and B pins are terminated with 120 Ω. If termination is not required, remove JP19. When JP40 is connected, a pull-up resistor of 10 kΩ is connected to the RxD pin (Pin 4) of the ADM2587E. Table 4 shows jumper configurations for all the interfaces on ezLINX.

The 3.3 V supply is connected to the VCC pins (Pin 2 and Pin 8) to power the isoPower isolated power supply and the iCoupler signal isolation of the ADM2587E. This generates an isolated 3.3 V on the VISOOUT pin (Pin 12) of the ADM2587E, which is connected to the VISOIN pin (Pin 19).

A 6-pin screw terminal connector, J7, is used for easy access to the A (Pin 2 of J7), B (Pin 3 of J7), Z (Pin 4 of J7), Y (Pin 5 of J7), and RS-485_ISO_GND (Pin 1 and Pin 6 of J7) signals.

The AN-960 Application Note, RS-485/RS-422 Circuit Imple-mentation Guide, provides more information about implementing RS-485 and RS-422 circuits.

The ADM2587E contains isoPower technology that uses high frequency switching elements to transfer power through the transformer. Special care must be taken during PCB layout to meet emissions standards. Refer to the AN-0971 Application Note, Recommendations for Control of Radiated Emissions with isoPower Devices, for details on board layout considerations.

1064

9-00

4GND

3.3V

RS485_ISO_GND

RS485_ISO_3.3V

GND

3.3V RS485_ISO_3.3V

RS485_ISO_GND

RS485_ISO_GND

3.3V

UART2TXUART2RX

#REDE

C15410uF

R11110K

+ +JP4

JUMPER

C1490.01uF

++ JP19

C1520.01uF

R66120R

C1500.1uF

U16

ADM2587E

GND11

VCC2

GND13

RxD4

RE5

DE6

TxD7

VCC8

GND19

GND110

GND211

VISOOUT12

Y13

GND214

Z15

GND216

B17A18

VISOIN19

GND220

C1550.1uF

J7

SCREW_6

1

2

3

4

5

6

C1530.1uF

+ +JP3

JUMPER

C1560.1uF

C15110uF

++ JP40

Figure 4. ADM2587E Isolated RS-485 and RS-422 Implementation














Rev. 0 | of 20

ISOLATED USB The isolated USB port is implemented using the ADuM3160 full speed USB isolator. The ADuM3160 connects to the integrated PHY of the ADSP-BF548’s USB controller and is capable of fun-ctioning at data rates of up to12 Mbit/sec. Figure 5 shows a circuit diagram of the implementation of the ADuM3160 on the ezLINX hardware.

The VBUS1 pin (Pin 1) and VDD1 pin (Pin 3) of the ADuM3160 are powered from the 5 V VBUS line of the USB mini connector and can only be connected to a USB master. The VBUS2 pin (Pin 16) and VDD2 pin (Pin 14) are powered from the 3.3 V generated by the ezLINX power supply.

10649-005

USB_

ISO

_GND

GND

USB_

ISO

_GND

USB_

ISO

_GND

USB_

ISO

_GND

GND

3.3V

GND

3.3V

3.3V

GND

GND

GND

3.3V

USB_

ISO

_GND

J5

USB

MIN

I B F

VBUS

1D-

2D+

3NC

4G

ND5

S9 9S8 8S7 7S6 6

C133

1uF

C138

0.1u

F

R62

24R

R14

10K

R65

1M

Y4 24M

Hz

OE

1

GND 2

OUT

3

VDD4

D7 PGB1

0106

03

R63

24R

LED1

0LE

D

C139

0.01

uF

D8 PGB1

0106

03

C134

0.01

uF

R64

24R

C135

0.1u

F

R100

1K

U4B

ADSP

_BF5

48

USB_

XIF1

USB_

XOF2

USB_

RSET

D3

USB_

VREF

B1

USB_

VBUS

D2

USB_

IDG

3

USB_

DPE1

USB_

DME2

C123

0.01

uFRV

1VA

RIST

OR

R59

10K

DNP

FER4

600R

C136

0.1u

F

R18

33R

C137

0.1u

F

U13

ADuM

3160

VBUS

11

GND

12

VDD1

3

PDEN

4SP

U5

UD-

6UD

+7

GND

18

GND

29

DD+

10DD

-11

PIN

12SP

D13

VDD2

14

GND

215

VBUS

216

R61

24R

Figure 5. ADuM3160 Isolated USB Implementation








Rev. 0 | of 20

ISOLATED RS-232 The isolated RS-232 port is implemented using the ADM3252E signal and power isolated RS-232 transceiver. The ADM3252E con-nects to UART3 of the ADSP-BF548 and is capable of functioning at data rates of up to 460 kbit/sec. Figure 6 shows a circuit diagram of the implementation of the ADM3252E on the ezLINX hardware.

When the JP2 jumper is fitted, it implements a loopback of the isolated RS-232 transmitter output (Pin TOUT1) to the receiver input (Pin RIN1).

The VCC pins (Pin A2, Pin B1, and Pin B2) of the ADM3252E are powered with 3.3 V and generate an isolated 3.3 V on the

VISO pins (Pin A10, Pin B10, and Pin C10) using Analog Devices isoPower technology.

A 3-pin screw terminal connector, J6, is used for easy access to the TOUT1 (Pin 2 of J6), RIN1 (Pin 3 of J6), and RS232_ISO_GND (Pin 1 of J6) signals.

The ADM3252E contains isoPower technology that uses high frequency switching elements to transfer power through the transformer. Special care must be taken during PCB layout to meet emissions standards. Refer to the AN-0971 Application Note, Recommendations for Control of Radiated Emissions with isoPower Devices, for details on board layout considerations.

1064

9-00

6

RS232_ISO_GND

3.3V

GND

GND RS232_ISO_GND

RS232_ISO_3.3V

RS232_ISO_GND

RS232_ISO_GND

3.3V RS232_ISO_3.3V

UART3TX

UART3RX

C1420.1uF

U44

ADM3252E

NC1A1

VCCB1

GNDC1

TIN1D1

GNDE1

TIN2F1

GNDG1

ROUT1H1

GNDJ1

ROUT2K1

NC2L1

VCCA2

VCCB2

GNDC2

GNDD2

GNDE2

GNDF2

GNDG2

GNDH2

GNDJ2

GNDK2

GNDL2

VISOA10

VISOB10

VISOC10

GNDISOD10

GNDISOE10

GNDISOF10

C2-G10

GNDISOH10

GNDISOJ10

GNDISOK10

GNDISOL10

DNC1A11

V+B11

C1+C11

TOUT1D11

C1-E11

TOUT2F11

C2+G11

RIN1H11

V-J11

RIN2K11

DNC2L11

C1250.1uF

C1260.1uF

C1410.1uF

C23610uF

C1400.1uF

C23710uF

+ +

JP2

JUMPER

C1300.1uF

J6

Screw_3

1

2

3

Figure 6. ADM3252E Isolated RS-232 Implementation











Rev. 0 | of 20

ISOLATED I2C The isolated I2C port is implemented using the ADuM1250 I2C isolator and the ADuM5000 isoPower isolated dc-to-dc converter. The ADuM1250 connects to TWI1 of the ADSP-BF548 and is capable of functioning at a maximum frequency of 1 MHz. Figure 7 shows a circuit diagram of the implementation of the ADuM1250 and ADuM5000 on the ezLINX hardware.

The VDD1 pin (Pin 1)) of the ADuM1250 and the VDD1 pins (Pin 1 and Pin 7) of the ADuM5000 are powered by 3.3 V. The ADuM5000 generates an isolated 3.3 V, which is used to supply power to the VDD2 pin (Pin 8) of the ADuM1250.

A 3-pin screw terminal connector, J22, is used for easy access to the SDA (Pin 1 of J22), SCL (Pin 2 of J22), and I2C_ISO_GND (Pin 3 of J22) signals.

The ADuM5000 contains isoPower technology that uses high frequency switching elements to transfer power through the transformer. Special care must be taken during PCB layout to meet emissions standards. See the AN-0971 Application Note, Recommendations for Control of Radiated Emissions with isoPower Devices, for board layout recommendations.

1064

9-00

7

GND

3.3V I2C_ISO_3.3V

I2C_ISO_GND

I2C_ISO_GND

3.3V

GND I2C_ISO_GND

I2C_ISO_3.3V

GND

3.3V

I2C_ISO_GND

I2C_ISO_3.3V

3.3V

GND I2C_ISO_GND

I2C_ISO_3.3V

SDA1SCL1

U18

ADuM1250

VDD11

SDA12

SCL13

GND14

GND25

SCL26SDA27

VDD28

C16810uF

C1730.01uF

C17110uF

R73120R

U19

ADuM5000

VDD11

GND12

NC13RCIN

4

RCOUT5

RCSEL6

VDD17

GND18 GNDISO

9

VISO10

NC211

NC312

VSEL13

NC414

GNDISO15

VISO16

C1660.1uF

R74120R

C1720.01uF

C1690.1uF

C1670.1uF

J22

SCREW_3

1

2

3

C1700.1uF

Figure 7. ADuM1250 and ADuM5000 Isolated I2C Implementation
















Rev. 0 | of 20

ISOLATED SPI Two isolated SPI ports are implemented using the ADuM3401, the ADuM3402 iCoupler signal isolators, and the ADuM5000 isoPower isolated dc-to-dc converter. The isolated SPI0 imple-mentation on the ezLINX hardware uses the ADuM3401. The ADuM3401 connects to SPI0 of the Blackfin ADSP-BF548 and is used to isolate the SCLK, MISO, SSEL1, and MOSI lines. The ADuM3402 is used for isolating the SPI slave select lines. Figure 8 shows a circuit diagram of the implementation of isolated SPI1 using the ADuM3401, ADuM3402, and ADuM5000 on the ezLINX hardware.

The isolated SPI2 implementation on the ezLINX hardware uses the ADuM3401. The ADuM3401 connects to SPI2 of the ADSP-BF548 and is used to isolate the SCLK, MISO, SSEL1, and MOSI lines. The ADuM3402 is used for isolating the SPI slave select lines. Figure 9 shows a circuit diagram of the implementation of the isolated SPI2 using the ADuM3401, ADuM3402, and ADuM5000 on the ezLINX hardware.

The VDD1 pin (Pin 1) of the ADuM3401 and ADuM3402 and the VDD1 pins (Pin 1 and Pin 7) of the ADuM5000 are powered by 3.3 V. The ADuM5000 generates an isolated 3.3 V, which is used to supply power to the VDD2 pin (Pin 16) of the ADuM3401 and ADuM3402.

Two 7-pin screw terminal connectors, J10 and J25, are used for easy access to the SPISCK (Pin 1 of J10 and J25), SPIMOSI (Pin 2 of J10 and J25), SPISEL1/SPISS (Pin 3 of J10 and J25), SPIMISO (Pin 4 of J10 and J25), SPISEL2 (Pin 5 of J10 and J25), SPISEL3 (Pin 6 of J10 and J25), and SPI_ISO_GND (Pin 7 of J10 and J25) signals.

To connect the isolated SPI0 as a master, connect Jumpers JP5, JP7, JP9, JP11, JP13, JP15, JP21, and JP36 while leaving Jumpers JP6, JP8, JP10, JP12, JP14, JP16, JP20, and JP37 open (see the Warnings section). To connect the isolated SPI0 as a slave, connect Jumpers JP6, JP8, JP10, JP12, JP14, JP16, JP20, and JP37 while leaving Jumpers JP5, JP11, JP13, JP15, JP21, and JP36 (see the Warnings section).

Table 1. Isolated SPI0 Connections Jumper SPI0 Master SPI0 Slave

JP5 Connect Open JP6 Open Connect JP7 Connect Open JP8 Open Connect JP9 Connect Open JP10 Open Connect JP11 Connect Open JP12 Open Connect JP13 Connect Open JP14 Open Connect JP15 Connect Open JP16 Open Connect JP20 Open Connect JP21 Connect Open JP36 Connect Open JP37 Open Connect

To connect the isolated SPI2 as a master, connect Jumpers JP22, JP24, JP26, JP28, JP30, JP32, JP35, and JP38 while leaving Jumpers JP23, JP25, JP27, JP29, JP31, JP33, JP34, and JP39 open (see the Warnings section). To connect the isolated SPI2 as a slave, connect Jumpers JP23, JP25, JP27, JP29, JP31, JP33, JP34, and JP39 while leaving Jumpers JP22, JP24, JP26, JP28, JP30, JP32, JP35, and JP38 open (see the Warnings section).

Table 2. Isolated SPI2 Connections Jumper SPI2 Master SPI2 Slave

JP22 Connect Open JP23 Open Connect JP24 Connect Open JP25 Open Connect JP26 Connect Open JP27 Open Connect JP28 Connect Open JP29 Open Connect JP30 Connect Open JP31 Open Connect JP32 Connect Open JP33 Open Connect JP34 Open Connect JP35 Connect Open JP38 Connect Open JP39 Open Connect


Warnings

JP20 and JP21

JP20 and JP21 should never both be connected because doing so will create a short circuit between 3.3 V and GND.

JP34 and JP35

JP34 and JP35 should never both be connected because doing so will create a short circuit between 3.3 V and GND.




























Rev. 0 | of 20

1064

9-00

8

GND

GND

3.3V

3.3V

GND

3.3V SPI_M_ISO_3.3V

SPI_M_ISO_GND

GND

3.3V SPI_M_ISO_3.3V

SPI_M_ISO_GND

SPI_M_ISO_3.3V

SPI_M_ISO_3.3V

SPI_M_ISO_GND

SPI_M_ISO_GND

GND

3.3V SPI_M_ISO_3.3V

SPI_M_ISO_GNDGND

3.3V

SPI_M_ISO_GND

SPI_M_ISO_3.3V

SPI_M_ISO_GND

3.3V

GND

3.3V

3.3V

SPI0MISO

SPI0SCK

#SPI0SEL1

SPI0MOSI

#SPI0SEL2

#SPI0SEL3

#SPI0SS

+ +JP13

C1810.1uF

C17910uF

R10610K

+ +JP14

+ +JP5

C1830.1uF

R7633R

++ JP21

U22

ADuM5000

VDD11

GND12

NC1 3RCIN4

RCOUT5

RCSEL6

VDD17

GND18 GNDISO 9

VISO 10

NC2 11NC3 12

VSEL 13

NC4 14

GNDISO 15

VISO 16

J10

SCREW_7

1

2

3

4

5

6

7

+ +JP7 + +

JP6

C1740.1uF

+ +JP11

U20

ADuM3401

VDD11

GND12

VIA3VIB4VIC5

VOD6

VE17

GND18 GND2 9

VE2 10

VID 11VOC 12VOB 13VOA 14

GND2 15

VDD2 16

R7733R

+ +JP15

U21

ADuM3402

VDD11

GND12

VIA3

VIB4

VOC5

VOD6

VE17

GND18 GND2 9

VE2 10

VID 11VIC 12VOB 13VOA 14

GND2 15

VDD2 16

+ +JP8

R2333R

C1770.1uF

C1750.1uF

+ +JP12

C1800.1uF

+ +JP16

+ +JP9

++ JP37

++ JP36

C1780.1uF

++ JP20

C1820.1uF

+ +JP10

C17610uF

R10710K

R2433R

R7533R

Figure 8. ADuM3401, ADuM3402, ADuM5000 Isolated SPI1 Implementation





Rev. 0 | of 20

1064

9-00

9

SPI_S_ISO_3.3V

GND

3.3V SPI_S_ISO_3.3V

SPI_S_ISO_GND

GND

3.3V SPI_S_ISO_3.3V

SPI_S_ISO_GND

GND

3.3V

SPI_S_ISO_GND

SPI_S_ISO_3.3V

GND

GND

3.3V

3.3V

3.3V

GND

SPI_S_ISO_GND

SPI_S_ISO_3.3V

SPI_S_ISO_GND

SPI_S_ISO_GND

GND

3.3V

SPI_S_ISO_GND

SPI_S_ISO_3.3V

3.3V

3.3V

SPI2SCK

SPI2MISO

SPI2MOSI

#SPI2SS

#SPI2SEL1

#SPI2SEL2

#SPI2SEL3

+ +JP23

C1930.1uF

C1910.1uF

+ +JP33

+ +JP24

C1940.1uF

U42

ADuM3401

VDD11

GND12

VIA3VIB4VIC5

VOD6

VE17

GND18 GND2 9

VE2 10

VID 11VOC 12VOB 13VOA 14

GND2 15

VDD2 16

J25

SCREW_7

1

2

3

4

5

6

7

R10233R

+ +JP28

+ +JP25

++ JP38

C19210uF

R10333R

+ +JP29

+ +JP26

C19510uF

C1960.1uF

C2340.1uF

R10810K

++ JP35

R10433R

++ JP39

+ +JP30

R10133R

U43

ADuM3402

VDD11

GND12

VIA3VIB4

VOC5VOD6

VE17

GND18 GND2 9

VE2 10


GND2 15

VDD2 16

++ JP34

+ +JP27

R10533R

R10910K

+ +JP31

U25

ADuM5000

VDD11

GND12

NC1 3RCIN4RCOUT5

RCSEL6

VDD17

GND18 GNDISO 9

VISO 10

NC2 11NC3 12

VSEL 13

NC4 14

GNDISO 15

VISO 16

C1970.1uF

+ +JP22

C2350.1uF

C1900.1uF

+ +JP32

Figure 9. ADuM3401, ADuM3402, ADuM5000 Isolated SPI2 Implementation





Rev. 0 | of 20

ISOLATED LVDS The isolated LVDS port is implemented using the ADuM3442 iCoupler signal isolator, the ADN4664 dual LVDS receiver, the ADN4663 dual LVDS transmitter, and the ADuM5000 isoPower isolated dc-to-dc converter. The ADuM3442 is connected to SPORT2 of the ADSP-BF548. Figure 10 shows a circuit diagram of the implementation of the isolated LVDS using the ADuM3442, ADN4663, ADN4664, and ADuM5000 on the ezLINX hardware.

The VDD1 pin (Pin 1) of the ADuM3442 and the VDD1 pin (Pin 1 and Pin 7) of the ADuM5000 are powered by 3.3 V. The ADuM5000 generates an isolated 3.3 V, which is used to supply power to the

VDD2 pin (Pin 16) of the ADuM3442, the VCC pin (Pin 1) of the ADN4663, and the VCC pin (Pin 8) of the ADN4664.

A 32-pin header connector is used for easy access to the isolated LVDS signals.





















Rev. 0 | of 20

1064

9-01

0

LVDS_ISO_GND

LVDS_ISO_3.3V_1

LVDS_ISO_GND

LVDS_ISO_GND

LVDS_ISO_3.3V_2

LVDS_ISO_3.3V_2

LVDS_ISO_GND

LVDS_ISO_GND

LVDS_ISO_3.3V_1

LVDS_ISO_3.3V_1

LVDS_ISO_GND

LVDS_ISO_GND

LVDS_ISO_3.3V_2

LVDS_ISO_3.3V_1

GND

3.3V

GND

GND

3.3V

3.3V

LVDS_ISO_GND

LVDS_ISO_3.3V_1

LVDS_ISO_GND

LVDS_ISO_3.3V_2

LVDS_ISO_GND

LVDS_ISO_3.3V_2

LVDS_ISO_GND

LVDS_ISO_3.3V_1

GND

3.3V

LVDS_ISO_GND

LVDS_ISO_3.3V_2

GND

LVDS_ISO_3.3V_13.3V

LVDS_ISO_GND

GND

3.3V LVDS_ISO_3.3V_1

LVDS_ISO_GND

GND

LVDS_ISO_3.3V_23.3V

LVDS_ISO_GND

GND

3.3V LVDS_ISO_3.3V_2

LVDS_ISO_GND

LVDS_ISO_GND

DR2PRIDR2SEC

DT2PRIDT2SEC

RSCLK2RFS2

TSCLK2TFS2

C2050.1uF

U28

ADN4663

VCC

1

DIN12

DIN23

GN

D4

DOUT2- 5DOUT2+ 6

DOUT1+ 7

DOUT1- 8

U32

ADuM5000

VDD11

GND12

NC1 3RCIN4RCOUT5

RCSEL6

VDD17

GND18 GNDISO 9

VISO 10

NC2 11NC3 12

VSEL 13

NC4 14

GNDISO 15

VISO 16

R82100R

U31

ADN4664

RIN1- 1RIN1+ 2

RIN2+ 3

RIN2- 4GN

D5

ROUT26

ROUT17 VCC

8

C2100.1uF

C2080.1uF

C2020.01uF

C2070.1uF

C2030.1uF

U34

ADuM5000

VDD11

GND12

NC1 3RCIN4RCOUT5

RCSEL6

VDD17

GND18 GNDISO 9

VISO 10

NC2 11NC3 12

VSEL 13

NC4 14

GNDISO 15

VISO 16

C2130.1uF

U29

ADN4663

VCC

1

DIN12

DIN23

GN

D4

DOUT2- 5DOUT2+ 6

DOUT1+ 7

DOUT1- 8

C2110.1uF

C2090.1uF

C2160.1uF

U27

ADuM3442

VDD11

GND12

VIA3VIB4

VOC5VOD6

VE17

GND18 GND2 9

VE2 10


GND2 15

VDD2 16

C2060.01uF

R83100R

C2140.1uF

C2190.1uF

C2170.1uF

R81100R

C2040.01uF

C21210uF

C1990.1uF

C2200.1uF

C2010.1uF

C2000.01uF

C21510uF

R84100R

J24

Header_32

13579

1113 14

24681012

15 1617 1819 2021 2223 2425 2627 2829 3031 32

C21810uF

U30

ADN4664

RIN1- 1RIN1+ 2

RIN2+ 3

RIN2- 4GN

D5

ROUT26

ROUT17 VCC

8

U26

ADuM3442

VDD11

GND12

VIA3VIB4

VOC5VOD6

VE17

GND18 GND2 9

VE2 10


GND2 15

VDD2 16

C1980.1uF

C22110uF

Figure 10. ADuM3442, ADN4663, ADN4664, and ADuM5000 Isolated LVDS Implementation






Rev. 0 | of 20

POWER INPUT An ac-to-dc desktop power supply is used to supply 7.5 V input to the J1 barrel connector on the ezLINX hardware. This supply connects to the UNREG_IN node of the circuit through a protection circuit as shown in Figure 11.

3.3 V POWER SUPPLY The ADP1864 constant frequency, current-mode, step-down dc-to-dc controller is used with an external P-channel MOSFET to generate the regulated 3.3 V power supply for the ezLINX hardware. The circuit implementation of the 3.3 V power supply is shown in Figure 12.

1064

9-01

1

GND

GNDPWR_SH_GND

UNREG_IN

PWR_SH_GND

F15A

L1190R

1

4

2

3

D2MBRS540T3G

FER1600R

D9SMBJ24CA

J1

PWR CONN

32

1

FER2600R

C11nF

C21nF

Figure 11. Power Input

1064

9-01

2

UNREG_IN

A_GND P_GND GND

P_GND

A_GND

A_GND

P_GND P_GND P_GND

3.3V

GNDP_GNDR4255K

C310uF

C568pF

L22.5uH

C6220uF

D3MBRS540T3G C7

4.7uF

R10.05RU1

ADP1864

COMP1

AG

ND

2

FB3

CS4

IN5

PGATE6

C4470pF

R224.9K

U2

SI4411DY

1234

5678

W1

COPPER4A

TP13.3V

TP2GND

C2450.01uF

R380.6K

W2

COPPER

Figure 12. 3.3 V Power Supply


Rev. 0 | of 20

1.2 V, 2.5 V, AND 5 V POWER SUPPLIES A P-channel MOSFET is used to regulate the 3.3 V input to 1.2 V (see Figure 13). The ADP1706 linear regulator is used to regulate the 3.3 V input to 2.5 V (see Figure 14). The ADP3335

low dropout regulator is used to regulate the UNREG_IN input to 5 V (see Figure 15).

1064

9-01

3

3.3V

GND GND

1.2V

GND

VROUT

D4

ZHCS1000C9

100uF

U3

FDS9431A

1

2

3

4

5

6

7

8

TP3

1.2V

C10

10uF

L3

10uH

C11

0.1uF

C8

100uF


1064

9-01

4

2.5V

GND

3.3V

GND GNDGND GND

U39

ADP1706

EN1

GND2

IN3

IN4 OUT

5

OUT6

SENS7

SS8

EPEP

C232

4.7uF C233

4.7uF

TP62.5V

C231

10nF


1064

9-01

5

5V

GND

UNREG_IN

GND GND

U38

ADP3335

OUT1

OUT2

OUT3

GND4

NR5

SD6

IN7

IN8

C229

1uF

C230

1uF

TP5

5V

Figure 15. 5 V Power Supply

http://www.analog.com/ADP1706

http://www.analog.com/ADP3335


Rev. 0 | of 20

EXTENDER CONNECTOR The Hirose FX8-120P-SV(91) extender connector is used for daughter board connections. This allows additional functionality to be added to the ezLINX hardware. Figure 16

shows the circuit implementation of the J23 and J26 extender connectors. Connector J26 is a 3-pin header connector that allows the CAN1 signals of the ADSP-BF548 to be routed to an external daughter board.

1064

9-01

6

GND GND

3.3V

GND

GND

SCL0SDA0

DR3PRIDR3SEC

DT3PRIDT3SEC

RSCLK3

RFS3

TSCLK3

TFS3

PC8 PC9PC10 PC11PC12 PC13

PPI0_D0PPI0_D1PPI0_D2PPI0_D3PPI0_D4PPI0_D5

PPI0_D6PPI0_D7PPI0_D8PPI0_D9PPI0_D10PPI0_D11PPI0_D12PPI0_D13

PPI0_D14PPI0_D15PPI0_D16PPI0_D17PPI0_D18PPI0_D19PPI0_D20PPI0_D21PPI0_D22PPI0_D23

PPI0_CLKPPI0_FS1PPI0_FS2

TMR10TMR8 TMR9

LAN_IRQ/UART0RX UART0TX

PD12 PD13

#SPI1SEL1#SPI1SEL2#SPI1SEL3

SPI1SCK

SPI1MOSISPI1MISO

#SPI1SS

BMODE1#HIROSE_RESETCAN1RXCAN1TX

PC5PC6

PC7

J26

CON3

123

J23

HIROSE

VIN1 NC12 GND3 GND4 USB_VBUS5 GND6 PAR_D237 PAR_D218 PAR_D199 PAR_D17

10 GND11 PAR_D1412 PAR_D1313 PAR_D1114 PAR_D915 PAR_D716 GND17 PAR_D518 PAR_D319 PAR_D120 PAR_RD21 PAR_CS22 GND23 PAR_A324 PAR_A125 PAR_FS326 PAR_FS127 GND28 SPORT_DR329 SPORT_DR230 SPORT_DR131 SPORT_DT132 SPORT_DT233 SPORT_DT334 SPORT_INT35 GND36 SPI_SEL_B37 SPI_SEL_C38 SPI_SEL1/SPI_SS39 GND40 SDA_141 SCL_142 GPIO043 GPIO244 GPIO445 GND46 GPIO647 TMR_A48 TMR_C49 NC250 NC351 GND52 NC453 NC554 NC655 EEPROM_A056 NC757 GND58 UART_RX59 RESET_IN60

BMODE161

UART_TX62

GND63

NC864

NC965

NC1066

NC1167

NC1268

GND69

NC1370

NC1471

TMR_D72

TMR_B73

GPIO774

GND75

GPIO576

GPIO377

GPIO178

SCL_079

SDA_080

GND81

SPI_CLK82

SPI_MISO83

SPI_MOSI84

SPI_SEL_A85

GND86

SPORT_TSCLK87

SPORT_DT088

SPORT_TFS89

SPORT_RFS90

SPORT_DR091

SPORT_RSCLK92

GND93

PAR_CLK94

PAR_FS295

PAR_A096

PAR_A297

GND98

PAR_INT99

PAR_WR100

PAR_D0101

PAR_D2102

PAR_D4103

GND104

PAR_D6105

PAR_D8106

PAR_D10107

PAR_D12108

GND109

PAR_D15110

PAR_D16111

PAR_D18112

PAR_D20113

PAR_D22114

GND115

VIO(+3.3V)116

GND117

GND118

NC15119

NC16120

R71100K

Figure 16. Extender Connector Using Hirose FX8-120P-SV(91)



Rev. 0 | of 20

RS-232 CONSOLE The RS-232 console connector is used for accessing the console of the uClinux kernel running on the ADSP-BF548 processor. It uses the ADM3202 RS-232 line driver and receiver to connect to UART1 of the ADSP-BF548. The RS-232 signals connect to a

DB-9 connector, J4. A circuit implementation of the RS-232 console is shown in Figure 17.

The RS-232 console is used to directly access the uClinux kernel running on the ADSP-BF548. When the console is connected to a RS-232 port on the PC, the kernel can be accessed through a terminal program.

1064

9-01

7

3.3V

GNDGNDGND

3.3V

3.3V

3.3V

GND

3.3V

GND

UART1TX

UART1RX

#UART1RTS

#UART1CTS

U12

ADM3202

GN

D15

T1IN11

T2IN10

R1IN13

R2IN8

C1+1

C1-3

C2+4

C2-5 V+

2

V-6

VCC

16

T1OUT14

T2OUT7

R1OUT12

R2OUT9

R5810K

C1140.1uF

R5533R

C1120.1uFR57

10K

J4

DB9

594837261

10

11

C1150.1uF

R5610K

C1110.01uF

C1130.1uF

Figure 17. RS-232 Console Implementation






Rev. 0 | of 20

LEDs There are 10 LEDs on the ezLINX evaluation board. The red LED6 illuminates to indicate when the reset button is being pressed. The orange LED10 illuminates to indicate when the isolated USB port is connected to a USB port on the PC. The green LED7 illuminates to indicate when the board is powered.

The orange LED1 illuminates to indicate when the uClinux kernel and application finishes booting up.

Table 4 describes the functionality and connections of the LEDs for the ADSP-BF548 and other circuitry.

Table 3. LED ADSP-BF548 Port Function LED1 PD6 Illuminates when the uClinux kernel and application finishes booting up. This LED can also be used

as a general-purpose indicator that can be turned on and off through software. LED2 PD7 General-purpose indicator that can be turned on and off through software. LED3 PD8 General-purpose indicator that can be turned on and off through software. LED4 PD9 General-purpose indicator that can be turned on and off through software. LED5 PD10 General-purpose indicator that can be turned on and off through software. LED6 PD11 General-purpose indicator that can be turned on and off through software. LED7 Not Applicable Illuminates when the 3.3 V power supply is available. LED8 Not Applicable Illuminates when the reset button is pressed. LED10 Not Applicable Illuminates when the VBUS voltage from the USB host is connected.



Rev. 0 | of 20

JUMPER CONFIGURATIONS

Table 4. Interface Configuration Jumpers Fitted Jumpers Open RS-485/RS-422 Half-duplex configuration JP3, JP4, JP40 Not applicable Full-duplex configuration Not applicable JP3, JP4, JP40 120 Ω termination JP19 Not applicable RS-232 Loopback TOUT1 to RIN1 JP2 Not applicable CAN Split terminate the bus with 120 Ω and a common-mode 47 nF

capacitor JP17, JP18 Not applicable

No termination Not applicable JP17, JP18 SPI0 Master mode JP5, JP7, JP9, JP11,

JP13, JP15, JP20,1 JP36

JP6, JP8, JP10, JP12, JP14, JP16, JP21,1 JP37

Slave mode JP6, JP8, JP10, JP12, JP14, JP16, JP21, JP37

JP5, JP7, JP9, JP11, JP13, JP15, JP20, JP36

SPI2 Master mode JP22, JP24, JP26, JP28, JP30, JP32, JP35,2 JP38

JP23, JP25, JP27, JP29, JP31, JP33, JP34,2 JP39

Slave mode JP23, JP25, JP27, JP29, JP31, JP33, JP34, JP39

JP22, JP24, JP26, JP28, JP30, JP32, JP35, JP38

1 Warning: JP20 and JP21 should never both be connected because doing so will create a short circuit between 3.3 V and GND. 2 Warning: JP34 and JP35 should never both be connected because doing so will create a short circuit between 3.3 V and GND.


Rev. 0 | of 20

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG10649-0-8/12(0)

www.analog.com

ez iCoupler Isolated Interface Development Environment€¦ · Plug and play system evaluation ....

Documents

Transcript of ez iCoupler Isolated Interface Development Environment€¦ · Plug and play system evaluation ....