EXTRA Final Report2 Contents 1. Introduction 3 2. Work package 1: Fabrication of SOI devices with...

INFORMATION SOCIETY TECHNOLOGIES(IST)

PROGRAMME

EXTRA

Final Report

Project acronym: EXTRAProject full title: Extremely fast silicon transistor based on carrier velocitymodulationContract no.: IST-2001-38937Duration: 12 monthsReport covering period: 1.1.2003-31.12.2003Classification: InternalDate of preparation: 12 January 2004

Project Coordinator: Prof. Jouni Ahopelto, VTTPartners: UGR, IIS

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Summary

This one-year Assessment Project focused on realisation and demonstration of velocitymodulation operation in silicon-based devices. Transistors operating in velocity modulationmode (VMT) have a promise for very high operation speed. The project concentrated onverifying the essential requirements for velocity modulation: a) to switch the electron gasbetween the top and bottom interface in a thin SOI channel without changing the carrierdensity in the channel and b) to create large enough mobility difference between the top andbottom interface of the SOI channel.

The project included fabrication and characterisation of devices on silicon-on-insulator (SOI)substrates, and simulation of the devices by one electron and ensemble Monte Carlosimulations. In addition to the original Work Plan, investigations on phonon confinement inthin SOI films were carried out.

The main results are:

� The first low temperature transport data measured from single and dual gate devices withsub-20 nm SOI channel.

� The dual gate devices showed clearly the predicted increase in room temperature mobilitydue to volume inversion.

� The first demonstration of velocity modulation in SOI devices at room temperature.

� Monte Carlo simulations performed on realistic device configuration show that theintrinsic speed of a VTM is well above 500 GHz.

� For the first time low frequency confined acoustic phonons have been observed in thinSOI films.

The results above show that the velocity modulation concept can be implemented into silicondevices by utilising SOI substrates, and very high operation speeds can be obtained. Theresults also indicate that there remain lots of interesting phenomena to be investigated insilicon structures.

The groups and persons involved in the EXTRA consortium were:

VTT Information Technology, device fabrication and characterisationJ. Ahopelto, co-ordinatorM. Prunnila, K. Henttinen, M. Markkanen

University of Granada, simulation and modellingF. GamizA. Roldan, J. B. Roldán, C. Sampedro

University of Tokyo, interpretation of resultsH. Sakaki

And as informal collaborator:Paul Sabatier University, Raman measurements to investigate confinement of phononsC. M. Sotomayor Torres (on leave from the University of Wuppertal)

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Contents

1. Introduction 3

2. Work package 1: Fabrication of SOI devices with top and back gates 7

2.1 Fabrication and characterisation of ultra thin SOI MOSFETs 7

2.2 Fabrication and characterisation of dual gate SOI devices 11

3. Work package 2: Velocity modulation in SOI devices 15

3.1 Fabrication and characterisation of devices with mobility modulation 15

4. Extra for EXTRA: Confined phonons in thin SOI films 19

5. Work package 3: Simulation and theory 21

5.1 Self-consistent solution of Poisson and Schrodinger equations. 21

5.2 Electron mobility evaluation in VMT transistors 27

5.3 Ensemble Monte Carlo simulations of transient behaviour 32

5.4 Simulations on devices with experimentally realised roughness parameters 37

6. Deliverables and Assessment Criteria 39

7. Dissemination 41

8. Conclusions 42

References 43

Appendix 1: Annex 1: Description of Work

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1. Introduction

As a prelude to the Introduction we have a perspective from the inventor of the velocitymodulation transistor:

“Velocity Modulation Transistor: From Its Concept Generation, Through Existence-Proof Studies, Toward Practical Device Development

The application of a transverse electric field Ez perpendicularly to a semiconductorsurface induces the redistribution of electric charges in the semiconductor. This leads in mostcases to the change of the electron concentration N in the surface space charge region andresults in the modulation of both electric conductance G and electrical current I along thesemiconductors surface, as they are normally proportional to N. Field-effect transistors(FETs) are based on this mechanism and widely used as the core device in LSI andcommunication systems. The switching speed or the cut-off frequency fT of FETs is limitedby the transit time under the gate and can be improved by reducing the gate length L wellbelow 100nm. Indeed, fT of 562GHz has been reported by reducing L down to 25nm [1].

Since the fabrication of ultra-short gate FETs not only requires delicate and costlyprocessing steps but also induces various problems, known as short-channel effects, a newtype of transistor that is free from the transit time limitation is keenly desired. As an attemptto fulfil such a hope, a novel field-effect device, called velocity-modulation transistor (VMT),was proposed in 1982 [2]. In this device, a conductive channel is made in such a way that theapplied gate electric field Ez affects the spatial distribution n(z)=Φ(z)Φ*(z) of electrons so asto modulate the drift velocity vx of electrons flowing along the channel.

Although the basic feasibility of VMT effect was demonstrated both in a double-gate n-AlGaAs/GaAs heterojunction device [3] and a resonantly-coupled GaAs/AlGaAs doublequantum well device [4], their successful operation was limited to the low temperature regimebelow 77 K, as these VMTs relied on the modulation of the Coulomb scattering process bycharged impurities. To fully disclose the potential of VMT concept, one needs to exploreother possibilities by examining the use of alternative materials and structures as VMTchannels. In this project, ultra-thin SOI (silicon-on-insulator) structures are specificallyinvestigated, as the spatial distribution n(z) of electrons can be efficiently modulated in SOIstructures and the selective interaction of electrons with the top and the bottom interfaceregions are predicted to yield an efficient modulation of electron velocity even at roomtemperature [5].

References

[1] Y. Yamashita et al: IEEE Electron Devices Lett. 23 (2002) 573.[2] H. Sakaki: Jpn J. Appl. Phys. 21 (1982) L381.[3] K. Hirakawa and H. Sakaki: Phys. Rev. Lett. 54 (1985) 1279.[4] Y. Ohno, M. Tsuchiya and H. Sakaki: Electronics Lett. 29 (1993) 375, and Appl. Phys.

Lett. 62 (1993) 1952.[5] J. Ahopelto: Private communication

H. Sakaki (Jan. 4, 2004)”

In this one-year Assessment Project the main focus was to verify the essential conditions for avelocity modulation operation in SOI devices. The essential requirement is that the carrier

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distribution can be switched between a high mobility and low mobility channel withoutchanging the carrier density. It turned out during the project that a considerable amount ofnew experimental results were obtained. Not only on velocity modulation but also on thegeneral behaviour of carriers and phonons in thin SOI films. Nevertheless, the main issue inthe project has been the demonstration of velocity modulation in devices fabricated on SOIsubstrates. A more detailed description of the structure and operation of an SOI velocitymodulation transistor (VMT) can be found in the Project Work plan in Appendix 1: ”Annex1: Description of Work”.

In this project we first investigated the transport properties of ultra thin SOI devices. Thevelocity modulation concept will work only when the two inversion layers at the top andbottom interfaces in a thin conducting channel are coupled. This means that the thickness ofthe SOI channel must be below 20-30 nm. Before this project we did not have experience onthe fabrication or the properties of devices with thin channels. The first step was to fabricateand characterise single gate devices with extremely thin channel. The results are given inSection 2.1.

� This first part of the project produced the first low temperature transportdata measured from devices with sub-15 nm SOI channel.

The next step was to realise devices with back gates to investigate the behaviour of thecarriers in sub-20 nm dual gated channels. For this, we fabricated SOI wafers with highlydoped handle wafers. For the fabrication of the dual gate devices we used the same process asfor the ultra thin single gate devices. The results obtained from the dual gate devices are givenin Section 2.2.

� The dual gate devices showed clearly the predicted increase in roomtemperature mobility due volume inversion.

Finally, we developed a process to decrease the mobility at the other interface in a thin SOIchannel without affecting too much the mobility at the other interface. We managed todemonstrate current modulation over 90% at room temperature while keeping the carrierdensity constant in the channel. The velocity modulation results are given in Section 3.1.

� This is the first demonstration of velocity modulation in SOI devices.

All the experimental results are measured from Hall bars. In the dual gate devices the handlewafer acted as the back gate. It became clear early in the project that we will faceconsiderable difficulties in developing a fabrication process, including design, layout, processfor aligned back gates etc., for devices suitable to high speed measurements in a one yearproject, in addition to the work and results we show in this report. We then deliberatelydecided to concentrate to investigate, how the essential requirements for velocity modulationin SOI devices can be fulfilled.

In addition ot the experimental part, we had in the project extensive package of simulations tosupport the experimental work. The simulation package consisted of one electron MonteCarlo simulations to deduce the electron mobility and ensemble Monte Carlo simulations toobtain the switching time for the velocity modulation operation. As the main result we have

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found that the intrinsic speed exceeds one teraherz and is relatively immune to the channellength. The results of the simulations are given in the Chapter 3.

� In this project Monte Carlo simulations were performed for the first timeon realistic device configuration. The simulations show that the intrinsicspeed is well above 500 GHz.

Below is given the Work Package list of the project. As explained above, the Task 2.3 and,thus, the deliverable 2.3, as seen as experimental RF measurement from a device designed tooperate at 70 - 150 GHz, were omitted in the project.

WPno.

Task Title WPleader

Taskleader

Startmonth

Endmonth

Deliverable

1 Fabrication of SOIdevices with top andback gates

VTT 1 12

1.1 Fabrication of deviceswith sub-50 nm thickSOI channel with topand back gates

VTT 1.1

1.2 Verification ofswitching by transportmeasurements

IIS 1.2

2 Velocity modulation inSOI devices

VTT 1 12

2.1 Development of aprocess to decrease themobility at the otherinterface in a controlledway

VTT 2.1

2.2 Electricalcharacterisation ofdevices with differentmobilities at top andbottom interfaces

IIS 2.2

2.3 Characterisation of RFproperties of velocitymodulation devices

VTT 2.3

3 Simulation and theory UGR 1 12

3.1 Simulation of electrontransport in SOI VMTin stationary conditions

UGR 3.1

3.2 Ensemble Monte Carlosimulations

UGR 3.2

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A fortuitous extra for the project was that Prof. Sotomayor Torres accepted the challenge toinvestigate the properties of phonons in the thin SOI films. This led to the observation ofconfined acoustic phonons by Raman measurements. The results are briefly described inChapter 4.

� This is the first time that low frequency confined acoustic phonons havebeen observed in thin SOI films.

Below is shown the Pert chart of the actual flow of the work, showing how the activities werelinked and how they followed each other during the project. The starting month of each of theessential topic is given in the boxes. The description and results are given in more detail in thefollowing chapters.

The description of the work in the original project work plan can be found in the Appendix 1”Annex 1: Description of Work”.

Fabrication andcharacterisationof ultra thin SOIMOSFETs (M 1)

Fabrication andcharacterisationof dual gateSOI devices(M7)

Fabrication andcharacterisationof devices withmobilitymodulation(M 9)

Simulations(M1)

Extra forEXTRA:Confinedphonons (M2)

Fabrication ofSOI wafers withdoped handlewafer (M2)

Interfaces formobilitymodulation(M8)

Report (M12)

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2. Workpackage 1: Fabrication of SOI devices with top and back gates

The first issue in this WP was to develop a fabrication process for single gate SOI Hall barswith sub-20 nm thick channels and to explore the properties of these devices. The reason forthis was that we wanted to verify the suitability of the CMOS process at VTT for thefabrication of SOI devices and also to have a reference for the dual gate devices. The secondstep was to make SOI wafers with highly doped handle wafer for back gating and to realisedual gate Hall bars with thin SOI channels. The single gate devices were characterised by lowfield Hall measurements at 4.2 K. The dual gate devices were characterised by both low fieldHall measurements at 4.2 K and by capacitance and conductance measurements at roomtemperature.

2.1 Fabrication and characterisation of ultra thin SOI MOSFETs

SOI MOSFET Hall bars with a 100 × 1900 µm2 channel dimension and a 400 µm voltageprobe distance were fabricated on commercially available 100 mm unibond (100) SOI wafersproduced by smart-cut process. The nominal SOI film thickness was 340 nm and the buriedoxide was 400 nm thick. The initial boron acceptor concentration of the SOI was ~ 1015 cm-3.A large scale variation of ~5 nm of the SOI film thickness was already observable across thewafer before any process steps. The thickness fluctuation is probably due to the chemical-mechanical polishing step used in the smart-cut process. This intrinsic large scale non-uniformity enabled us to study the electronic properties of devices with a slightly differentchannel thicknesses. First, the SOI film was thinned by thermal oxidation and oxide strippingto a thickness of 180 nm. Then half of the wafer was covered by silicon nitride and the otherhalf was further thinned utilising local oxidation of silicon (LOCOS). A second LOCOS stepwas performed to reduce locally the thickness of the Hall bar channels. The Hall bar mesaswere patterned by UV lithography and dry etching. After implanting the contact areas, a 41nm-thick gate oxide was grown, followed by deposition of 250 nm-thick polysilicon gate.Finally, after patterning the Al bonding pads, the samples were annealed in H2/N2 ambient at425 °C for 30 min.

The process resulted in two sets of devices on the same wafer with channel thickness rangingfrom10 to 15 nm and from 56 to 61 nm, respectively. Prior to growth of the gate oxide wemapped the SOI film thickness by fitting theoretical reflectance to experimental scanningreflectance in a 480 - 800 nm wavelength range (~15 µm spot diameter). Cross-sectionalbright field and HR TEM images from the single gate devices are shown in Fig. 1. The TEManalysis showed that the SOI film is highly uniform (on a scale of few 100 µm) and free fromdefects.

Electronic properties of the SOI MOSFETs were characterised by low field Hall mobilitymeasurements in the magnetic field range of ±0.25 T at temperature of 4.2 K. Gate andsource-drain biasing, and Hall and longitudinal voltage measurement were performed withAgilent 4156 C precision semiconductor parameter analyser. The bias heating was alwayskept clearly below 0.8 nW. Differential buffer amplifiers were used for Hall and longitudinalvoltages. DC offsets were systematically removed from the data by applying at least fourdifferent source-drain bias values for each gate voltage (electron density) value. Fig. 2(a)shows the experimental mobility versus carrier density N measured from six different deviceson the wafer. The carrier density range in the Figure corresponds to 0 - 8 V gate voltagerange. The largest observed peak mobility µp ~1.9 m2/Vs. Fig. 2(b) presents µp vs. tSOIobtained from nine different devices.

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Fig.1. Upper panel: Cross-sectional bright field TEM image of a single gate device. Thethickness profile of the SOI film from the source to the 13 nm thick channel is clearly visible.Lower panel: HRTEM image of the SOI channel.

All the devices behave qualitatively similarly. They show the typical MOSFET behaviourwhere the mobility first increases at low carrier density, reaches a maximum value and thendecreases at high carrier density. This behaviour can be ascribed to well known elasticscattering mechanisms: Coulomb scattering which is most effective at low density, andinterface roughness scattering which is most effective at high density. The mobility of thethree devices show clear quantitative difference at low density: the devices from the side ofthe wafer that was thinned by the first LOCOS (tSOI < 15 nm) have substantially smaller lowdensity mobility than the ones on the thicker side (tSOI > 56 nm). Moreover, there aredifferences in the low density mobilities among the devices with the sub 15 nm channel. Thegeneral trend is that the thinner the SOI film the lower the low density mobility and µp, whereas the

BOX, SiO2100 nmgate oxide, SiO2

SOI, Si

n+ Poly-Si gate n+ source p- channel

5 nm

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gate oxide, SiO2

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0 1 2 3 40.6

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T = 4.2 K

Mob

ility

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s)

Carrier density, N (1016m-2)

(a)

�p

(b)

E2-4-1 60.0 1.90 30.0E2-4-2 14.5 1.58 30.0E3-3-2 60.0 1.89 21.0E3-5-2 13.5 1.57 21.0E3-8-2 13.5 1.54 15.0E4-8-1 59.0 1.89 6.0E4-8-2 13.0 1.51 6.0E8-4-1 57.0 1.89 -24.0E8-4-2 11.5 1.35 -24.0

Sample tSOI �p Y

11 12 13 14 15 50 55 60 651.2

1.4

1.6

1.8

2.0

(m2 /V

s)

�p

tSOI (nm)

Fig. 2. (a) Mobility as a function of carrier density for six different Hall bars measured at 4.2 K.The thickness of each of the devices is given in the legend. (b) Peak mobility as a function ofthe thickness of the SOI channel.

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mobility of all devices with thicker channel more or less coincides in the whole studied carrierdensity range. The SOI film thickness in the thick devices is clearly much larger than thewidth of the inversion layer and, therefore, the small SOI thickness variations do not affectthe mobility and these devices resemble bulk MOSFETs. However, in the devices with thinchannel the situation is different and the observed mobility degradation can be interpreted tobe due to increased scattering arising from the interface and charges of the BOX layer.

To support this interpretation we have calculated the electron wavefunctions � anddistribution n(z) in the SOI layer by solving Schrödinger and Poisson equations self-consistently. The calculations were performed for 12 subbands. However, the occupation ofsubbands other than the first is less than 4 % in the explored carrier density range at 4.2 K.Image charge and exchange-correlation contributions were not taken into account. Fig. 3shows normalised spatial fractions of carrier distribution f as a function of carrier density, andwavefunctions (the inset) of the first 2D sub-band at two different carrier concentrations for a12 nm-thick device. The fractions describe how a large portion of the electron gas occupiesthe half of the SOI film next to the gate oxide where z < tSOI/2 and the half next to BOX wherez > tSOI/2. As expected, a finite portion of the electron gas resides next to BOX at low carrierdensity for such a thin device. This can be seen more clearly from the wave function at N =7.2 × 1015 m-2 shown in the inset. The wave function has clearly a finite magnitude and slopeclose to the BOX. Thus, at low density we are no longer dealing with a simple inversion layerbut with an asymmetric SOI quantum well where the electrons are confined by the gate oxideand BOX. This intimate contact with the BOX naturally increases the scattering. At N = 2.8 ×1016 m-2 the magnitude and the slope of � close to BOX are practically zero and also f with z> tSOI/2 is negligible. Thus, at high carrier density the electron gas is pulled away from theBOX starting to resemble a bulk MOSFET inversion layer and the mobility is expected tocoincide with the devices with thick SOI channel. This is exactly what is seen in Fig. 2 wherethe mobility of all devices coincide above N ~2.5 × 1016 m-2.

0 1 2 3 40.01

0.1

1.0

z < tSOI

/2 z > t

SOI/2

Spat

ial f

ract

ion,

f

N (1016 m-2)

0.00 0.25 0.50 0.75 1.00

0.0

0.5

1.0

� (a

.u.)

z (tSOI)

BOX

gate

oxi

de

N = 2.8 x 1016 m-2

7.2 x 1015 m-2

T = 4.2 K

Fig. 3. Normalised spatial fraction of the electron distribution in the upper and lower half ofthe SOI channel as a function of the carrier density. The thickness of the channel is 12 nm.(Inset) Electron wave functions for the lowest sub-band at two different carrier densities.

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2.2 Fabrication and characterisation of dual gate SOI devices

Because wafers with a thin SOI channel and a highly doped handle wafer for back gatingwere not commercially available, we first had to make the substrates for the dual gate devicesin-house. The fabrication consisted of oxidation of commercial SOI wafers, bonding theoxidised wafers to highly doped silicon wafers and of removal the handle wafers of thecommercial SOI wafers by wet etching in TMAH. The doping concentration of the newhandle wafers is ~2E19 cm-3. The process resulted in substrates with a handle wafer suitablefor back gating. The 80 nm thick thermal oxide on top of the original SOI film formed theback gate oxide.

Hall bars were fabricated on these SOI wafers having the highly doped handle. Thefabrication process was similar to the process for the fabrication of the single gate devices, seefor details in Chapter 2.1. Cross-sectional TEM images of the dual gate Hall bar are shown inFig. 4. The thickness of the SOI channel is 18 nm. The top and bottom gate oxide in thesedevices have different thickness: the top oxide is 40 nm thick and the bottom oxide 80 nmthick. This leads to an asymmetric behaviour of the devices as a function of the top andbottom gate voltages.

Low temperature transport properties

The devices were characterised using similar low field Hall measurements at 4.2 K as thesingle gate devices, but now as a function of both top and bottom gate voltages. From themeasurements we deduced the carrier density, mobility and conductance. Contour plots of thecarrier density, mobility and conductance as a function of the top and bottom gate voltagemeasured from a dual gate device (sample VHB-E7-2-1, 17 nm thick SOI) are shown in Fig.5. The low temperature data show several interesting features. For example, the decrease inmobility when the electron gas is pulled away from the interface. This effect was discussedalready in Ref. [3], and the origin of this phenomenon is not yet clear.

The two interfaces have rather different maximum mobilities, as shown in Fig. 5 (d)in whichthe mobility of both of the interfaces are plotted as a function of carrier density. When thegate bias is such that the carriers reside at the top interface of the channel, the mobility isabout 1.9 m2/Vs, equal to the best mobilities measured from the single gate devices (seeSection 2.1). When the carries reside at the bottom interface, the mobility is only about 1.0m2/Vs. The reason for the different mobilities at the two interfaces is not clear. It may be aconsequence of the wafer bonding process, which can degrade the electrical properties of thebottom interface.

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Fig. 4. Cross-sectional TEM images of the dual gate Hall bar. Upper panel: Bright field TEMimage showing the 18 nm thick SOI channel, the 80 nm thick bottom gate oxide and the 40nm thick top gate oxide. The highly doped handle wafer acts as the back gate and the poly-Sias top gate. Lower panel: HRTEM image of the SOI channel, top gate oxide and the poly-Sitop gate.

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Fig. 5 (a) Carrier density as a function of the top and bottom gate voltage measured from a 17nm thick dual gate device at 4.2 K. (b) Contour plot of mobility as a function of top andbottom gates. (c) Contour plot of conductance. (d) Mobilities at the top and bottom interfaceas a function of carrier density.

0.10

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VHB-E7-2-1T = 4.2 K[N] = 1016 m-2

(a) (b)

(c)

[�] = m2/Vs

[Gs] = 10-41/�

0.0 0.5 1.0 1.5 2.0 2.5 3.00.0

0.5

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2.0 top channel, V

BG = 0 V

back channel, VTG

= 0 V

Mob

ility

[m2 /V

s]

Carrier density, N [1016m2]

(d)

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Room temperature properties of the dual gate devices

At room temperature the dual gate devices were characterised by conductance andcapacitance measurements as a function of the top and bottom gate voltages. Fig. 6 shows thecontour plots of conductance and mobility measured at room temperature from a 18 nm thickdevice (sample VHB-E7-4-2). In the plots the carrier density is also shown.

The plots clearly show that if one follows a constant density line, the conductance and, thus,the mobility is highest when the electron gas resides in the centre part of the SOI channel.When the carrier distribution is moved towards either of the interfaces, the conductance andmobility decrease. The effect can be explained by volume inversion occurring in a dual gatedevices [10]. The volume inversion leads to reduced scattering and increased mobility. Themaximum mobility measured at room temperature is 0.08 m2/Vs. The enhancement inconductance and mobility due volume inversion is 10-20 % for the positive gate biases.

Fig. 6. (a) Conductance and (b) mobility measured at room temperature from 18 nm thickdual gate device as a function of top and bottom gate voltages. The gray curves are constantcarrier density contours, labelled in bold. The contour plots show clearly that the mobility ishighest when the electron gas resides in the middle of the SOI channel.

3.8

4.0 4.24.4

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-5

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-5

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[�] = 0.01 m2/Vs[N] = 1016 m-2

0.1 1.0 2.0 3.04.0

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�max ~ 8.0

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VHB-E7-4-2T = 300 K[Gs] = 10-4 1/�[N] = 1016 m-2

(a)

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3. Work package 2: Velocity modulation in SOI devices

The aim in this WP was to develop means to modulate the mobility in the thin SOI channel ina controllable way and to demonstrate the velocity modulation operation. First, we had to findway to change the mobility of the carriers at the other interface without degrading too muchthe mobility at the other interface. The second step was to implement the developed processinto the dual gate fabrication process.

3.1 Fabrication and characterisation of devices with mobility modulation

We considered two different possibilities to degrade the mobility at the other interface and topreserve high enough mobility at the other. The first candidate was a shallow implantationusing heavy ions, i.e., arsenic to create high density of defects into the upper part of thechannel. We performed some simulations, and it turned out that it is not easy to achieve asteep enough damage profile in a thin SOI channel. Also, to prevent recrystallisation, no hightemperature process steps were allowed after the damage implantation. This would make thecompletion of the fabrication process very difficult. Consequently, we abandoned this option.The other possibility was to use oxidised polysilicon to create a rough top surface in thechannel, and we choose this option. AFM analysis gave 2 nm and 15 nm for the averageamplitude and correlation length of the resulting surface roughness, respectively.

Fabrication of Hall bars with velocity modulation

The Hall bars were fabricated on a similar wafer as the single and double gate devices. Thedifference in the fabrication was that we implemented the roughening step into the process.To avoid any leakage through the top gate dielectric, a 40 nm thick silicon nitride wasdeposited on top of the oxide. Cross-sectional TEM images of the device are shown in Fig. 7.The thickness of the SOI channel is 20 nm and the thickness of the bottom gate oxide is 80nm and the thickness of the top gate oxide-nitride stack is 80 nm. The roughness at the topinterface of the SOI channel is clearly visible in the HRTEM image. The amplitude of theroughness is about 2 nm and the correlation length 15 nm, as obtained also with AFM fromthe test structures.

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Fig. 7. TEM images of the VMT device. Upper panel: Bright field image showing the 20 nmthick SOI channel, the 80 nm thick bottom gate oxide and the 80 nm thick top gate oxide-nitride stack. Highly doped handle wafer acts and the bottom gate and the top poly-siliconforms the top gate. Lower panel: HRTEM image of the SOI channel. The roughness at theupper interface of the channel is clearly visible.

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Transport properties of the VMT structures

The transport properties of the VMT devices at room temperature were obtained usingcapacitance and conductance measurements. A contour plot of conductance measured from avelocity modulation Hall bar together with constant carrier density lines is shown in Fig. 8.From the plot it is clear that at constant carrier density the current can be modulated bymoving the electron distribution between the top and bottom interfaces. In Fig 9 is shown therelative modulation of mobility (or current) at different carrier densities. The relativemodulation exceeds 90 % at densities below 2E16 m-2. At higher densities the relativemodulation is smaller but still substantial. This is to our knowledge the first demonstration ofthe velocity modulation in silicon based devices. It is interesting to compare the conductancecurves with the results in Fig. 6 showing the enhancement of conductance and mobility duevolume inversion.

Fig. 8. Contour plot of conductance as a function of top and bottom gate voltages measured atroom temperature from a Hall bar designed for velocity modulation operation. The constantcarrier density lines with 1E16 steps are shown in gray. The absolute values for the carrierdensity are only suggestive due to high impedance of the channel at low densities which makethe capacitance measurements difficult. However, the relative changes are accurate.

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18

The threshold voltage of the Hall bar is rather high and the reason for this is not clear at themoment. One possibility may be a high density of interface and oxide charges in the layer ofoxidised polysilicon.

Fig. 9. Relative current/mobility modulation along constant carrier density lines as a functionof the top gate voltage. Left panel: carrier density regime 1.2 - 3.0E16 m-2(with step of0.2E16 from left to right). Right panel: carrier density regime 3.5 - 7.0E16 m-2 (with step of0.5E16 from left to right). The curves were deduced from the data in Fig. 8. The relativemodulation exceeds 90 % at densities below 2E16 m-2.

10 15 20

70

75

80

85

90

95

100

-4 -2 0 2 40

10

20

30

40

50

60

70

80

90

100

VTG [V] VTG [V]

�I, ��

[%]

19

4. Extra for EXTRA: Confined phonons in thin SOI films

It has been predicted that acoustic phonons will become confined in thin SOI films [11]. Theconfinement alters the dispersion of phonons, which affects the carrier scattering and the in-plane heat conduction in the thin SOI film. Both effects can become important in devices witha thin SOI channel. So far no clear experimental verification of such a confinement has beenreported. While fabricating single gate devices, samples were prepared for Raman scatteringmeasurements to investigate the possible phonon confinement. These measurements werecarried out by Prof. C. M. Sotomayor Torres at the Paul Sabatier University in Toulouse.

The sample structure is shown in Fig. 10. The original thickness of the SOI film had amonotonic variation, which remained after thinning the SOI film by thermal oxidation, thusmaking it possible to measure the phonon spectrum in layers with different thickness from asingle sample. Prior to the Raman measurements the thickness of the SOI film was carefullymeasured by ellipsometry across the sample to ensure the correct thickness values were usedin the interpretation of the results.

Fig 10. Schematic cross section of the sample fabricated for measuring the phonon spectrumby Raman spectroscopy. The size of the sample is 1.7 x 1.0 cm2. The thickness of the SOIfilm increases from 30 nm to 40 nm along the direction of the longer side of the sample.

Low frequency Raman scattering spectra were obtained in the near-back scatteringconfiguration at room temperature using a triple spectrometer equipped with a cooled photoncounter. The sample was held in vacuum to avoid air-related Raman signal. For excitation the413.1 nm line from a Krypton laser was used. A Raman spectrum recorded from a location onthe sample where the thickness of the SOI film is 30.5 nm is shown in Fig. 11. The confinedacoustic phonons manifest themselves as a series of low frequency oscillations withdecreasing amplitude and spacing with increasing wavenumber. The frequency of theseconfined phonons decreases with increasing silicon layer thickness.

20

Fig. 11. Low frequency Raman scattering of a 30.5 nm thick SOI film showing severalconfined phonons (black line). Simulation of light scattering by confined phonons using aphonon cavity model with a smoothly varying photo-acoustic coefficient.

21

5. Work Package 3: Simulation and theory

ObjectivesThe objective of this WP is to analyse the operation of a VMT by one electron and ensembleMonte Carlo simulations. The results will be used to optimise the device design in order tomaximise the current modulation and modulation speed.

5.1. Self-consistent solution of Poisson and Schroedinger equations.

Different structures, such as the ones shown in Fig. 12 have been studied at differenttemperatures:

(a)

(b)

Fig. 12. Simulated structures with aluminium upper gate (a) and with poly-Si upper gate (b). Iboth cases the bottom gate is made of Si highly doped (ND=2x1019cm-3).

The goal of this task is calculation of the electron mobility in the device when all the electronspopulate the high-mobility channel or the low-mobility channel. The geometrical andtechnological properties of the structure will be taken into account. The different scatteringmechanisms will be studied, and their influence on the electron mobility carefully analysed.The previous results show that the two channels at the opposite interfaces are in some way

n+ Gate B

n+ n+

SiO2

SiO2

Si - substrate

Aluminum Gate, Asource

drain

channel

n+ Gate B

n+ n+

SiO2

SiO2

Si - substrate

Polysilicon Gate, A

sourcedrain

channel

Gate A

22

coupled. The question to solve is whether the scattering mechanisms intentionally induced todegrade the mobility in the other channel, would also degrade the mobility of the electrons inthe channel at the opposite interface. Another important question is the influence of the driftelectric field on the population of the two channels, and of course on the mobility.

To shed light on these topics, Poisson and Schroedinger equations will be solved in thestructure, taking into account the voltages applied at each gate. For the sake of simplicity,calculations are made in the Hartree approximation. To solve Poisson's equation weconsidered a non-uniform adaptive mesh, employing an iterative-Newton scheme. The actualband-bending through the whole structure and the finite height of the barrier at the Si-SiO2interfaces were considered. A simple non-parabolic band model for the silicon was taken intoaccount assuming α=0.5 eV-1, where α is the parameter of non-parabolicity [1]. This limitedour study to low-electron energies (below 0.5 eV) . The electron effective masses wereassumed to be those of bulk silicon[2]. One may well question the use of effective-massapproximation for electronic states whose spatial extent is limited to a few atomic layers.However, on the one hand, it is claimed that four or five atomic layers are enough to recoverthe complete bulk bandstructure, and consequently, the same effective-mass-approximationparameters; on the other hand, as pointed out by Ando et al.[3], it is thought to be the lack ofknowledge about the physical parameters and uncertainties of the problem, rather than theeffective-mass approximation itself, that limits the accuracy of electron mobility calculations.A detailed description of the self-consistent solution of the Poisson and Schroedingerequations can be found elsewhere [4-7].

Fig. 13. Potential well and electron distribution for the structure with aluminium gate with (a)all the electrons in channel A (front channel) and (b) all the electrons in channel B (backchannel). (T=300K, Tox=65 nm, tSi=20 nm, tBox=180nm, NA,channel=1012cm-3)

Fig. 13 shows the potential distribution in the structure and the electron concentration for twosets of voltages applied to each gate, such as the inversion charge in the structure is the samein both cases, but with all the electrons populating channel A (Fig. 13(a)) and all the electronspopulating channel B (Fig. (13b)). We show that with a silicon thickness higher than 15nm itis possible to have two separated channels even for low inversion charge concentrations.

23

One of the keys of the operation of these VMT devices is that the total inversion charge mustkeep constant in the device. As the first device we have considered is not symmetric we haveperformed an exhaustive calculation of (VG1, VG2) pairs such as total inversion charge in thedevice keeps constant. These (VG1, VG2) define the lines shown in Fig. 14.

0 5 10 15 20 250

5

10

15

20

25

30

VG1 (V) (aluminun gate)

VG

2 (

V)

(pol

ysili

con

gate

)

0

1,500E12

3,000E12

4,500E12

6,000E12

7,500E12

9,000E12

1,050E13

1,200E13

Fig. 14. Contour plot of the total inversion charge in the device versus both gate voltages.T=300K. The front gate (VG1) is made of aluminium and the back gate (VG2) is made ofpolysilicon. (T=300K, Tox=65 nm, tSi=20 nm, tBox=180nm, NA,channel=1012cm-3)

24

05

1015 20 25

0

510

1520

2530

1E11

1E12

1E13

VG

2 (V)In

vers

ion

char

ge (c

m-2)


Fig. 15. Surface plot of the total inversion charge in the device versus both gate voltages.T=300K. The front gate (VG1) is made of aluminium and the back gate (VG2) is made ofpolysilicon.

0 5 10 15 20 250

5

10

15

20

25

30


VG

2 (V

) (p

olys

ilico

n ga

te)

0

1,125E12

2,250E12

3,375E12

4,500E12

5,625E12

6,750E12

7,875E12

9,000E12

Fig. 16. Contour plot of the inversion charge in the front channel of the device versus bothgate voltages. T=300K. The front gate (VG1) is made of aluminium and the back gate (VG2) ismade of polysilicon.

25

05

1015

2025

05

1015

2025

30

1E10

1E11

1E12

VG2 (V) (polysilicon gate)

Inve

rsio

n ch

arge

in fr

ont c

hann

el (c

m-2

)


Fig. 17. Surface plot of the inversion charge in the front channel of the device versus bothgate voltages. T=300K. The front gate (VG1) is made of aluminium and the back gate (VG2) ismade of polysilicon.

0 5 10 15 20 250

5

10

15

20

25

30


VG

1 (V

) (po

lysi

licon

gat

e)

0

5,000E11

1,000E12

1,500E12

2,000E12

2,500E12

3,000E12

3,500E12

4,000E12

Fig. 18. Contour plot of the inversion charge in the back channel of the device versus bothgate voltages. T=300K. The front gate (VG1) is made of aluminium and the back gate (VG2) ismade of polysilicon.

26

Low temperatures:

We have also obtained results at low temperatures showing that it is also possible to have allthe electrons in one channel (front channel) or in the other one (back channel) depending onthe set of voltages applied to each gate:

Fig 19. Potential well and electron distribution for the structure with front gate of polysilicongate at T=4.2K (tox=44 nm, tSi=17 nm, tBox=80nm, NA,channel=1012cm-3).

27

5.2. Electron mobility evaluation in VMT transistors

To study electron mobility behaviour in VMT inversion layers, we used a one-electron MonteCarlo simulator [4-5]

Phonon, surface-roughness and Coulomb scattering have been taken into account in this work.We used bulk electron-phonon scattering models considering acoustic deformation potentialscattering and intervalley scattering (both between equivalent and non-equivalent valleys).The coupling constants for the intervalley phonons and the acoustic deformation potential arethe same as in bulk silicon inversion layers [1-2]. The phonon-scattering rates for inversionlayers were deduced by using Price's formulation [8]. Here again, the use of bulk phonons isquestionable, as the presence of Si-SiO2 interfaces undoubtedly alters the dispersion of thephonons, their nature and their coupling to the electrons. Previous studies [9] accounting forthese effects in idealized conditions showed that phonon-limited mobility is reduced by 20 %or less [1] due to the presence of the Si/SiO2 interfaces. Nevertheless, if such idealizedconditions are relaxed, an even lower reduction is expected. For these reasons and due to thedifficulty in dealing with the effects of the interfaces on the phonon-scattering rate [1], [9], wehave assumed that the bulk phonons are not influenced by the layered structure. In any case,the presence of the two Si/SiO2 interfaces becomes more important as the silicon layerthickness is reduced. This effect is to be the object of future studies. Finally, the effect of SiO2polar-phonon remote scattering has also been ignored. In this simulation the electron energywas limited to 0.5 eV, since for higher electron energies the results obtained by the simulationare not likely to be very accurate, as a detailed bandstructure was not used. Accordingly, asthe silicon bandgap was set to 1.12 eV at room temperature (thus setting the energy thresholdfor the impact ionization process), impact ionization was not included.

Fig. 20. Electron mobility in a dual gate SOI device. This figure qualitatively compares quitewell with the experimental results in Fig. 6(b), showing the enhancement in mobility whenboth of the gates have positive bias.

First of all, we have considered a double gate silicon on insulator (DGSOI) device, and wehave evaluated the electron mobility in the structure as a function of the voltages applied to

µ (x 100 cm2/Vs)

28

each gate. The structure have the following parameters: T=300 K, Tox=65 nm, tSi=20 nm,tBox=180nm, NA,channel=1012cm-3. The results are shown in Fig 20.

To perform a deeper study of the electron mobility in a VMT transistor, a VMT structure withfront gate of aluminium (Fig 12(a)) with the following parameters has been assumed: T=300K, Tox=65 nm, tSi=20 nm, tBox=180nm, NA,channel=1012cm-3).

First of all, we have assumed that both Si-SiO2 interfaces are identically characterized, i.e. thesame interface-roughness parameters (Lfront=Lback=1.5nm, ∆front=∆back=0.185nm). We havecalculated the mobility of the electrons in both channels as shown in Fig. 21. As observed,electron mobility is the same in both channels, since both have the same scatteringparameters.

For the correct operation of a VMT transistor it is needed that one of the channels (high-µchannel) has an electron mobility much higher than the one corresponding to the otherchannel (low-µ channel). Therefore, if we want that the SOI structure of Figure 12 works as aVMT transistor , we need that the mobility in one of the channels is much lower than themobility in the other one. In the Assessment Criteria a factor of 5 was promised, i.e., µA/µB~5. To achieve this, we can think about degrading the electron mobility in one of the channelsby means of any scattering mechanism: Coulomb scattering due to charge trapped at theinterface or doping impurities in half of the structure, or a rough Si-SiO2 interface. However,we do not forget that the chosen mechanism to degrade the mobility of one of the channelsshould not degrade the electron mobility in the other one.

Fig. 21. (Squares) Electron mobility of electrons in the front channel (channel A) as afunction of the inversion charge concentration, assuming that all the electrons populate thischannel. (Circles) Electron mobility of electrons in the back channel (channel B) as a functionof the inversion charge concentration, assuming that all the electrons populate this channel.

Interface roughness

The first mechanism we have considered is a rougher Si-SiO2 interface in channel B (backchannel) which will be the low mobility channel. Fig. 22 shows the mobility in the frontchannel for two conditions (surface-roughness parameters) of the back interface

29

∆back =0.185 nm Lback=1.5nm soft interface (non-degraded) or ∆back =0.6 nm Lback=1.5nm rough interface (degraded)

In both cases, the front interface has been considered to be not degraded: ∆front=0.185nm,Lfront=1.5nm

Fig. 22. Mobility in the front channel for two conditions (surface-roughness parameters) ofthe back interface.

As observed the electron mobility in the front channel does not depend on the interfaceroughness parameters of the back channel. However, as observed in Fig. 23, the electronmobility in channel B (back channel) is strongly degraded mainly at high inversion chargeconcentrations:

Fig. 23. Mobility in the back channel for two conditions (surface-roughness parameters) ofthe back interface.

30

Fig. 24. Mobility ratio between high-mobility channel and low-mobility channel, when backchannel is degraded with a rough Si-SiO2 interface.

Interface charge

A different way to degrade the mobility in one of the channels is to use a high chargeconcentration trapped at the Si-SiO2 interface. Fig. 25 shows the electron mobility in bothchannels, when there is an interface trap concentration of Nit-back=5x1010 cm-2.

Fig. 25. (a) Mobility in front and back channels for two conditions (interface trapconcentration) of the back interface. (b) Mobility ratio.

In the case shown in Fig. 25, we can see that Coulomb scattering degrades the mobility curvesin both channels mainly at low inversion charge concentrations. In addition note that theseparation between both mobility curves is very small in this case, resulting in a mobility rationext to 1 regardless of the inversion charge concentration. Fig. 26 compares the electronmobility in the front channel when the back channel is non-degraded, and when weconsidered an interface trap concentration of Nit-back=5x1010 cm-2 in the back Si-SiO2interface.

31

Figure 26. Mobility in the front channel for two conditions (interface trap concentration) inthe back interface.

Interface roughness + interface charges

We have also considered the case in which both mechanisms are simultaneously applied. Fig.27 shows electron mobility in front and back channel, when both degradation mechanisms aresimultaneously taken into account:

Fig. 27. (left) Electron mobility in the front channel and in the back channel for a degradedback interface by a higher interface trap concentration (Nit,back =5x1010 cm-2 (degraded)) andby a rougher back interface (∆back =0.6 nm rough interface (degraded)). The front channelhas been considered to be non-degraded. (right) Mobility ratio.

32

For the sake of comparison, Fig. 27 (left) also shown in bold squares the electron mobility inthe front channel when there is no degradation in the back channel. Thus, we can observe theeffect of the degradation mechanisms of the back channel on the electron mobility in the high-mobility channel.

Fig. 28 shows the same results as in Fig. 28, but with a higher interface trap concentration inthe back Si-SiO2 interface (Nit,back =5x1011 cm-2):

Fig. 28. (left) Electron mobility in the front channel and in the back channel for a degradedback interface by a higher interface trap concentration (Nit,back =5x1011 cm-2 (degraded)) andby a rougher back interface (∆back =0.6 nm rough interface (degraded)). The front channelhas been considered to be non-degraded. (right) Mobility ratio.

As observed in Figs. 23, 27 and 28, the combination of a rougher interface and a higherinterface trap concentration allows a mobility in the back channel lower than the mobility inthe front channel. However, the mobility ratio, µA/µB, although increases as the inversioncharge concentration increases, may be too low. The simulations based on realistic devicestructure for VM operation (see Section 3.1) are described in Section 5.4 below.

5. 3 Ensemble Monte Carlo simulations of transient behaviour

In this Task the transient behavior of the device will be studied, i.e., the switching timebetween the two channels will be deduced from simulations. To achieve this, the one-electronMonte Carlo code developed in Task 3.1 of the project will be implemented into anEmsemble Monte Carlo (EMC) simulator. The structure will be optimised to reduce theswitching time, taking into account the best mobility ratio. The EMC simulator will also beused to evaluate the current in the structure.

As seen in Sections 5.1 and 5.2, quantum effects are important. However, the inclusion ofquantum effects in a EMC (Poisson+Boltzmann equations) is a huge task. Before facing thistask, we have considered as starting point a classical EMC scheme, i.e., where quantumeffects are ignored. This will give us an estimation for the switching behaviour.

33

The device structure was the following: The silicon channel thickness was considered to betSi=20nm. In the on-state the voltages applied to the gate were: VG-front=1.1 V, VG-back=0, whilein the off state VG-front=0 V, VG-back=1.1. To degrade the mobility in the back channel, we haveassumed that the lower half of the channel is strongly compensated with dopingconcentrations: ND=1021cm-3, NA-ND=1014cm-3, as shown in Fig. 29. We have evaluated thedrain current transients produced in the structure when the electrons which are initially in thefront channel are transferred to the back channel (on-off transition) and the opposite case (off-on transition), for different values of the channel length.

Fig. 29. Structure used to perform transient simulations.

The results are shown in Fig. 30. As observed, the device switches from one state to the otherstate in a time less than 1ps, regardless of the channel length. This means that the device havean intrisic cut-off frequency in the range of hundreds of GHz.

Fig. 30. Drain current transients in the VMT device shown in Fig. 18, for different values ofthe channel length.

Time (ps)

34

Following figures show the distribution of the charge in the structure of Figure 29 at differenttimes in the transition on-off.

37

5.4 Simulations on devices with experimentally realised roughness parameters

As detailed in Section 3.1, the option chosen experimentally to degrade the mobility in one ofthe channels, was to intentionally create a rough interface between Si and SiO2 in thatchannel. Figure 31 shows the electron mobility in each channel when one of the interfaces isvery rough (surface roughness parameters: ∆sr=2nm , Lsr=15nm). As seen in Figure 31,electron mobility in the degraded channel is very low in the whole range of inversion chargeconcentration. Although the mobility in the other channel (the one next to the non-degradedinterface) also decreases mainly at low inversion charge concentrations, for inversion chargeconcentrations of 5x1012cm-2 and higher, a ratio among the mobilities in both channels(µA/µB) higher than 40 is achieved. This exceeds by a factor of eight the value included in theAssessment Criteria.

Figure 31. Electron mobility in the front channel (middle curve) and in the back channel(lowest curve) for a degraded back interface by a rougher back interface (∆back =2.0 nm). Forthe sake of comparison the electron mobility in front channel, when there is no degradation, isalso shown (top curve).

To estimated the transient response, we have considered a VMT structure such as the oneshown in Figure 12(b), with a silicon thickness of 20nm. We have assumed that one of theinterfaces is rough, while the other one is kept non-degraded. We have applied the appropiatepolarization to both gates, so the total inversion charge in the structure is confined either inchannel A or in channel B. In both cases the total inversion charge is kept constant(Ninv=5x1012 cm-2). We have evaluated the transient response of this structure when thecharge is transferred from one channel to the other one, for different values of the channellength. The results are shown in Fig. 32.

38

-1.00-0.75-0.50-0.250.000.250.500.751.00

0 2 4 6 8-0.4

-0.2

0.0

0.2

0.4

0 2 4 6 8

Dra

in C

urre

nt (m

A/�m

)

LG=0.1�m

TSi=20nmVDS=0.2VNinv=5x1012cm-2

LG=0.2�m

TSi=20nm

Time (ps)

LG=0.6�m

TSi=20nm

LG=1.0�m

TSi=20nm

Figure 32. Transient response of a velocity modulation transistor (VMT) for different valuesof the channel length.

We observed that the switching time does not depend on the channel length. Based on thesimulations, devices with a 1 µm long are capable of switching at frequencies of hundreds ofGhz, or even Thz. The results fulfill the Assessment Criterium on verifying intrinsic speed of500 GHz by simulations.

39

6. Deliverables and Assessment Criteria

Deliverables

Below is given the Deliverables list of the EXTRA project. Based on the results shown in theprevious sections, we can easily tick most of the deliverables as OK. The only exception is theDeliverable 2.3 where we have put the tick in parenthesis since we do not have directexperimental results from RF measurements of VMTs. However, the simulations based on ourexperimental data and device structure show that the intrinsic operation speed of a device witha one micron long channel is expected to be in the range of several THz.

Deliverables list

Del.No.

Del. Name WPno.

Leadparticipant

Estimatedpersonmonths

Del.Type

Security Delivery Status

1.1 Devices with sub-50nm thick channels

1 VTT 4 R Pu M5 OK

1.2 Demonstration ofswitching between theinterfaces

1 IIS 2 R Pu M12 OK

2.1 Control of mobilitiesat the interfaces

2 VTT 3 R In M6 OK

2.2 Demonstration ofcurrent modulation

2 IIS 1 R Pu M12 OK

2.3 Demonstration ofincreased speed dueVM operation

2 VTT 1 R Pu M12 (OK)

3.1 MC simulations of DCbehaviour

3 UGR 6 R Pu M8 OK

3.1 EMC simulations oftransients

3 UGR 6 R Pu M12 OK

Assessment criteria

The following assessment criteria was included in the "Annex 1: Descrition of work":

"We can define the following criteria for the successful fulfilment of the project. The mostimportant criteria in this assessment project are the first two, which form the essentialconditions for realisation of a functioning velocity modulation transistor. The firstrequirement is essential for high speed operation and the second for large current modulation,i.e., gain.

1. Experimentally and theoretically define a condition (gate voltage bias window, SOI filmthickness) where the carriers can be switched between top and bottom interfaces in theSOI channel without modulating the total carrier concentration.

40

2. Find means to create large enough mobility difference between top and bottom interfacesin the SOI channel. The criterion is to reach a mobility ratio of at least 5 at 300 K (80 %current modulation).

3. Demonstration of increased operation speed due to velocity modulation mode incomparison to operation in conventional FET mode.

4. Making realistic calculations of velocity modulation in thin SOI films by Monte Carlosimulations and show that intrinsic speeds of 500 GHz are possible with a VMT.

5. RF measurements on a test device targeted for running at 70-150 GHz range.

Successful fulfiling of the first two criteria paves the way for the realisation of silicon VMT.The last three give information about the speed of a SOI VMT."

The first two criteria are clearly fulfilled, both experimentally and by simulations. The thirdcriterium is fulfilled based on results obtained by simulations. The fourth criterium is clearlyfulfilled. The fifth criterium is not fulfilled becaused we deliberately omitted the developmentof a fabrication process in this one year project for devices targeted for high speed RFmeasurements.

41

7. Dissemination

Part of the results have already been presented in conferences and submitted to journals.Below is the list of conference presentations and submissions

Journals:

M. Prunnila, J. Ahopelto and F. Gamiz, Electron Mobility in Ultrathin Silicon-on- Insulatorlayers at 4.2 K, Appl. Phys. Lett., accepted for publication.

M. Prunnila, J. Ahopelto and F. Gamiz, Low Temperature Transport Properties of Thin SOIMOSFETs, Superlattices and Microstructures, accepted for publication.

F. Poinsotte, C.M.Sotomayor Torres, J.Ahopelto, M.Prunnila, A.Zwick, V. Paillard,A.Mlayah, and J. Groenen, Modeling of confined acoustic phonons in thin silicon-on-insulator films, Superlattices and Microstructures, submitted.

Conference presentations:

C.M.Sotomayor Torres, M.Prunnila, J.Ahopelto, A.Zwick, A.Mlayah, and S.Zankovych,Phonons in Thin Silicon-on-Insulator Films (Keynote), Trends in Nanotechnology (TNT2003)Salamanca, Spain.

C.M.Sotomayor Torres, J.Ahopelto, M.Prunnila, A.Zwick, V. Paillard, A.Mlayah, F.Poinsotte and J. Groenen, Confined phonons in thin silicon-on-insulator films, NPMS6-SIMD4, November 30 - December 5 2003, Maui, Hawaii.

M. Prunnila, F. Gamiz, and J. Ahopelto, Low Temperature Transport Properties of Thin SOIFilms, NPMS6-SIMD4, November 30 - December 5 2003, Maui, Hawaii.

42

8. Conclusions

In this project we have shown that the operation in the velocity modulation mode is possiblein SOI devices and, based on simulations of realistic device structure, the operation speed canbe higher than 500 GHz. The experimental data show that the amplitude of the modulationexceeds 90 % which is the highest value obtained for velocity modulation in 3-5semiconductor compounds or in silicon.

To reach this target, we first developed fabrication processes for single and dual gate deviceshaving a thin SOI channel. The investigations on the single gate devices indicate that thescattering arising from the charges at the bottom interface of the channel becomes significantin channels thinner than 15 nm. The mobility measured in dual gate devices increases at roomtemperature due to the reduced phonon scattering when the channel is in volume inversion, aspredicted recently by simulations. The results obtained by Raman spectroscopy show that theacoustic phonons become confined in thin SOI films, giving rise to potential implications tothe scattering of carriers and also to the heat conduction in the silicon slab.

The number of new results obtained in this project is large and many of the results still waitfor their interpretation. The vast amount of the new results also manifests the importance ofthe research on SOI devices, not only because of verification of predicted advantageousfeatures in performance due thin SOI channels but also because of the new physics in thesestructures.

Altogether, the results obtained in this assessment project are state of the art for ultra thin SOIdevices, and we conclude that the main goals in the project are fulfilled.

43

References.

[1] M.V.Fischetti, and S.E. Laux, Phys.Rev. B 48, pp.2244 (1993)

[2] C.Jacoboni and L.Reggiani, Rev.Mod.Phys. 55, pp.645-705 (1983)

[3] T.Ando, A.B.Fowler, and F.Stern, Rev.Mod.Phys. 54, pp.437-672 (1982)

[4] F.Gámiz, J.A.López-Villanueva, J.Banqueri, J.Carceller and P.Cartujo, IEEE Transact.on Electron Devices, ED-42, pp.258 (1995)

[5] F.Gámiz, J.A.López-Villanueva, J.A.Jiménez-Tejada, I.Melchor and A.Palma, J.Appl.Phys., 75, p.924-934 (1994)

[6] F.Gámiz, I.Melchor, A.Palma, P.Cartujo and J.A.López-Villanueva, Semicond. Sci. Technol., 9, p.1102-1107 (1994)

[7] F.Gamiz, J.B.Roldán, P.Cartujo-Cassinello, J.E.Carceller, J.A.Lopez-Villanueva, and S.Rodriguez, J.Appl.Phys. 86, pp.6269-6275 (1999)

[8] P.J.Price, Ann.Phys. (N.Y.), 133, pp.217-239 (1981)

[9] H.Ezawa, Ann.Phys. (N.Y.), 67, pp.438-460 (1971)[10] F.Gámiz and M.V.Fischetti, J. Appl. Phys., 89, 5478 (2001).

[11] A. Balandin and K. L. Wang, Phys. Rev. B 58, 1544 (1998).

INFORMATION SOCIETY TECHNOLOGIES(IST)

PROGRAMME

Contract for:

Shared-cost RTD

Annex 1 - “Description of Work”

Project acronym: EXTRAProject full title: Extremely fast silicon transistor based on carrier velocitymodulationProposal/Contract no.: IST-2001-38937Related to other Contract no.: n/a

Date of preparation of Annex 1: 13 September 2002

Operative commencement date of contract: see Article 2.1 of the contract

TTEJOU

Appendix 1

EXTRA, IST-2001-38937, 13 September 2002 2(20)

Contents

page

1. Project summary…………….....................…………………………………........ 3

2. Project objectives…………………………………………………........................ 4

3. Participant list………………………………………………………..................... 4

4. Contribution to programme/key action objectives……………….......................... 5

5. Innovation................................................................................................................5

5.1 Background..................................................................................................5

5.2 Principle of velocity modulation in SOI devices.........................................5

5.3 High frequency performance....................................................................... 7

References…............................................................................................... 8

6. Community added value and contribution to EU policies.......................................8

7. Contribution to Community social objectives......................................................... 8

8. Economic development and scientific and technological prospects……………………………………………………...................... 8

9. Project workplan……………………………….....................…………………….9

9.1 Workpackage list………………………………......………....................... 10

9.2 Workpackage description…………………………………...................…. 10

Workpackage 1: Fabrication of SOI devices with

top and back gates……………………………………………………....... 10

Workpackage 2: Velocity modulation in SOI devices……........................ 11

Workpackage 3: Simulation and theory………………….......................... 13

9.3 Deliverables list……………………………………………....................... 14

9.4 Assessment criteria...................................................................................... 14

9.5 Project planning and schedule……………………………......................... 15

9.6 Graphical description of the project components………......................…. 16

9.7 Project management………………………………………........................ 16

10. Clustering…………………………………......................................................….. 17

11. Other contractual conditions................................................................................... 17


1. Project Summary

Objectives (maximum 1000 characters) The objectives in this work are to: (1) Realise a dual gate velocity modulation transistor on ultra-thin SOI substrate. (2) Experimentally and theoretically define the optimum operation point for velocitymodulation switching. (3) Perform Monte Carlo simulations on transport and switching properties of a velocitymodulation transistor realised on substrates with ultra-thin SOI films. Description of the work (maximum 2000 characters) The work includes the following: Device fabrication: The test structures and devices will be fabricated on thin SOI wafers. Theprocess includes fabrication of thin SOI wafers with highly doped handle wafers for backgating and device processing on the wafers. For the structural characterisation ultra-thin SOIfilms can be realised simply by thermal oxidation and stripping the sacrificial oxide. Structural characterisation: The device structures will be characterised using XDR, AFM,HRSEM and TEM. Transport measurements: The electrical characteristics of the VMT structures will be studiedusing the field effect mobility measurements and low temperature Hall measurements. For ACmeasurements, a set-up up to 110 GHz is available. Modelling and theoretical aspects: The VMT devices will be simulated using one particle andensemble Monte Carlo schemes. The scattering mechanisms include contributions ofphonons scattering, interface roughness scattering and Coulomb scattering. The phonons areconfined in the thin SOI films and this affects the phonon scattering. The transient responseof the SOI VMTs can be deduced by ensemble Monte Carlo simulations.

Milestones and expected results (maximum 500 characters) The necessary two conditions for a VMT operation to become feasible are i) large enoughmobility difference between the current carrying channels and ii) during switching the channelcharge must remain more or less constant. The successful realisation of the two issues formthe main milestones of the project. The third expected result is development of ensembleMonte Carlo scheme suitable for simulation of devices fabricated on ultra-thin SOI substrates.


2. Project objectives

Telecommunication, optical telecommunication and local area network applicationsutilise higher and higher frequencies. Automotive collision warning radar control isanother fast growing volume application market requiring high frequency devices.Moreover, environmental applications, such as atmospheric sounding, monitoring thewater and oxygen levels, are of increasing importance. All these application areas requirefrequencies extending up to 200 GHz and even beyond. Currently it is expected thatoperation in this frequency range can be obtained only with pseudomorphic InP HEMTsor InP HBTs.

It is usually advantageous, eventually, to transfer the production of semiconductorcircuits to the "silicon world" due to the very rugged and effective process technologydeveloped during the past decades. The current silicon-based candidates for highfrequency operation are SiGe heterobipolar transistor and MOSFETs with a very shortgate. The fabrication of the HBTs requires epitaxy, and is not an all-silicon process,making the fabrication process more complicated. Recently, cut-off frequencies almostup to 200 GHz were reported for silicon MOSFETs (see, e.g., report from IEDM inCompound Semiconductor Jan/Feb 2002 issue). The high frequency operation is,typically, reached by devices with gate lengths in the deep sub-100 nm regime. The shortgates lead to short channel effects, which can be avoided by using dual gate structures orFINFET structures. The fabrication of the ultra short dual gates is not an easy task andcan lead to yield problems.

In this project we investigate the possibility to realise an extremely fast silicon transistorwhich is based on carrier velocity modulation and in which the length of the channel isnot a limiting factor for speed. In this so called velocity modulation transistor (VMT) theactive channel can be even a micron long without degrading the operation speed. Cut-offfrequency of the device is estimated to be several hundreds of GHz, and the device isimmune to parasitics. There are two conditions essential for the operation in velocitymodulation mode: 1) Formation of two parallel channels with different carrier mobilitiesbetween which the current carrying carriers can be switched and 2) keeping the carrierconcentration constant in the channel while switching. The objective in this project is todemonstrate that the two conditions can be fulfilled in a device in which a thin silicon-on-insulator (SOI) film forms the channel. Once it is shown that these requirements can befulfiled, it is possible to create a new family of very fast silicon transistors.

3. List of participants

Partic.role

Partic.no.

Participant name Shortname

Country Dateenterproject

Date exitproject

C 1 Technical Research Centre of Finland VTT FIN M0 M12P 2 University of Granada UGR E M0 M12P 3 Tokyo University IIS JP M0 M12


4. Contribution to programme/key action objectives

The role of "... FET open is to enable a range of ideas for future and emergingtechnologies to be explored and realised. ... to the widest possible spectrum of researchopportunities that relate to information society technologies." The implementation ofvelocity modulation concept to silicon based devices presented here enables very highspeed operation for silicon transistors, comparable to the performance of the best InPbased devices. If succesful, the concept permits application of silicon transistors, e.g., invery high speed telecommunication, local area networks, automotive radars andenvironmental monitoring. In this assessment project the possibility to realise velocitymodulation operation on silicon-on-insulator substrates will be investigated.

5. Innovation

5.1 Background

Velocity modulation transistor (VMT) was proposed by H. Sakaki as a means ofachieving rapid current modulation by modulating the carrier mobility instead of thecarrier density [1]. The concept of VMT was originally introduced with compoundsemiconductors in mind and several experiments have been performed on GaAs VMTstructures [2][3][4]. However, no experimental verification or studies exist for Si orsilicon-on-insulator (SOI) devices. There is a wide know-how about processing ofvarious different Si and SOI devices at VTT. The current state of the art in mobility ofSOI MOSFETs fabricated at VTT is around 1000 cm2/Vs at room temperature and 13000cm2/Vs at 300 mK. The values are comparable with the current high quality MOSFETsand are the basis for the innovation in this proposal.

5.2 Principle of velocity modulation in SOI devices

The geometry of a DGSOI FET depicted in Fig. 1(a) enables the adaptation of theconcept of velocity modulation in silicon-based materials. The device has two parallelgate controlled channels, A and B, which have different effective electron mobilities(velocities) �A and �B, respectively. The difference in the mobility between the bottomand top channel in a SOI VMT can be achieved, e.g., by making the other sideamorphous or by creating artificial corrugation in the top gate oxide [see Fig. 1(b)]. Theelectron gas that carries the source-drain current can be switched between the two surfacechannels by applying a voltage difference VgAB = VgA -VgB between the gates A and B ina push-pull fashion, shown in Fig. 1(c). In addition of the push-pull voltage, a finiteconstant gate bias Vg is required for a SOI VMT to provide finite electron concentrationin the whole SOI channel (meaning that the total gate voltages are VgA = Vg + VgAB/2 > 0and VgB = Vg - VgAB/2 > 0). Now if the total electron concentration Ntot between the gatesis approximately constant the current modulation is roughly ��I ~ ��effNtot, where ��eff=�A-�B is the effective mobility difference. Where as in conventional FET the currentmodulation mainly arises from the change in the total carrier concentration �Ntot andfollows relation �I ~ �eff�Ntot (�eff the effective channel mobility). The schematicbehaviour of the VMT drain-source current is depicted in Fig. 1(d). Imax and Imin describe


the limits where the charge transfer is fully completed and device current starts to beaffected by conventional field effect (Ntot changes). The mobility ratio defines the relativecurrent modulation Imax/Imin = max(�A,�B)/min(�A,�B) = �B/�A, which has to bemaximised for device applications.

In addition to mobility difference another important parameter in a VMT is the couplingbetween channels A and B. It should be large enough so that when the voltage betweenthe gates is changed charge preferably flows directly between channels A and B andneither of the channels is charged or discharged through the source or drain electrode.

Source Drain

Si substrate

Gate B

Gate A

Electron gas

Gate B

SiO2

SOI

Gate A

Gate B

Gate A

Gate B

Ch. A��A

Ch. B��B

Ch. A��A

Ch. B��B

(a)

(c)(d)

SiO2

amorphous Si rough interface

low mobilitychannel Ahigh mobilitychannel B

(b)

Gate voltage difference VgAB

Cha

nnel

cur

rent

I

Imin

Imax

0

�I

�VgAB

SiO2

SOI film

Gate A

ChannelSiO2

Fig. 1. (a) SOI VMT is based on Dual Gate SOI FET, whose structure and energy band model is shownschematically. (b) Illustration of methods to provide channels with different mobility for velocitymodulation operation. (c) Velocity modulation cycle in SOI VMT with different mobilities �A and �B atthe top and bottom interfaces, respectively. (d) Illustration of VMT current as a function of gate voltagedifference. Imax and Imin describe the limits where conventional field effect starts to dominate.


This situation is realised when the gate biasing point Vg is small enough that clearly finiteelectron density (in comparison to maximum density) exists in the middle of the filmwhen VgAB = 0. The gate bias point window where the strong coupling occurs is the largerthe thinner the SOI film is. Large gate bias point is desirable as it means high totalelectron concentration and, therefore, large current drive in the device. From the recenttheoretical studies of DGSOI devices [5][6] we can estimate that the above condition ofstrong coupling with high electron concentration is fulfilled when the SOI film thicknessis below ~ 40 nm.

5.3 High frequency performance

The operation of VMT is not limited by the carrier source-drain transit time defined bythe length of the gate. Instead, the intrinsic speed or switching time of a VMT is definedby two factors: the transfer time of the electrons between the high and low mobilitychannels �AB (~ �BA) and electron distribution relaxation in the channels �AA and �BB.Time constant �AB is obviously very small and in the case of thin SOI film it is affectedby the size quantisation effects, which makes estimations rather difficult. However,estimations based on classical transport schemes should give adequate upper limitestimate for the case of thin SOI VMT. Such approaches give �AB < 0.5 ps for both GaAs[7] and Si [8] based devices. Time constants �AA and �BB are affected by the scatteringprocesses of the individual channels and when considering device speed we should usemax(�AA,�BB). The higher mobility channel has longer relaxation time (by definition) andwe can use a rough estimate max(�AA,�BB) ~ max(�A,�B)*m/e (~ 0.5 ps, e.g., formaximum mobility of 1000 cm2/Vs). However, it may not be adequate to use themobility only to define the electron distribution relaxation. Especially this is the case withlarger source-drain voltages when electron energy related phenomena –such as carrierheating and field dependent mobility- can play major role in the relaxation processes.Anyhow, this discussion shows that intrinsic time constant in thin SOI VMT is � [~ �AB +max(�AA,�BB)] ~ 0.5 - 1.5 ps, which is consistent with Monte Carlo simulations of thickerfilm devices [7] [8]. This gives an intrinsic cut-off frequency of fc ~ 1/� ~ 500 GHz forthe device.

As the charge density in the channel is kept constant during the operation cycles onlyextremely small extra gate charge is required to provide the velocity modulation. Smallchange in the gate charge during the operation means small effective input capacitancefor VMT. Constant channel charge and small gate capacitance again suggest that thedevice is relatively immune to parasitic charging time effects arising from finite sourceand gate resistances. We conclude that in comparison to conventional FET a VMTconcept promises a (i) higher intrinsic speed, because the transit time does not limit theoperation, and also (ii) higher extrinsic speed, due to immunity to parasitic effects. Theextrinsic cut-off frequency can reach close to the intrinsic ~500 GHz cut-off. Therealisation of such a transistor would require a dual gate process in which a buried polysilicon back gate is aligned with the top gate with high accuracy. In addition to thestandard silicon CMOS processes, the fabrication would include two chemical-mechanical-polishing steps and wafer bonding. Although the technology is available atVTT, the fabrication of a true, optimised transistor for high frequencies would require


development of a new, complete and relatively complex fabrication process dedicated forVMT, which is out of the scope and resources of this assessment project. In this projectwe will mainly concentrate to verify the essential conditions for the velocity modulationoperation in silicon. RF properties from a test vehicle will also be measured.

References

[1] H. Sakaki, Jpn. J. Appl. Phys. 21, 381 (1982)[2] K. Hirakawa, H. Sakaki, and J. Yoshino, Phys. Rev. Lett. 54, 1279 (1985)[3] E.B. Cohen, K.J. Webb, D.B. Janes, and M.R. Melloch, Appl. Phys. Lett. 70, 2864 (1997)[4] K.J.Webb, E.W.Cohen, and M.R.Melloch, IEEE Trans.Electron Devices, 48, 2701 (2001)[5] F. Gamiz and M. V. Fischetti, J. Appl. Phys. 89, 5478 (2001)[6] H. Iwata, J. Appl. Phys. 90, 866 (2001)[7] I.C. Kizilyalli and K. Hess, Jpn. J. Appl. Phys. 26, 1519 (1987)[8] G.C. Crow and R.A. Abram, J. Appl. Phys., 85, 1196 (1999)

6. Community added value and contribution to EU policies

Incessant development of devices and circuits operating at higher and higher frequenciesleads also to emergence of novel products in the field of information technology andappliances. Currently high operation speed is obtained using compound semicondutors.Implementation of silicon technology in the production of high speed circuits would giveEurope a head start in the field. It is expected that the rugged silicon technology wouldreduce the production cost of the circuits in comparison with, e.g., InP technology andthus carry new opportunity to create volume market for new products.

7. Contribution to Community social objectives

A low cost, high volume production of high speed circuitry would impact several areasinfluencing every day life. The information society needs fast, user friendlycommunication networks and systems. Wireless local area networks operating around 60GHz, where the atmospheric attenuation is high, is one possible application. Anapplication that has potentially very high volume commercial market is collision warningradar or adaptive cruise control for automotive applications. Such a system would operateat 77 or 140 GHz. Nowadays the use of silicon based MEMS acceleration sensors in carsis widespread. The radars would further improve safety and convenience in traffic.Another, yet more and more important application is environmental and pollutionmonitoring. The sensing requires high frequency devices operating at resonance(absorption) lines of the target medium. For example, the resonances for oxygen are at60, 119 and 184 GHz and for water vapour at 22, 183 and 325 GHz. Such a surveysystem would provide real time data for studying changes in Earth's atmosphere.

8. Economic development and scientific and technological prospects

Device physics. We aim to demonstrate the applicability of the concept of velocitymodulation in devices fabricated on silicon-on-insulator wafers. Velocity modulation is a


novel mode of operation and has not been applied to silicon based devices yet. Afterdemonstrating the VM mode in SOI structures, the development of optimised fabricationprocess for dual gate devices will eventually lead to a family of silicon transistorsoperating at frequencies of several hundreds of GHz, a performance that has been so farreached with highest end compound semiconductor devices.

Economic development. At millimeter-wave frequencies the availability of largespectrums of bandwidth and the allocation of frequency bands for commercial use hasstimulated great interest for the development of low cost circuits for commercialproducts, cf. Chapter 7 above. Currently it is expected that operation at this frequencyrange can be obtained only with pseudomorphic InP HEMTs or InP HBTs. If afabrication process for dual gate silicon VMTs can be developed, it can be expected thatthe cost per device will be much lower and, thus, the market volume of various highfrequency applications will largely increase.

9. Project workplan

As was discussed above, there are two fundamental requirements for a SOI VMT tobecome a practical device:

i) Charge must be readily switched between the two channels with minimal totalsheet charge modulation in order to minimise the capacitive charging-discharging time constants.

ii) Mobility in the high-mobility channel must be significantly greater thanmobility in the low-mobility channel.

The first requirement is equivalent to high speed and the second to large currentmodulation (and gain). The main goal in this project is to demonstrate that the two basicrequirements can be fulfilled in SOI based devices.

9.1 Workpackage list

WPno.

Task Title WPleader

Taskleader

Person-months

Startmonth

Endmonth

Deliverable

1 Fabrication of SOIdevices with top andback gates

VTT 6 1 12

1.1 Fabrication of deviceswith sub-50 nm thickSOI channel with topand back gates

VTT 4 1.1

1.2 Verification ofswitching by transportmeasurements

IIS 2 1.2


2 Velocity modulation inSOI devices

VTT 5 1 12

2.1 Development of aprocess to decrease themobility at the otherinterface in a controlledway

VTT 3 2.1

2.2 Electricalcharacterisation ofdevices with differentmobilities at top andbottom interfaces

IIS 1 2.2

2.3 Characterisation of RFproperties of velocitymodulation devices

VTT 1 2.3

3 Simulation and theory UGR 12 1 12

3.1 Simulation of electrontransport in SOI VMTin stationary conditions

UGR 6 3.1

3.2 Ensemble Monte Carlosimulations

UGR 6 3.2

Total 23

9.2 Workpackage description

The work in EXTRA will be divided into three workpackages. WP1 concentrates totackle the first of the essential conditions for velocity modulation, i.e., switching thecharge carriers between top and bottom interfaces of the thin SOI film without changingthe total carrier density in the channel. The aim in WP2 is to develop a process for tuningthe mobilities in the channel in such a way that velocity modulation amplitude is largeenough for applications. WP3 includes modelling and Monte Carlo simulations of SOIvelocity modulation structures.

Workpackage 1: Fabrication of SOI devices with top and back gates

Participant VTT UGR IISPerson-months 4 2

Objectives

The objective of WP1 is to verify that the essential condition of charge switching withoutcharge modulation can be fulfilled. To do this, devices with top and back gates will befabricated and characterised.


Task 1.1: Fabrication of devices with sub-50 nm thick SOI channel and with top andback gates.

For the verification of the possibility to switch charge between the two channels withouttotal channel charge modulation, devices with gates on both sides of the channel arerequired. The most straight forward approach is to use SOI wafers with a conductinghandle wafer. Wafers with a highly doped handle wafer and with buried oxide thicknesssuited for back gating are not commercially available. Such SOI wafers will be firstfabricated at VTT. The fabrication consists of high dose hydrogen implantation of thedonor wafer, wafer bonding, exfoliation of the SOI film from the donor wafer by thermaltreatment and chemical-mechanical polishing of the top surface.

Hall bars, devices for transfer length measurements and transistors with gate lengths from1 to 10 microns will be processed on the wafers using mainly the processing technologyalready developed in projects Q-Switch and NEAR. The difference in here is that thefinal channel thickness is less than in the devices fabricated in those projects. This createsa need to further develop some of the process steps. Fabrication of devices with buriedback gates for RF measurements will also be attempted.

Task 1.2: Verification of the switching by transport measurements.

The devices fabricated in Task 1.1 will be characterised by transport measurements. Themost important measurement is mapping of mobility and carrier concentration in thechannel as a function of top and bottom gate biases at various temperatures. From themaps the condition of minimal sheet carrier modulation in the channel during switchingcan be deduced. This condition provides the window for velocity modulation operation.The mapping from room temperature down to 1.5 K will be carried out at IIS. Thecharacterisation of the test structures at room temperature will be performed at VTT.

Based on the results obtained from the transport measurements and on the results fromWP 3, the channel thickness and the gate oxide thicknesses will be optimised foreffective switching of carriers between the channels.

Deliverables:� Fabrication of SOI devices with sub-50 nm thick channels and with back and top

gates� Demonstration of carrier switching between channels formed at the upper and lower

interface of the SOI film with minimal charge modulation

Workpackage 2: Velocity modulation in SOI devices

Participant VTT UGR IISPerson-months 4 1


ObjectivesThe objective of WP2 is to demonstrate the current modulation based on differentmobilities at the upper and lower interface of the SOI film. This is the other essentialcondition for velocity modulation operation.

Task 2.1: Development of a process to decrease the mobility at the other interface ina controlled way.

In this Task a process to decrease the mobility at the other interface to one fifth will bedeveloped. The first candidate is shallow implantation with heavy ions, such as As. Theidea is to create high density of defects at the upper interface of the SOI channel. With adose high enough part of the channel can even be turned amorphous. This will decreasethe mobility at the upper interface and provide mobility difference large enough forvelocity modulation.

In case the implantation degrades the mobility also at the lower interface too much,different means to create the mobility difference must be used. The other possibilities areto create an artificial corrugation on the upper interface or to grow a thin layer of finegrain polysilicon or even amorphous silicon on the SOI channel. The layer would formthe low mobility channel. The drawback is that the fabrication process becomes morecomplicated.

Task 2.2: Electrical characterisation of devices with different mobilities at top andbottom intefaces.

This Task consist of similar mapping measurements as in the Task 1.2, but now fromsamples with deliberately induced mobility modulation. The measurements giveinformation, not only about the side of the channel which is modified by implantation,but also information about the effect on the other side of the channel. From the maps theproper region for operation in velocity modulation mode can be defined.

Task 2.3: Characterisation of RF properties of the velocity modulation devices.

The devices with the handle wafer as back gate are not optimised for ultra high frequencyoperation because of the paracitics induced by large area back gate. Anyhow, interestingRF measurement results can be obtained from these devices. In a conventional FET theoperation speed is limited by transit time or by the time constant defined by the gatecapacitance and series resistance in the channel. In velocity modulation mode theselimitations are lifted and the operation speed should be higher. By comparing the RFproperties of the fabricated devices in field effect mode and in velocity modulation mode,the change over to VM operation can be traced. In the characterisation both Hall bars andback gated transistors can be used. This way the enhanced speed due velocity modulationcan be demonstrated in the devices with large area back gates. RF properties of testdevices with buried back gates will be also ananlysed.


Deliverables� Process to control the mobilities at the interfaces of the SOI channel.� Demonstration of current modulation� Demonstration of increased operation speed due velocity modulation mode.

WP3: Simulation and theory

Participant VTT UGR* IISPerson-months 12

ObjectivesThe objective of this WP is to analyse the operation of a VMT by one electron andensemble Monte Carlo simulations. The results will be used to optimise the device designin order to maximise the current modulation and modulation speed.

Task 3.1: Simulation of electron transport properties in SOI VMT in stationaryconditions

The goal of this task is calculation of the electron mobility in the device when all theelectrons populate the high-mobility channel or the low-mobility channel. Thegeometrical and technological properties of the structure will be taken into account. Thedifferent scattering mechanisms will be studied, and their influence on the electronmobility carefully analysed. The previous results show that the two channels at theopposite interfaces are in some way coupled. The question to solve is whether thescattering mechanisms intentionally induced to degrade the mobility in the other channel,would also degrade the mobility of the electrons in the channel at the opposite interface.Another important question is the influence of the drift electric field on the population ofthe two channels, and of course on the mobility.

To shed light on these topics, Poisson and Schroedinger equations will be solved in thestructure, taking into account the voltages applied at each gate. The Boltzmann transportequation will then be solved by the Monte Carlo method. Electron mobility curves will beevaluated. Finally, an improved drift-diffusion model will be used here to evaluate anapproximation to the current in the structure when a voltage is applied between drain andsource. The results will be used to optimise the design and to maximise the electronmobility ratio between the two channels

Task 3.2. Ensemble Monte Carlo simulations of transient behaviour

In this Task the transient behavior of the device will be studied, i.e., the switching timebetween the two channels will be deduced from simulations. To achieve this, the one-electron Monte Carlo code developed in Task 3.1 will be implemented into an EmsembleMonte Carlo (EMC) simulator. Quantum effects will be incorporated by solving the

* Additional 8.6 man-months by permanent staff will be included in the total workpackage man-months.


Schroedinger equation self-consistently with the EMC. The effect of the scatteringmechanisms, and technological and geometrical parameters of the device on switchingtime will be carefully analysed. The structure will be optimised to reduce the switchingtime, taking into account the best mobility ratio. The EMC simulator will also be used toevaluate the current in the structure.

Deliverables� Analysis of DC behaviour of a SOI VMT by Monte Carlo simulations� Deduct the switching speed of a VMT by an Emsemble Monte Carlo simulations

9.3 Deliverables list

Deliverables list

Del.No.

Del. Name WPno.

Leadparticipant

Estimatedpersonmonths

Del.Type

Security Delivery

1.1 Devices with sub-50nm thick channels

1 VTT 4 R Pu M5

1.2 Demonstration ofswitching between theinterfaces

1 IIS 2 R Pu M12

2.1 Control of mobilitiesat the interfaces

2 VTT 3 R In M6

2.2 Demonstration ofcurrent modulation

2 IIS 1 R Pu M12

2.3 Demonstration ofincreased speed dueVM operation

2 VTT 1 R Pu M12

3.1 MC simulations of DCbehaviour

3 UGR 6 R Pu M8

3.1 EMC simulations oftransients

3 UGR 6 R Pu M12

9.4 Assessment criteria

We can define the following criteria for the successful fulfilment of the project. The mostimportant criteria in this assessment project are the first two, which form the essentialconditions for realisation of a functioning velocity modulation transistor. The firstrequirement is essential for high speed operation and the second for large currentmodulation, i.e., gain.


1. Experimentally and theoretically define a condition (gate voltage bias window, SOIfilm thickness) where the carriers can be switched between top and bottom interfacesin the SOI channel without modulating the total carrier concentration.

2. Find means to create large enough mobility difference between top and bottominterfaces in the SOI channel. The criterion is to reach a mobility ratio of at least 5 at300 K (80 % current modulation).

3. Demonstration of increased operation speed due to velocity modulation mode incomparison to operation in conventional FET mode.

4. Making realistic calculations of velocity modulation in thin SOI films by Monte Carlosimulations and show that intrinsic speeds of 500 GHz are possible with a VMT.

5. RF measurements on a test device targeted for running at 70-150 GHz range.

Successful fulfiling of the first two criteria paves the way for the realisation of siliconVMT. The last three give information about the speed of a SOI VMT.

In this assessment project we will first fabricate devices with a highly doped handle waferof the SOI substrate as the back gate. This kind of device configuration is suitable forfulfiling the first two assessment criteria. Considering high frequency measurents, weestimate that the parasitic capacitances to the conducting handle wafer will shunt thedevice at frequencies around 1 GHz. This means that this device geometry is not suitablefor explicit determination of high frequency properties of SOI VMTs. With buried andaligned back gates the shunting can be avoided and RF performace can be verifiedexperimentally.

9.5 Project planning and timetable

EXTRA Project planning and timetable

WP Task Description 1 2 3 4 5 6 7 8 9 10 11 12

1 1.1 Fabrication of SOI wafers, fabricationof devices with top and bottom gates

1 1.2 Mobility and carrier density vs. gatevoltages

2 2.1 Process for controlling the mobilities inthe channel, device fabrication

2 2.2 Mobility and carrier density vs. gatevoltages, current modulation

2 2.3 RF measurements

3 3.1 One electron Monte Carlo simulations

3 3.2 Ensemble Monte Carlo simulations


9.6 Graphical description of the project components

9.7 Project management and dissemination of results

The coordinator and the steering committee will be resposible for the projectmanagement.

Affiliation Name Task leader Steering committee

VTT Jouni Ahopelto, Coordinator XVTT Mika Prunnila Task 1.1, 2.1 XUGR Francisco Gámiz Task 3.1, 3.2 XIIS Hiroyuki Sakaki Task 1.2, 2.2 X

The steering committee will meet on suitable occasions at least twice during the project.In addition to the steering committee meetings, the staff working in the project will visitthe laboratories of other partners.

The results will be published in international journals and conferences, taking intoaccount also the IPR aspects.

SOI waferswith conductinghandle wafer

Monte Carlosimulations

Report onresults

Mobility andcarrierconcentration vs.VgTop and VgBottom

Feedback for the next processing round

Mobilities andcarrierconcentrations,RF properties

Process formobility control,devices

Devices withtop andbottom gates


10. Clustering

There is currently a relative strong community in Europe working on SOI materials,ranging from academic research to SOI substrate development and wafer production. Onemanifestation of the community was the Expresion of Interest called EUROSOI,coordinated by Prof. F. Gamiz, a partner in EXTRA. The EoI included 33 universities,research institutes and companies. The results obtained in EXTRA will definitely be ofinterest for the SOI community, laying part of the foundation for clustering and future,extended work in this field, e.g., in the Sixth Framework Programme.

11. Other contractual conditions

Clean room costs. The velocity modulation test structures and devices will be processedusing facilities at VTT Centre for Microelectronics. The clean room facility is a centralservice, charged internally from every project using the facility. The fee includes costsdue air-conditioning, DI-water, dry nitrogen and use of generic clean room materials andprocessing equipment. The cost amounts 120€/hour. The usage of the facility in EXTRAis estimated to total 16500€.


Appendix A - Consortium DescriptionThe velocity modulation transistor (VMT) was proposed by one of the partners, Prof.Sakaki, Institute of Industrial Science (IIS), University of Tokyo, in 1982. Thus, theconsortium has excellent theoretical background to carry out the planned work. Thevelocity modulation structures have been so far reported on 3-5 compound materials. AtTechnical Research Centre of Finland, VTT Centre for Microelectronics (VTT), has beendeveloping processing technology for SOI devices in, e.g., EU funded projects. In thisproject we aim to demonstrate velocity modulation in silicon using SOI substrates. IISand VTT have together the necessary transport measurement facilities, IIS lowtemperatures and magnetic fields and VTT RF measurement equipment, to analyse thedevices. The experimental work is supported by the Group of Research In Devices inElectronics (GRIDE) of the University of Granada which is specialised to Monte Carlosimulations of SOI structures.The consortium has the necessary and sufficient competence to reach succesfully thegoals in the proposal, and the partners complement each other well, without overlap inthe assignments.

Overview of the consortium

ActivityCode

Shortname

Organisation Country Role in project

CO1 VTT VTT Centre forMicroelectronicsProf. J.Ahopelto

FIN Coordination. Design andfabrication of VMTs.Structural and electricalcharacterisation.

CR2 UGR Departamentode Electrónica yTecnolgía deComputadores.Universidad deGranadaProf. F. Gamiz

E One particle and ensemble MonteCarlo simulations of VMTs.

CR3 IIS University ofTokyo,Institute ofIndustrialScienceProf. H. Sakaki

JP Transport studies of VMTs,threoretical aspects of SOI devices.

CO1: VTT is a national research institute. VTT Centre for Microelectronics has a longexperience in fabrication and characterisation of silicon devices and circuits. In recentyears processing technologies for producing both thick and thin SOI wafers have beenactively investigated at VTT, leading to establishing a proto line for fabrication of SOI


wafers for a Finnish wafer company. In the nanoelectronics group fabrication processesfor devices, such as single electron devices and SOI micro coolers, on very thin SOIlayers has been developed. VTT has been engaged in EU projects Q-SWITCH,NANOTECH, CHANIL and NEAR.

CR2: The Group of Research In Devices in Electronics (GRIDE) of the University ofGranada, UGR, has a long record of activity (over 10 years) in the field of numericalsimulation of Electron Devices. Extensive calculations on transport in thin SOI filmshave been developed in the last few years.

CR3: IIS at University of Tokyo has expertise in theory of transport of mesoscopicsemiconductor structures, and facilities for transport measurements down to 300 mK andin magnetic fields up to 13 T. Lower temperatures and even higher magnetic fields are atConsortium's disposal at the Institute of Solid State Physics of Univerity of Tokyo. Note:The velocity modulation transistor was invented and originally proposed by CR3.

CVs of key persons

Prof. Jouni Ahopelto obtained his M.Sc., Lic.Tech., and Dr.Tech. degrees from theHelsinki University of Technology (Finland) on semiconductor physics. He is currently atVTT Centre for Microelectronics (VTT Technical Research Centre of Finland)responsible for research in the field of nanoelectronics. His main activities have beenfabrication and characterization of mesoscopic semiconductor structures. He haspublished over 150 journal and conference papers on compound semiconductor andsilicon nanostructures and devices. He has been contractor in EU projects Q-SWITCH(phases one and two), NANOTECH, CHANIL and NEAR.

Prof. Francisco Gamiz graduated with a bachelor’s degree in physics in 1991, andreceived the Ph.D. in 1994 from the University of Granada. Since 1991 he has beenworking on the characterization of scattering mechanisms and their influence on thetransport properties of charge carriers in semiconductor heterostructures. He has studiedelectron mobility in silicon inversion layers by the Monte Carlo method. His currentresearch interests include the effects of many-carriers on electron mobility and thetheoretical interpretation of the influence of high longitudinal electric fields on theelectrical properties of MOS transistors. Other interests are related to SiGe and SiC, SOIdevices and quantum transport. He has coauthored more than 60 refereed papers in allthese subjects. In 1999 he was Visiting Researcher at the IBM T.J.Watson ResearchCenter, Yorktown Heights, NY. Since 1995, he has been an Associate Professor at theUniversity of Granada. During 1998-1999 Dr.Gamiz was the Spanish Coordinator of theConcerted Action “Simulation tools for Nanometer Silicon Devices” with the TechnicalUniversity of Vienna. At present, he is coordinator of the concerted action “Modelling ofSOI devices” with the Institute for Microelectronics of the Technical University ofVienna. Prof. Gamiz was Chair of the European Workshop on Silicon-on-InsulatorDevices (EUROSOI) that was held in Granada, October 2000, and he is Co-Chair of the11th INTERNATIONAL SYMPOSIUM ON SILICON-ON-INSULATOR


TECHNOLOGY AND DEVICES of the Electrochemical Society to be held in Paris in2003.

Prof. Hiroyuki SAKAKI:Born on Oct.6, 1944. Received from University of Tokyo (UT) B.S.degree in electricalengineering in 1968 and M.S. and Ph.D degree in electronic engineering in 1970 and 73respectively. His Ph. D work was on “Surface quantization and electron transport insilicon MOS inversion layers.” From 1973 to 1987, he was an associate professor atInstitute of Industrial Science (IIS), UT, where he conducted nano-structure research,including seminal works on quantum wire/dot devices, MBE growth and atomic scalestudy of quantum heterostructures, in-plane and tunneling transports of 2D electrons inquantum wells (QWs) and superlattices (SLs) and so on. From March 1976, he workedfor 18 months as a visiting scientist with Dr. Leo Esaki at Watson Research Center,where he invented a QW infrared detector and performed the first in-plane electrontransport study on type I and type II QWs and SLs. Since 1987, he is a full professor atIIS. From 1988 to 98, he was a co-appointed professor at Research Center for AdvancedScience and Technology of UT. He led ERATO Project on “Quantum Wave” (‘88-’93)and Joint Project on “Quantum Transitions” (’94-’98) with UC Santa Barbara, bothunder the JST support. Now he leads COE Project on “Quantum Dots: Physics andDevices” under the support of Ministry of Education. He received numerous awards,such as Purple Ribbon Medal (Shiju-Hosho) of Japanese Government (‘01), IEEE DavidSarnoff Award (’96), Fujiwara Prize (’00), Japan IBM Science Award (’89), Hattori-Hoko Award (’90), Japan Soc. Appl. Phys. Award (’90, ’83) and OutstandingAchievement Awards from Institute of Electronics, Information and CommunicationEngineers of Japan (IEICEJ) (’73, ’91). He is a fellow member of IEEE, APS andIEICEJ.

EXTRA Final Report2 Contents 1. Introduction 3 2. Work package 1: Fabrication of SOI devices with...

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