External I/O Bus Scott Fierstein Technical Evangelist Consumer AV Platforms and Networking, IEEE...

External I/O BusExternal I/O Bus

Scott FiersteinScott FiersteinTechnical EvangelistTechnical EvangelistConsumer AV Platforms and Consumer AV Platforms and Networking, IEEE 1394Networking, IEEE 1394Microsoft CorporationMicrosoft Corporation

Goals And ObjectivesGoals And Objectives

Increase adoption of 1394 Increase adoption of 1394 on desktopson desktops

Understand the advantages 1394b Understand the advantages 1394b offers over 1394aoffers over 1394a

Understand how to build a USB 2.0 Understand how to build a USB 2.0 high-speed devicehigh-speed device

Technology Forum OutlineTechnology Forum Outline

Introduction and technical overviewsIntroduction and technical overviews Close examination of the IEEE 1394b Close examination of the IEEE 1394b Motivation for upgrading 1394 Motivation for upgrading 1394

implementations in the PC to the 1394b implementations in the PC to the 1394b PIL/FOP modelPIL/FOP model

Extending the design of full speed USB Extending the design of full speed USB to high speed (USB 2.0) to high speed (USB 2.0)

USB-IF compliance program updateUSB-IF compliance program update

IntroductionIntroduction

1394b Inside And Out1394b Inside And Out Michael Johas Teener, ZayanteMichael Johas Teener, Zayante

1394 On The Consumer PC1394 On The Consumer PC Steve Bard, Intel Mobile Computing GroupSteve Bard, Intel Mobile Computing Group

Update on USB 2.0 - Support for MicrosoftUpdate on USB 2.0 - Support for Microsoft®® Windows Windows®®

Robert Ingman, Microsoft CorporationRobert Ingman, Microsoft Corporation

USB 2.0: The Development Of A High-Speed DeviceUSB 2.0: The Development Of A High-Speed Device Ed Beeman, Hewlett-Packard Ed Beeman, Hewlett-Packard

Expanding The USB Compliance ProgramExpanding The USB Compliance Program Jason Ziller, Intel CorporationJason Ziller, Intel Corporation

1394b Inside And Out1394b Inside And Out

Michael Johas TeenerMichael Johas TeenerChief Technical OfficerChief Technical OfficerZayante, Inc.Zayante, Inc.

AgendaAgendaSame familiar 1394, but with:Same familiar 1394, but with:

Higher speeds to 3.2 GB/secHigher speeds to 3.2 GB/sec New coding (8b10b + scrambling + control coding)New coding (8b10b + scrambling + control coding)

New arbitration (BOSS)New arbitration (BOSS) Overlapped, pipelined arbitration, hybrid bus operation for Overlapped, pipelined arbitration, hybrid bus operation for

backwards compatibilitybackwards compatibility

Consumer Electronics - friendly high-speed connector Consumer Electronics - friendly high-speed connector with backwards compatibilitywith backwards compatibility

Longer distance to 100m per hopLonger distance to 100m per hop A “greener” standard with its emphasis on lower emissionsA “greener” standard with its emphasis on lower emissions New media, but all compatible above the media New media, but all compatible above the media

dependent leveldependent level

New integration model (PIL-FOP)New integration model (PIL-FOP)

But Why Improve 1394?But Why Improve 1394?

PC peripherals need higher speedsPC peripherals need higher speeds Disk head read rates continue to increase Disk head read rates continue to increase

S400 on existing PCs and Macs is not enough: 1 GB/sec. needed S400 on existing PCs and Macs is not enough: 1 GB/sec. needed in 2001, growth path to over 2 GB needed in a few yearsin 2001, growth path to over 2 GB needed in a few years

Imaging devices have higher and higher pixel densities and Imaging devices have higher and higher pixel densities and color depthscolor depths

Home network needs high speed, long distance, low Home network needs high speed, long distance, low bit error, guaranteed latencybit error, guaranteed latency Consumer Electronic devices already use 1394 for video and Consumer Electronic devices already use 1394 for video and

audio streamsaudio streams Virtually all DTVs, STBs, VCRs, and DVDs will be 1394 by 2002Virtually all DTVs, STBs, VCRs, and DVDs will be 1394 by 2002

6-20 Mbit/sec MPEG-2 streams for DTV6-20 Mbit/sec MPEG-2 streams for DTV Very good error rate required (loss of I-frame disastrous)Very good error rate required (loss of I-frame disastrous)

… … And 1394 is also a dandy peer-to-peer IP networkAnd 1394 is also a dandy peer-to-peer IP network

First - What Hasn’t ChangedFirst - What Hasn’t Changed

Same ...Same ... Point-to-point connection modelPoint-to-point connection model

But now has loop healingBut now has loop healing Logical bus modelLogical bus model Peer-peer operationPeer-peer operation User friendliness - Plug and PlayUser friendliness - Plug and Play Transaction and addressing modelsTransaction and addressing models Asynchronous operation model (including fairness)Asynchronous operation model (including fairness) Isochronous operation model Isochronous operation model $0.25 per SYSTEM license fee (http://www.1394la.com)$0.25 per SYSTEM license fee (http://www.1394la.com)

Identical functionality above the link layerIdentical functionality above the link layer Existing software will work unchangedExisting software will work unchanged

Existing devices are all “home network ready”Existing devices are all “home network ready”

What Is 1394b, Really?What Is 1394b, Really?

Additional “Beta” mode of operationAdditional “Beta” mode of operation 1394a operation is called “Legacy” mode1394a operation is called “Legacy” mode

1394b PHYs may have Legacy ports, 1394b PHYs may have Legacy ports, Beta ports, or “Bilingual” portsBeta ports, or “Bilingual” ports Bilingual ports negotiate with attached Bilingual ports negotiate with attached

peer for best mode of operation (Beta is peer for best mode of operation (Beta is MUCH better)MUCH better)

Beta mode yields higher speeds, longer Beta mode yields higher speeds, longer distance, improved efficiencydistance, improved efficiency

Beta Mode: Higher SpeedsBeta Mode: Higher Speeds

1394b specifies S800 and S1600 data 1394b specifies S800 and S1600 data transmission rates transmission rates Also future-proofs with media for S3200 Also future-proofs with media for S3200

Electrical spec still uses two twisted pairsElectrical spec still uses two twisted pairs Transmission is now continuous dual simplexTransmission is now continuous dual simplex

One pair transmitting continuously in each directionOne pair transmitting continuously in each direction Transmission speed never variesTransmission speed never varies Simpler and more efficient than 1394-1995Simpler and more efficient than 1394-1995

PortPort PortPortTPATPA

TPBTPB

TPATPA

TPBTPB

Beta Mode: Signal EncodingBeta Mode: Signal Encoding

Use only one scheme for data, arbitration and Use only one scheme for data, arbitration and speed signalingspeed signaling

All signaling uses 10 bit symbolsAll signaling uses 10 bit symbols DC balanced code with bounded running disparity to combat DC balanced code with bounded running disparity to combat

“baseline wander”“baseline wander” Limited run length for ease of clock recoveryLimited run length for ease of clock recovery

Data and arbitration states use IBM’s 8B10B encodingData and arbitration states use IBM’s 8B10B encoding Leveraged from Fibre Channel and Gigabit EthernetLeveraged from Fibre Channel and Gigabit Ethernet ……But scrambled to minimize emissionsBut scrambled to minimize emissions

Control symbols use 10 bit codesControl symbols use 10 bit codes All DC balanced with a hamming distance of 2 from each All DC balanced with a hamming distance of 2 from each

other and from data for added robustnessother and from data for added robustness Also scrambledAlso scrambled

More Beta BenefitsMore Beta Benefits

Fully self-timedFully self-timed No need for gap time setting, totally self-adjustingNo need for gap time setting, totally self-adjusting

Simplifies analog designSimplifies analog design Avoid common mode signaling, avoid bi-directional Avoid common mode signaling, avoid bi-directional

arbitration signalingarbitration signaling Robust error detectionRobust error detection

Most single bit errors detected immediately, extra precautions Most single bit errors detected immediately, extra precautions taken to bound propagationtaken to bound propagation

Control symbols duplicated for added robustnessControl symbols duplicated for added robustness Shorter start and end packet timesShorter start and end packet times

No packet start-up latencyNo packet start-up latency Same coding scheme for all mediaSame coding scheme for all media

Ideal for optical transmissionIdeal for optical transmission Leverage the benefit of high volume production for PHYsLeverage the benefit of high volume production for PHYs

The Downside Of BetaThe Downside Of Beta

Requires a new suite of connectorsRequires a new suite of connectors Digital logic much more complexDigital logic much more complex

2 to 3x more gates2 to 3x more gates Clock recovery neededClock recovery needed

Just like Ethernet, USB 2.0Just like Ethernet, USB 2.0

New “border” functionality neededNew “border” functionality needed For PHYs with Beta and Legacy portsFor PHYs with Beta and Legacy ports Non-trivial design, need to preserve Non-trivial design, need to preserve

critical Legacy timings, subtle critical Legacy timings, subtle corner casescorner cases

Beta Mode EfficiencyBeta Mode EfficiencyBOSS arbitrationBOSS arbitration

Legacy 1394 alternates between data transmission Legacy 1394 alternates between data transmission and arbitrationand arbitration Arbitration depends on round-trip transmission time Arbitration depends on round-trip transmission time Not scalable, so proportionately worse for higher speedsNot scalable, so proportionately worse for higher speeds Becomes much more significant with long distancesBecomes much more significant with long distances

1394b uses overlapped pipelined arbitration1394b uses overlapped pipelined arbitration Scheme known as “BOSS”Scheme known as “BOSS”

The Boss is the currently transmitting node and The Boss is the currently transmitting node and decides who should transmit nextdecides who should transmit next Explicit decision at the end of each subactionExplicit decision at the end of each subaction Immediate decision saves the arbitration timeImmediate decision saves the arbitration time

datadata datadata

datadata

datadata

grantgrant grantgrant

end of packetend of packet

grantgrant

Overlapped ArbitrationOverlapped Arbitration

With BOSS, 1394b exploits the dual With BOSS, 1394b exploits the dual simplex propertysimplex property

Requests go inRequests go inopposite directionopposite direction

to datato data

Sends a “grant”Sends a “grant”when finishedwhen finished

node #0BOSS

rootnode #4

node #3

node #1 node #2

ch ch

ch ch

p

pppp

p

requestrequest

low requestlow request

requestrequest requestrequest

Last node to sendLast node to sendin a subaction isin a subaction is

the “boss”the “boss”

Gaps Are Removed!Gaps Are Removed!

When the “BOSS” is finished transmitting, When the “BOSS” is finished transmitting, it knows where to send a grantit knows where to send a grant The “end of packet” sequence includes an The “end of packet” sequence includes an

optional “Grant” symboloptional “Grant” symbol Each node repeating the end of packet sends the Each node repeating the end of packet sends the

grant signal to the highest priority requestorgrant signal to the highest priority requestor Similar process removes the need for an Similar process removes the need for an

“arbitration reset gap”“arbitration reset gap” A node can request the bus at the next fairness A node can request the bus at the next fairness

interval when it runs out of allocated opportunities interval when it runs out of allocated opportunities in the current intervalin the current interval

BOSS transmits an arbitration reset symbol when BOSS transmits an arbitration reset symbol when only requests for the next interval are receivedonly requests for the next interval are received

Hybrid Bus OperationHybrid Bus Operation

1394b is fully backwards compatible1394b is fully backwards compatible A port on a PHY may be implemented asA port on a PHY may be implemented as

A DS port A DS port A Beta-mode only portA Beta-mode only port A bi-lingual portA bi-lingual port

Connector keying ensures that incompatible Connector keying ensures that incompatible connections cannot physically be madeconnections cannot physically be made

A PHY may have any mix of ports operating in A PHY may have any mix of ports operating in DS mode and Beta modeDS mode and Beta mode

A PHY may have a B link, a Legacy link A PHY may have a B link, a Legacy link or no linkor no link

Hybrid Bus Operation - 2Hybrid Bus Operation - 2 A hybrid bus is one which contains DS (legacy) connections, and/or one or A hybrid bus is one which contains DS (legacy) connections, and/or one or

more Legacy link devices (as well as connections operating in Beta mode)more Legacy link devices (as well as connections operating in Beta mode)

BB BB

BBDSDS

DSDS

BB BB

BB

DSDS

DSDS

DSDS

DSDS

BB

BB BB

B cloudB cloud B cloudB cloud

BoBo

BoBo BoBo

Devices communicating via Beta-mode connections group themselves Devices communicating via Beta-mode connections group themselves into B cloudsinto B clouds

Border nodes connect between Legacy ports and links and 1394b Beta Border nodes connect between Legacy ports and links and 1394b Beta ports and linksports and links

Hybrid Operation: SummaryHybrid Operation: Summary

No restrictions on mixing Legacy nodes and 1394b No restrictions on mixing Legacy nodes and 1394b nodes, beyond those inherent in the particular PHY nodes, beyond those inherent in the particular PHY chip implementationchip implementation If the user can plug it together, then it worksIf the user can plug it together, then it works

Traffic within a B cloud can exploit full benefit of boss Traffic within a B cloud can exploit full benefit of boss arbitration and more efficient packet formatsarbitration and more efficient packet formats And Beta-only nodes are significantly simplerAnd Beta-only nodes are significantly simpler

DS traffic operates as normal, with suitable gap times DS traffic operates as normal, with suitable gap times to ensure that all DS nodes can transmit each to ensure that all DS nodes can transmit each isochronous interval and in each fairness interval isochronous interval and in each fairness interval Existence of more efficient Beta mode operation is Existence of more efficient Beta mode operation is

totally transparenttotally transparent

Improved ConnectorImproved Connector

New connector needed for higher date ratesNew connector needed for higher date rates So let’s make everything betterSo let’s make everything better

Much better shielding and signal isolationMuch better shielding and signal isolation Designed for both CE and PC worldsDesigned for both CE and PC worlds

Only slightly larger than existing 4-ckt connectorOnly slightly larger than existing 4-ckt connector Carries power to support PC peripheralsCarries power to support PC peripherals

Keying to ensure compatibilityKeying to ensure compatibility Beta mode signaling is never used on a Legacy connectorBeta mode signaling is never used on a Legacy connector Simplifies backwards compatibilitySimplifies backwards compatibility

Two variantsTwo variants Bi-lingual connector - accepts bilingual plug or Beta plugBi-lingual connector - accepts bilingual plug or Beta plug Beta connector - only accepts Beta plugBeta connector - only accepts Beta plug

Bilingual And BetaBilingual And BetaConnector Plug And SocketConnector Plug And Socket 9 pin9 pin

Includes powerIncludes power 2 extra pins for signal integrity2 extra pins for signal integrity One pin for reserved for future useOne pin for reserved for future use

Small size - mating interface 8mm x 5 mmSmall size - mating interface 8mm x 5 mm Beta-onlyBeta-only BilingualBilingual

Bi-lingualBi-lingual Bi-lingualBi-lingual

Bi-lingualBi-lingualBeta-onlyBeta-only

Beta-onlyBeta-only Beta-onlyBeta-only

Bi-lingualBi-lingual 4-ckt4-ckt

Bi-lingualBi-lingual6-ckt6-ckt

3 Cable Assemblies3 Cable Assemblies Legacy mode cables (prevents DS to Beta-only connection)Legacy mode cables (prevents DS to Beta-only connection)

Bilingual to 6-ckt DS (carries power)Bilingual to 6-ckt DS (carries power) Bilingual to 4-ckt DS (no power)Bilingual to 4-ckt DS (no power)

Beta mode cable (also used for bilingual to Beta) (also used for bilingual to Beta)

Longer DistanceLonger Distance

General goal is 100m per hopGeneral goal is 100m per hop Input from VESA Home Network committeeInput from VESA Home Network committee

Unfortunately, longer distance requires Unfortunately, longer distance requires new medianew media UPT-5 for S100UPT-5 for S100

Just like 100BASE-T EthernetJust like 100BASE-T Ethernet

Plastic Optical Fiber (POF) for S200Plastic Optical Fiber (POF) for S200 S400 by 2001S400 by 2001

Multi-mode glass fiber for higher speedsMulti-mode glass fiber for higher speeds Road map from S400 all the way up to S3200Road map from S400 all the way up to S3200 Best for future-proof installationsBest for future-proof installations

Common PropertiesCommon Properties

All media use the same encoding schemeAll media use the same encoding scheme Optical media typically implemented with an Optical media typically implemented with an

optical transceiver integrated into the connector, optical transceiver integrated into the connector, with electrical connection to the PHYwith electrical connection to the PHY

Data and control symbols are scrambled Data and control symbols are scrambled using a side-stream scrambler using a side-stream scrambler before encodingbefore encoding Saves 20dB on emissionsSaves 20dB on emissions Preserves signal integrity properties of 8B10BPreserves signal integrity properties of 8B10B Essential for UTP-5Essential for UTP-5 A great help for system integration as wellA great help for system integration as well

Good News For UTP-5Good News For UTP-5

Binary signaling, bounded running disparity Binary signaling, bounded running disparity and limited run length all help to simplify and limited run length all help to simplify UTP analogUTP analog Substantially simpler than 100BASE-T, Substantially simpler than 100BASE-T,

e.g., no adaptive thresholdinge.g., no adaptive thresholding Less ISI for adaptive equalization to deal withLess ISI for adaptive equalization to deal with Overall signal integrity significantly better Overall signal integrity significantly better

than Ethernetthan Ethernet 1394b uses same RJ-45 connector1394b uses same RJ-45 connector

But uses pairs on pins 1/2 and 7/8But uses pairs on pins 1/2 and 7/8 Minimizes cross-talkMinimizes cross-talk Best pins for signal integrity (pair 3/6 and 4/5 are much Best pins for signal integrity (pair 3/6 and 4/5 are much

more problematic)more problematic)

UTP-5 - Problem-Free Wiring UTP-5 - Problem-Free Wiring

Polarity compensationPolarity compensation A common wiring error is to connect the two wires A common wiring error is to connect the two wires

in a twisted pair incorrectly - particularly in UTP in a twisted pair incorrectly - particularly in UTP building wiringbuilding wiring

1394b detects this at scrambler synchronization 1394b detects this at scrambler synchronization time and automatically compensatestime and automatically compensates

Pair-to-pair cross-over compensationPair-to-pair cross-over compensation Building wiring is usually “straight-thru” - Building wiring is usually “straight-thru” -

no crossoverno crossover But Ethernet normally requires a crossover - results in two But Ethernet normally requires a crossover - results in two

types of “patch cable”types of “patch cable” 1394b compensates for lack of crossover in UTP1394b compensates for lack of crossover in UTP

Result: no wiring problems, only a single type of patch Result: no wiring problems, only a single type of patch cable needed cable needed

Plastic Optic FiberPlastic Optic Fiber POF: 1000 µm plastic optic fiberPOF: 1000 µm plastic optic fiber

Suitable for S200 up to 50mSuitable for S200 up to 50m Improved version demonstrated at S400 for 100mImproved version demonstrated at S400 for 100m

Low cost, easy to installLow cost, easy to install Fiber alleviates emissions and interference problemsFiber alleviates emissions and interference problems Currently use PN connectorCurrently use PN connector

Japanese effort to define smaller, more friendly versionJapanese effort to define smaller, more friendly version Automotive version in developmentAutomotive version in development

Only 10m, smaller and more robust connectorOnly 10m, smaller and more robust connector

Glass Fiber (MMF)Glass Fiber (MMF) Leverage VCSEL (Vertical Cavity Surface Leverage VCSEL (Vertical Cavity Surface

Emitting Laser) technologyEmitting Laser) technology Leverage Fibre Channel and Gigabit Ethernet specificationsLeverage Fibre Channel and Gigabit Ethernet specifications 50 micron multimode fiber (MMF)50 micron multimode fiber (MMF)

Media spec’d to S3200, transceiver spec’d to S1600Media spec’d to S3200, transceiver spec’d to S1600 Transceiver @ S3200 is only open development itemTransceiver @ S3200 is only open development item

LC connectorLC connector

Reach S100 S200 S400 S800 S1600 S3200

UTP5 100m

POF/HPCF

100m (only50mfor

POF)

()for

newgener-ationPOF

MMF 100m ()

STP(Beta)

4.5m ()

STP(DS)

4.5m

Media SummaryMedia Summary

Integrated PHY and Link (“PIL”)

1394 enabled device1394 enabled devicee.g., PC, STB, etc.e.g., PC, STB, etc.

Internal Beta Internal Beta connectionsconnections

External Beta, External Beta, bilingual or bilingual or

Legacy Legacy connectionsconnections

Beta Link

New PC Integration ModelNew PC Integration Model

PC chipset vendor integrates “PIL” into chipsetPC chipset vendor integrates “PIL” into chipset PIL gate count relatively lowPIL gate count relatively low Fully enabled for 800 Mbit/sec and aboveFully enabled for 800 Mbit/sec and above

PC OEM chooses “FOP” based on market requirementsPC OEM chooses “FOP” based on market requirements Various choices of types and numbers of portsVarious choices of types and numbers of ports

Beta Beta connectionconnection

1394b 1394b fan-fan-out out PHY PHY

“FOP”“FOP”

1 port Beta-only PHY

Beta Beta connectionconnection

Integrated PHY and Link (“PIL”)

1394 Beta-only disk1394 Beta-only disk

External Beta, External Beta, bilingual or bilingual or

Legacy Legacy connectionsconnections

1394b 1394b fan-fan-out out PHY PHY

“FOP”“FOP”

1 port Beta-only PHY

Beta Link

1394b Disks?1394b Disks?

Absolutely! PIL-FOP model is ideal for storage OEMAbsolutely! PIL-FOP model is ideal for storage OEM Storage OEM uses PIL on diskStorage OEM uses PIL on disk

High volume internal storage uses low gate count High volume internal storage uses low gate count direct Beta interfacedirect Beta interface

External version use attached FOP for legacy interface or for External version use attached FOP for legacy interface or for RAID packagingRAID packaging

Only used for Only used for connection to connection to Legacy 1394Legacy 1394

ConclusionsConclusions

No change for software and applicationsNo change for software and applications All existing 1394 devices are “home network ready”All existing 1394 devices are “home network ready” Improvements:Improvements:

Lower cost and more flexible for the PC OEMLower cost and more flexible for the PC OEM Even more efficientEven more efficient Up to 1.6 Gbits/secUp to 1.6 Gbits/sec Up to 100mUp to 100m

Fully backwards compatibleFully backwards compatible Expect products this yearExpect products this year

Product already available using intermediate drafts of 1394bProduct already available using intermediate drafts of 1394b ““NEC Termboy” S200, 100m repeaterNEC Termboy” S200, 100m repeater

Call To Action!Call To Action!

Review 1394b specs ASAPReview 1394b specs ASAP Standard will go final late 2000Standard will go final late 2000 Chipsets will appear by 2001, get your Chipsets will appear by 2001, get your

preferences known NOW!preferences known NOW! You know how long it takes to roll You know how long it takes to roll

a new version!a new version! Review mechanical and electrical Review mechanical and electrical

requirements for connectorsrequirements for connectors Tooling for sockets is long lead time itemTooling for sockets is long lead time item

Plan on PIL-FOP interface modelPlan on PIL-FOP interface model External ports must be bilingualExternal ports must be bilingual Internal ports should be beta-capableInternal ports should be beta-capable

1394 On The Consumer PC1394 On The Consumer PC

Steve Bard Steve Bard Intel Mobile Computing GroupIntel Mobile Computing Group

Technology ConvergenceTechnology ConvergenceConsumer Content PCConsumer Content PC 1394 is the interconnect of choice 1394 is the interconnect of choice

between Consumer Electronics devicesbetween Consumer Electronics devices 1394 cost and power consumption are 1394 cost and power consumption are

concerns for low cost and power concerns for low cost and power constrained PC systemsconstrained PC systems

If 1394 is implemented in the PC, a need If 1394 is implemented in the PC, a need exists for long term Consumer exists for long term Consumer Electronic device interconnectivityElectronic device interconnectivity

1394b Offers Compelling PC 1394b Offers Compelling PC Benefits Over 1394aBenefits Over 1394a Long-term solutionLong-term solution

Provides 1394a-2000 interconnectivityProvides 1394a-2000 interconnectivity Lowest cost “future proof” solutionLowest cost “future proof” solution

Simple IP licensing – 25¢ per system to 1394LASimple IP licensing – 25¢ per system to 1394LA Any number of 1394 devices in a systemAny number of 1394 devices in a system Any number of ports on each deviceAny number of ports on each device

Best Power Conservation MechanismsBest Power Conservation Mechanisms Partitions cost for appropriate usePartitions cost for appropriate use Least system impact as technology advancesLeast system impact as technology advances PCI-interface silicon solutions expected soonPCI-interface silicon solutions expected soon

A New “Link” ModelA New “Link” Model

Serial versus parallel Serial versus parallel PHY/Link interfacePHY/Link interface 1394b “PIL” (PHY-Integrated-Link)1394b “PIL” (PHY-Integrated-Link)

OHCI 1.1 register compatible link with OHCI 1.1 register compatible link with integrated Beta only PHY portintegrated Beta only PHY port

Integrated OHCI 1.1 link and Beta Integrated OHCI 1.1 link and Beta port (fully functional)port (fully functional)

Capable of providing a serial Capable of providing a serial “PHY/Link” interface to a “PHY/Link” interface to a

Fan-Out-PHY (FOP)Fan-Out-PHY (FOP)

1394b Parallel PHY/Link Interface1394b Parallel PHY/Link Interface 1394b implementation like 1394a today:1394b implementation like 1394a today:

LINKLINK

PHYPHY

S100-800S100-800 Bilingual:Bilingual: Data-Strobe (Analog)Data-Strobe (Analog)

Common Mode Differential Common Mode Differential SignalingSignaling

Beta Mode (8b10b digital)Beta Mode (8b10b digital) Differential SignalingDifferential Signaling

OH

CI L

ink

OH

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ink

Ho

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e.g

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PHY/Link InterfacePHY/Link Interface

1394b1394bPHYPHY

D0-D7D0-D7

CTL0-CTL1CTL0-CTL1

LReqLReqPCLKPCLK

LPSLPSLinkOnLinkOn

(16 Signals)(16 Signals)

Diff_Transmit_Plus_1Diff_Transmit_Plus_1Diff_Transmit_Minus_1Diff_Transmit_Minus_1

Diff_Receive_Plus_1Diff_Receive_Plus_1Diff_ Receive _Minus_1Diff_ Receive _Minus_1





Data Strobe Mode: Data Strobe Mode: 1.030 - 2.015V 1.030 - 2.015V Common Mode Bias Common Mode Bias 172 - 265mV Diff. - 172 - 265mV Diff. - Signal type & speed Signal type & speed dependent (3.3V to dependent (3.3V to 5V PHY’s)5V PHY’s)

Beta Mode:Beta Mode:No Common Mode DC BiasNo Common Mode DC Bias8b10b digital encoded 600 – 800 mV 8b10b digital encoded 600 – 800 mV Diff. Signaling (1.8V & 2.5V PHY’s)Diff. Signaling (1.8V & 2.5V PHY’s)

BilingualBilingualPINTPINTLCLKLCLK

(OHCI 1.1 LINK/PHY8b10b (digital Only)

1394b)

8b10b Encoded 8b10b Encoded Digital Beta Mode Digital Beta Mode Serial PHY/Link Serial PHY/Link

InterfaceInterface

OH

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OH

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FOPFOP


Receive +Receive +Receive -Receive -

Diff_Transmit_MinusDiff_Transmit_Minus

Diff_Transmit_PlusDiff_Transmit_Plus

139

4b “

Bet

a-O

nly

” P

ort

139

4b “

Bet

a-O

nly

” P

ort

Data PortData PortExpansionExpansion

LinkOnLinkOn

Diff_Receive_MinusDiff_Receive_Minus

Diff_Receive_PlusDiff_Receive_Plus

Transmit +Transmit +Transmit -Transmit -





Border Node FOP: Border Node FOP: ““B” port Serial PHY/Link B” port Serial PHY/Link Interface with Three Data-Interface with Three Data-Strobe Expansion PortsStrobe Expansion Ports

FOP

S100-1600S100-1600

PILPIL

S100-400S100-400(Data Strobe – a (Data Strobe – a

border node example)border node example)

PIL

1394b Serial PHY/Link Interface1394b Serial PHY/Link Interface A 1394b PIL interface to FOP:A 1394b PIL interface to FOP:

(OHCI 1.1 LINK/PHY8b10b (digital only)

1394b)

OH

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PILPIL

The foundation for The foundation for 1394 in the PC1394 in the PC

8b10b Digital 8b10b Digital Encoded Beta Encoded Beta Mode Serial Mode Serial

PHY/Link PHY/Link InterfaceInterface

4 Signals4 SignalsS100-1600S100-1600

(Beta Mode Only)(Beta Mode Only)

A fully functional Beta Port!A fully functional Beta Port!

139

4b “

Bet

a-O

nly

” P

ort

139

4b “

Bet

a-O

nly

” P

ort

PIL

1394b Serial PHY/Link Interface1394b Serial PHY/Link Interface A 1394b PIL:A 1394b PIL:


The Fan-Out-PHYThe Fan-Out-PHY

No “Parallel” PHY/Link interfaceNo “Parallel” PHY/Link interface One “Beta-Only” PIL portOne “Beta-Only” PIL port Expansion ports:Expansion ports:

1394a only1394a only Beta onlyBeta only BilingualBilingual MixtureMixture

Versatile locationVersatile location On the system boardOn the system board In the AC power brick (mobile)In the AC power brick (mobile) In the cableIn the cable

FOP Configuration OneFOP Configuration One

Beta PIL port; 1394b Data Strobe Mode Beta PIL port; 1394b Data Strobe Mode expansion ports (example border node FOP):expansion ports (example border node FOP):

Border Node FOP: “B” PIL Border Node FOP: “B” PIL port (serial PHY/Link port (serial PHY/Link interface) with Three Data-interface) with Three Data-Strobe Expansion PortsStrobe Expansion Ports


FOP

FOPFOP



LinkOnLinkOn






S100-1600S100-1600S100-S400S100-S400

TPA1-PlusTPA1-PlusTPA1-MinusTPA1-Minus

TPB1-PlusTPB1-PlusTPB1-MinusTPB1-Minus





1394b DS = 1394a DS1394b DS = 1394a DS

FOP Configuration TwoFOP Configuration Two

Beta PIL port; 1394b Beta mode expansion ports:Beta PIL port; 1394b Beta mode expansion ports:

““B” PIL port (serial PHY/Link B” PIL port (serial PHY/Link interface) with Three Beta interface) with Three Beta Mode Expansion PortsMode Expansion Ports


FOP

S100-S1600S100-S1600







FOPFOP



LinkOnLinkOn






S100-1600S100-1600

FOP Configuration ThreeFOP Configuration Three

Beta PIL port; 1394b Bilingual (Beta Mode and Beta PIL port; 1394b Bilingual (Beta Mode and Data Strobe capable) expansion ports:Data Strobe capable) expansion ports:

““B” PIL port (serial B” PIL port (serial PHY/Link interface) with PHY/Link interface) with

Three Bilingual Expansion Three Bilingual Expansion PortsPorts


FOP

FOPFOP



LinkOnLinkOn






S100-1600S100-1600

S100-S1600 (Beta Mode)S100-S1600 (Beta Mode)S100-S400 (Data Strobe Mode)S100-S400 (Data Strobe Mode)







FOP Configuration FourFOP Configuration Four

Beta PIL port; 1394b Mixture (Beta Mode and Beta PIL port; 1394b Mixture (Beta Mode and Data Strobe Capable) Expansion Ports:Data Strobe Capable) Expansion Ports:

““B” PIL port (serial B” PIL port (serial PHY/Link interface) with PHY/Link interface) with Three Expansion Ports Three Expansion Ports

(One Beta Two Data (One Beta Two Data Strobe)Strobe)


FOPFOPFOP



LinkOnLinkOn






S100-1600S100-1600

S100-S1600 (Beta Mode)S100-S1600 (Beta Mode)

S100-S400S100-S400(Data Strobe Mode)(Data Strobe Mode)

Rec

eive

+R

ecei

ve +

Rec

eive

-R

ecei

ve -

Tra

nsm

it +

Tra

nsm

it +

Tra

nsm

it -

Tra

nsm

it -





Versatile FOP Locations…Versatile FOP Locations…

PC system opportunities...PC system opportunities...

1394 Consumer Electronic Device

LinkLink

Unit InterfaceUnit Interface

Beta Mode SignalingBeta Mode SignalingFOPFOP

1394b Serial 1394b Serial PHY/Link PHY/Link InterfaceInterface

PC SystemPC System

Two Ports: IEEE 1394a-2000Two Ports: IEEE 1394a-2000(PC Back Panel)(PC Back Panel)

One Port: 1394a Only One Port: 1394a Only or 1394b Bilingualor 1394b Bilingual

(PC Front Panel)(PC Front Panel)

OHCI 1.1 LinkOHCI 1.1 Link

Host Interface (e.g. PCI)

1394b Beta Port1394b Beta Port


PILPIL

Versatile FOP Location (Mobile)Versatile FOP Location (Mobile)

In the AC power brick (mobile)...In the AC power brick (mobile)...

FOPFOP

Beta PortBeta PortConnectionConnection

Power “Brick”Power “Brick”

Three Ports: Three Ports: IEEE 1394a-2000IEEE 1394a-2000

AC AC PowerPower

Beta Socket / PlugBeta Socket / Plug

Mobile PC Mobile PC SystemSystem



Host Interface (e.g. PCI)

Versatile FOP Location (Cable)Versatile FOP Location (Cable)

In the cable...In the cable...

IEEE 1394a-2000IEEE 1394a-2000Data Strobe ModeData Strobe Mode

IEEE 1394bIEEE 1394bBeta ModeBeta Mode

Beta PlugBeta PlugIEEE 1394bIEEE 1394b 1394a-20001394a-2000

4 Ckt. Plug4 Ckt. Plug

Embedded Embedded Two PortTwo PortBorder-NodeBorder-NodeFOPFOP

Mobile PC Mobile PC SystemSystem


Host Interface


Call To ActionCall To Action

Study IEEE P1394b Rev. 1.0 AmendmentStudy IEEE P1394b Rev. 1.0 Amendment Ballot draft has full specificationBallot draft has full specification Available for public review at: Available for public review at:

www.zayante.com/p1394bwww.zayante.com/p1394b 1394-enabled PC systems use the 1394-enabled PC systems use the

1394b PIL architecture1394b PIL architecture Fundamental 1394 building block Fundamental 1394 building block

for the PCfor the PC PCI-interface silicon solutions PCI-interface silicon solutions

expected soonexpected soon

Update On USB 2.0 Support Update On USB 2.0 Support For Microsoft WindowsFor Microsoft Windows

Robert IngmanRobert IngmanProgram Manager LeadProgram Manager LeadWindows DivisionWindows DivisionMicrosoft CorporationMicrosoft Corporation

Current Microsoft StatusCurrent Microsoft Status

New USB 2.0 driver stack up and runningNew USB 2.0 driver stack up and running New port driver New port driver New mini-port drivers for EHCI and OHCI New mini-port drivers for EHCI and OHCI

Early testing of driver stack withEarly testing of driver stack with 2 eval EHCI host controllers2 eval EHCI host controllers

First peripherals about to show upFirst peripherals about to show up Scanner, storage deviceScanner, storage device

USB 2.0 hubs not part of the mix yetUSB 2.0 hubs not part of the mix yet Hardware not yet availableHardware not yet available

Test tools being developed in parallelTest tools being developed in parallel

Microsoft’s Ship CriteriaMicrosoft’s Ship Criteria

Before Microsoft USB 2.0 driver stack Before Microsoft USB 2.0 driver stack ships, for any Windows OS, we need at ships, for any Windows OS, we need at least 3 months of solid end-to-end least 3 months of solid end-to-end testing with the following hardware:testing with the following hardware: Production-quality USB 2.0 host Production-quality USB 2.0 host

controllers from at least 2 vendorscontrollers from at least 2 vendors Production-quality USB 2.0 hubs from at Production-quality USB 2.0 hubs from at

least 3 vendorsleast 3 vendors Production-quality USB 2.0 peripherals Production-quality USB 2.0 peripherals

from at least 6 vendorsfrom at least 6 vendors

Microsoft’s PlanMicrosoft’s Plan

Tentative “early adopter” USB 2.0 Tentative “early adopter” USB 2.0 driver support for Windows 2000 driver support for Windows 2000 in Q4, 2000in Q4, 2000 Only if hardware is ready in timeOnly if hardware is ready in time

Tentative USB 2.0 support in Tentative USB 2.0 support in Windows “Whistler” in 2001 Windows “Whistler” in 2001

Tentative back-ports of USB 2.0 Tentative back-ports of USB 2.0 driver support for Windows Me and driver support for Windows Me and Windows 98 SE by mid-2001Windows 98 SE by mid-2001

Why Windows 2000 First?Why Windows 2000 First?

Windows 2000 is our USB 2.0 Windows 2000 is our USB 2.0 development platformdevelopment platform We develop and test on Windows 2000 first anywayWe develop and test on Windows 2000 first anyway Reduces riskReduces risk Reduces test burdenReduces test burden

Windows 2000 is now Microsoft’s strategic Windows 2000 is now Microsoft’s strategic foundation for all future OS effortsfoundation for all future OS efforts Paves the way for USB 2.0 support in Paves the way for USB 2.0 support in

Windows “Whistler” and beyond Windows “Whistler” and beyond Enables early focus on business customers Enables early focus on business customers

and “prosumers” and “prosumers”


““Early adopter” USB 2.0 driver support Early adopter” USB 2.0 driver support for Windows 2000 in Q4, 2000 is gated for Windows 2000 in Q4, 2000 is gated on hardware availabilityon hardware availability CONTACT US NOW if you are ready to CONTACT US NOW if you are ready to

participate in this effort participate in this effort New USB 2.0 hardware is always New USB 2.0 hardware is always

welcome at anytime, of coursewelcome at anytime, of course Contact us at: Contact us at:

[email protected]@MICROSOFT.COM

USB 2.0USB 2.0The Development Of The Development Of A High-Speed DeviceA High-Speed Device

Ed BeemanEd BeemanProduct Line ArchitectProduct Line ArchitectGreeley Hardcopy DivisionGreeley Hardcopy DivisionHewlett-PackardHewlett-Packard

AgendaAgenda

OverviewOverview When to build a high-speed deviceWhen to build a high-speed device Status of high-speed scanner Status of high-speed scanner

developmentdevelopment How to build a high-speed deviceHow to build a high-speed device

Options 1, 2, and 3Options 1, 2, and 3 Building block availabilityBuilding block availability Lessons learnedLessons learned

Overview Overview Sample USB 2.0 topologySample USB 2.0 topology

Hub provides high-speed (HS) expansionHub provides high-speed (HS) expansion Hub provides additional low-speed(LS) and Hub provides additional low-speed(LS) and

full-speed (FS) busesfull-speed (FS) buses

System SWSystem SW

Client DriverClient Driver Client DriverClient Driver

USB 1.1 USB 1.1 HubHub

USB USB 1.1 1.1

DeviceDevice

USB USB 1.1 1.1

DeviceDevice

HS HubHS HubHS HubHS Hub

USB 1.1 USB 1.1 HubHub

USB USB 1.1 1.1

DeviceDevice

USB USB 1.1 1.1

DeviceDevice

HS DeviceHS DeviceHS DeviceHS Device

USB 2.0 HostUSB 2.0 HostControllerController

USB 2.0 HostUSB 2.0 HostControllerController

Full/Low SpeedFull/Low Speed

High Speed OnlyHigh Speed Only

(2 x 12Mb/s(2 x 12Mb/sCapacity)Capacity)

Overview Overview USB 2.0 deployment milestonesUSB 2.0 deployment milestones

Watch for USB 2.0 spec at Watch for USB 2.0 spec at http://www.usb.org/developers/http://www.usb.org/developers/

Leading systems and peripherals Leading systems and peripherals expected in the marketplace in Q4 ’00expected in the marketplace in Q4 ’00

Widespread system and peripheral Widespread system and peripheral availability by mid-2001availability by mid-2001

Note: All dates provided are for planning purposes only and are subject to change.Note: All dates provided are for planning purposes only and are subject to change.

When To Build A HS Device When To Build A HS Device Should I wait for the installed base?Should I wait for the installed base?

HostsHosts CostsCosts

Discrete Host Controllers H2 ’00Discrete Host Controllers H2 ’00 Integrated solutions by 2001Integrated solutions by 2001

BenefitsBenefits Improved performance – even for Improved performance – even for

USB 1.1 devicesUSB 1.1 devices Latest technology messageLatest technology message

Low cost – immediate benefit - Low cost – immediate benefit - No need to waitNo need to wait

When To Build A HS DeviceWhen To Build A HS DeviceShould I wait for the installed base?Should I wait for the installed base?

PeripheralsPeripherals CostsCosts

Discrete transceivers now - $2-$5Discrete transceivers now - $2-$5 USB 1.1 discrete transceiver now - <$1USB 1.1 discrete transceiver now - <$1

ASIC integration by H2 ’00 - <$1ASIC integration by H2 ’00 - <$1 BenefitsBenefits

Higher speedHigher speed HS/FS devices work with installed baseHS/FS devices work with installed base

Low cost – immediate benefit - Low cost – immediate benefit - No need to waitNo need to wait

DemoDemo

HP ScanJet scanner connected HP ScanJet scanner connected to USB 1.1 host and then to USB 2.0 to USB 1.1 host and then to USB 2.0 hosthost Status updateStatus update

How To Build A HS DeviceHow To Build A HS DeviceOption 1 – Discrete transceiverOption 1 – Discrete transceiver

+ 1st part availability+ 1st part availability + 480 Mbit contained+ 480 Mbit contained - High pin count- High pin count

FPGAFPGAFPGAFPGAASICASICASICASIC

Serial Interface Engine

DeviceDeviceSpecificSpecific

LogicLogic

Endpoint Logic

Endpoint Logic

…SIE

Control Logic

USB 2.0USB 2.0Endpoint Logic

Device Device HardwareHardware

USB 2.0 USB 2.0 TransceiverTransceiver


HS Discrete TransceiverHS Discrete Transceiver

Has to be a parallel interface on function sideHas to be a parallel interface on function side 8-bit parallel interface difficult to connect to8-bit parallel interface difficult to connect to

Has to run at 60MHzHas to run at 60MHz Hard to do with FPGA’sHard to do with FPGA’s

16-bit parallel interface severely 16-bit parallel interface severely pin constrainedpin constrained Package cost dwarfs silicon costPackage cost dwarfs silicon cost Easy to connect to (runs at 30MHz)Easy to connect to (runs at 30MHz)

Can add functionality to increase silicon valueCan add functionality to increase silicon value SIE, DMA,…but that limits scopeSIE, DMA,…but that limits scope

Result is high costResult is high cost

How To Build A HS DeviceHow To Build A HS DeviceOption 2 – Micro-controllerOption 2 – Micro-controller

+ + Quickest time to marketQuickest time to market + Low pin count+ Low pin count + Focus on device specific functions+ Focus on device specific functions - Moderate cost- Moderate cost

USB 2.0 Micro-ControllerUSB 2.0 Micro-ControllerUSB 2.0 Micro-ControllerUSB 2.0 Micro-ControllerASICASICASICASIC

Serial Interface EngineSerial Interface Engine


LogicLogic

Endpoint Logic

Endpoint Logic

…SIE

Control Logic





How To Build A HS DeviceHow To Build A HS DeviceOption 3 – Fully integrated ASICOption 3 – Fully integrated ASIC

- Longer design/qualification times- Longer design/qualification times + Lower cost for high volume product+ Lower cost for high volume product

ASICASICASICASIC

Serial Interface EngineSerial Interface Engine


LogicLogic


LogicLogic

Endpoint Logic

Endpoint Logic

…SIE

Control Logic





Fully Integrated ASICFully Integrated ASIC

Standard gates won’t work Standard gates won’t work for transceiverfor transceiver Bit rates over ~150Mb/s require Bit rates over ~150Mb/s require

custom designcustom design Clock recovery, squelch, bitstuff, CRCClock recovery, squelch, bitstuff, CRC

Custom design is outside the scope Custom design is outside the scope of many IHVsof many IHVs

How does USB 2.0 get into an ASIC?How does USB 2.0 get into an ASIC? USB 2.0 transceiver macrocellUSB 2.0 transceiver macrocell

Fully Integrated ASIC Fully Integrated ASIC Transceiver macrocellTransceiver macrocell

Standard cell available in Standard cell available in foundry libraryfoundry library Easily connects to standard gates Easily connects to standard gates

Macrocell has standard interface Macrocell has standard interface across all foundriesacross all foundries

Current Macrocell Interface Current Macrocell Interface specification is posted at specification is posted at members.usb.orgmembers.usb.org

Transceiver Block DiagramTransceiver Block Diagram

ControlControlControlControlControlControl

D-D-

D+D+

DLLDLLDLLDLL

FSFSInterfaceInterface

HSHSInterfaceInterface

Shared LogicShared LogicShared LogicShared Logic

ParallelParallelInterfaceInterfaceParallelParallel

InterfaceInterface

DLLDLLDLLDLLmuxmuxmuxmux

BitBitUnstufferUnstuffer

BitBitUnstufferUnstuffer DeserializerDeserializerDeserializerDeserializer RX HoldingRX Holding

RegRegRX HoldingRX Holding

RegReg

BitBitStufferStuffer

BitBitStufferStuffer SerializerSerializerSerializerSerializer TX HoldingTX Holding

RegRegTX HoldingTX Holding

RegReg

ToToSIESIE

DataData

ToToUSBUSB

Building Block Availability Building Block Availability Schedules and vendorsSchedules and vendors

Microcontroller with USB 2.0 integratedMicrocontroller with USB 2.0 integrated Available in H2 ’00Available in H2 ’00

Discrete transceiverDiscrete transceiver Engineering samples in Q2 ’00Engineering samples in Q2 ’00 In production early Q3 ’00In production early Q3 ’00

Transceiver MacrocellTransceiver Macrocell In foundry libraries before end of the yearIn foundry libraries before end of the year

For a list of USB 2.0 building block vendors, For a list of USB 2.0 building block vendors, see www.usb.org/developerssee www.usb.org/developers

Note: All dates provided are for planning purposes only and are subject to change.Note: All dates provided are for planning purposes only and are subject to change.

Lessons Learned Lessons Learned PCB layout concernsPCB layout concerns

GroundingGrounding Short tracesShort traces 30 MHz versus 60 MHz30 MHz versus 60 MHz

Lessons Learned Lessons Learned Software concerns are fewSoftware concerns are few

Standard application softwareStandard application software Same software used with two-year old FS Same software used with two-year old FS

scanner product scanner product

Standard Imaging Class driverStandard Imaging Class driver Same software used with two-year old FS Same software used with two-year old FS

scanner productscanner product

Lessons Learned Lessons Learned Comparisons to USB 1.1 developmentComparisons to USB 1.1 development

Tools - CATC analyzer available for Tools - CATC analyzer available for bothboth

No reason to wait for installed base this No reason to wait for installed base this timetime Test functionality with 1.1, then add Test functionality with 1.1, then add

HS functionHS function Issues with high-speed FPGA designs Issues with high-speed FPGA designs Cable compatibility issuesCable compatibility issues

Expanding The USB Expanding The USB Compliance ProgramCompliance Program

Jason ZillerJason ZillerTechnology Initiatives ManagerTechnology Initiatives ManagerIntel CorporationIntel CorporationChairman, USB Implementers Forum Chairman, USB Implementers Forum

Why Expand USB Why Expand USB Compliance Program?Compliance Program? USB products are not perfect in USB products are not perfect in

the marketplacethe marketplace Compliance testing is voluntary and has Compliance testing is voluntary and has

limited availabilitylimited availability Not enough incentive to pass testingNot enough incentive to pass testing

Non-compliant product still use USB Non-compliant product still use USB name and logoname and logo

Headroom goes away on USB 2.0…Headroom goes away on USB 2.0…

New Compliance New Compliance Program ModelProgram Model

Testing available Testing available to vendors anytime to vendors anytime through 3rd party through 3rd party

test housestest houses

Testing available Testing available to vendors anytime to vendors anytime through 3rd party through 3rd party

test housestest houses

Testing availabilityTesting availabilityneeded to implementneeded to implement

incentive programincentive program

Logo license provides Logo license provides incentive for vendors incentive for vendors to perform and pass to perform and pass compliance testingcompliance testing

Logo license provides Logo license provides incentive for vendors incentive for vendors to perform and pass to perform and pass compliance testingcompliance testing

Both testing and incentive are dependent upon each other for successBoth testing and incentive are dependent upon each other for success

Vendor incentiveVendor incentiveneeded for feasible needed for feasible

test house test house business modelbusiness model

Testing AvailabilityTesting Availability

Cables, peripherals and hubs Cables, peripherals and hubs can test in independent labscan test in independent labs

Testing any time for a priceTesting any time for a price Integrators listing, certificates and Integrators listing, certificates and

logo rights without a Plugfestlogo rights without a Plugfest Plugfest will offer Interoperability Plugfest will offer Interoperability

testing not obtainable anywhere elsetesting not obtainable anywhere else Plugfest will offer first high Plugfest will offer first high

speed (USB 2.0) testingspeed (USB 2.0) testing

Cable And Connector Cable And Connector Testing AvailabilityTesting Availability A2LA Certified labs test USB cablesA2LA Certified labs test USB cables

Use Cable and Connector Device Use Cable and Connector Device Class documentClass document

Two labs currently testingTwo labs currently testing Contech and NTSContech and NTS Contact info on Contact info on www.usb.orgwww.usb.org

USB-IF lists all passing cables USB-IF lists all passing cables and connectors and connectors In USB-IF Integrators List on the WebIn USB-IF Integrators List on the Web

Vendor IncentiveVendor Incentive

Issue certificatesIssue certificates New trademarked logoNew trademarked logo Listing of compliant cables Listing of compliant cables

to ship with peripheralto ship with peripheral Promote new list with members Promote new list with members

product search listproduct search list >150K visitors per month to product >150K visitors per month to product

search pagesearch page Channel, Press use product search listChannel, Press use product search list

NEWNEWNEWNEWNEWNEWNEWNEW

NEWNEWNEWNEW

Logo Incentive ModelLogo Incentive Model

LogoLogo

Peripheral VendorsPeripheral Vendors

ChannelChannel UsersUsers

Conveys exciting

Conveys exciting

message (hi-s

peed?)

message (hi-s

peed?)Education:

Education:

logo=compliance

logo=compliance

Vendors want Vendors want to use logoto use logo

Channel Channel requires logorequires logo

Users buy productsUsers buy productswith logowith logo

Objective: Create incentive for vendors to use logo Objective: Create incentive for vendors to use logo

Logo Positioning/Logo Positioning/Key MessagesKey Messages Core = USB goodness (simple, Core = USB goodness (simple,

speedy, expandable)speedy, expandable) Message to users: New and excitingMessage to users: New and exciting

Optional identifier for high-speed productOptional identifier for high-speed product Message to channel: ComplianceMessage to channel: Compliance

Identified as passing USB-IF Identified as passing USB-IF compliance testingcompliance testing

“HI-SPEED”

USB“USB-IF Listed”

Concept onlyConcept only

Key EventsKey Events

PIMC had test suite in March PlugfestPIMC had test suite in March Plugfest Ran a correlation with USB-IF suiteRan a correlation with USB-IF suite

Labs can open for businessLabs can open for business After certification by USB-IFAfter certification by USB-IF

USB-IF begins to accept lab results USB-IF begins to accept lab results For Integrators List, Logo, and certificateFor Integrators List, Logo, and certificate

USB-IF Peripheral Test Spec completeUSB-IF Peripheral Test Spec complete Validated in USB-IF PlugfestsValidated in USB-IF Plugfests Q2 ’00Q2 ’00

Spec approved by industrySpec approved by industry Q2 ’00Q2 ’00

Third-party labs offer USB peripheral testing Third-party labs offer USB peripheral testing service to industryservice to industry Mid 2000Mid 2000

First products with new licensed USB logo on First products with new licensed USB logo on the package are in channels and in storesthe package are in channels and in stores Holiday 2000Holiday 2000

MilestonesMilestones


Review the USB-IF Peripheral Test Review the USB-IF Peripheral Test Spec and provide feedbackSpec and provide feedback members.usb.orgmembers.usb.org

Locate USB-IF approved third-party Locate USB-IF approved third-party test lab near youtest lab near you Send devices to third-party labs Send devices to third-party labs

to get logoto get logo Continue to bring devices to Continue to bring devices to

USB-IF PlugfestsUSB-IF Plugfests

External I/O Bus Scott Fierstein Technical Evangelist Consumer AV Platforms and Networking, IEEE...

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