Expo Potencia en Fpga
-
Upload
jaime-andres-salazar -
Category
Documents
-
view
218 -
download
0
Transcript of Expo Potencia en Fpga
-
7/31/2019 Expo Potencia en Fpga
1/27
POWERDISSIPATIONINFPGA
DEVICES
RICHARDFABIANRODRIGUEZ
JAIMEANDRESSALAZARUNIVERSIDADDELVALLE
-
7/31/2019 Expo Potencia en Fpga
2/27
CONTENT
1. INTRODUCTION2. POWERDISSIPATION:concept,components
andequaon.
3. POWERESTIMATIONTECHNIQUEFORFPGA.3.1-Switchingacvity
3.2-Capacitance
4.FPGAvs.ASIC
5.CONCLUSIONS
-
7/31/2019 Expo Potencia en Fpga
3/27
1.INTRODUCTION
Developmentofportablecompungsystem. PowerdissipaonisbecomingoneofthemostimportantissuetoconsiderinthedesignofFPGAbasedsystems. FPGAisbecomingmorepopularbecauseCMOStechnology
improvesatanexponenalratebutpowerdissipaondiffersalotcomparedtoASICbasedsystems.
-
7/31/2019 Expo Potencia en Fpga
4/27
2.POWERDISSIPATION
ASICpowercomponents:Dynamicandstaccomponents.Junconleakageandtunnelinggatecurrentsare
notconsidered.
FPGApowercomponents(all3withdynamicand
staccomponents): Powerupcomponent. Configuraoncomponent.
Execuoncomponent.
-
7/31/2019 Expo Potencia en Fpga
5/27
Firstterm=dynamicpower.ExponenalVdd. Secondterm=stacpower.
Vdd=voltagesourcesupply. C=parasiccapacitance. F=operangfrequency. =acvityofthecircuit. Vt=thresholdvoltageofthetransistor. S=slopefactor. U=ulizaonofaresource. Si=switchingacvityofaresource. i=numberofaresourceinaFPGA. Io=reversecurrent.
-
7/31/2019 Expo Potencia en Fpga
6/27
3.POWERESTIMATIONTECHIQUEFOR
FPGAs
TheworkofJasonH.AndersonandFaridNajm,showsamethodbycalculangFPGApowerconsumponbyFPGAinterconnect.Theystudiedtwospecialproblems:
Switchingacvitypredicon. Interconnectcapacitancepredicon.
Theyproposeamodelforpredicngtheseparameterswhenaccurateroungdataisincompleteorunavailable.
InthisstudyitisuseXilinxVirtexIIPROcommercialFPGAforinvesgaon.
Switchingacvityisstudiedandexamineifzerodelayacvityvaluescanbeusedreliablyasesmatesofthecalculaonofrouteddelayacvityvalues.
-
7/31/2019 Expo Potencia en Fpga
7/27
PrediconMethodologyOverview
Targetparameters: Netsrouteddelayacvitypredicon. Interconnectcapacitancepredicon.
Prediconparameters:valuesknowbeforeroungcompleon. Generalsteps:
AsetofbenchmarkcircuitsareselectedandmappedintoVirtexIIPRO.
Thecircuitsaredividedintotwosets:characteriza3onsetandtestset.
Thecharacterizaoncircuitsareanalyzedandprediconandtargetparametersvaluesareextracted.
Thenwiththeseparameters,theyperformmul-variableregressionanalysistoestablishanempiricalrelaonshipbetweenthese.
Applyprediconmodelstopredictcapacitanceandrouteddelayacvityvaluesfornetsinthetestcircuits.
-
7/31/2019 Expo Potencia en Fpga
8/27
3.1SwitchingAcvity
SwitchingacvityofanetinaFPGAissignificantinthecalculaonofpower.
Wecanconceivedifferentviewsofthisacvity: Zerodelayacvity Logicdelayacvity Routeddelayacvity.
Whendelaysareconsidered,switchingacvitynormallyincreasesbecausetheintroduconofglitches.
Anunderstandingofhowswitchingacvitychangeswhendelaysareconsideredisimportantbecause:
FPGApowerdissipaonisdominatedbyinterconnecon. Duetothepresenceofprogrammableswitchesintheinterconneconnetwork,pathdelaysinFPGAsaredominatedbyinterconnectratherthanbylogicdelays,suggesngthetheeffectofglitcheswillbegreaterinFPGAsthaninASIC.
-
7/31/2019 Expo Potencia en Fpga
9/27
SwitchingAcvityAnalysis
Simulaon-basedapproachusing10krandominputvector. Twodifferentvectorsets:representshighinputacvityand
lowinputacvity.
Tabulaonofcomparisonoftotalnumbertransioninthelogicandrouteddelaysimulaonsofeachcircuit,withthenumberoftransionsinthezerodelaysimulaon.
Significantincreaseinacvitywhendelaysareconsidered.Theincreaseinacvityaresomehowlessdrascwhenlowacvityvectorsetwereused.
Conclusion:zeroandlogicdelayacvityvaluesdonotnecessarilycorrelatestronglywithrouteddelayacvityvalues.
-
7/31/2019 Expo Potencia en Fpga
10/27
SwitchingAcvityPrediconModel
ThecombinaonalpartofalogiccircuitcanberepresentedasaBooleanNetwork.
BooleanNetwork:directedacyclicgraph(DAG).Node:single-outputlogicfuncon.Edgesbetweennodes:input-output
dependenciesbetweenthecorrespondinglogicfuncons.
ForanodeyinacircuitDAG: Inputs(y)=thesetofnodesthatarefaninsofy.Depthofanodey(Dy)=thelengthofthelongestpathfromanyprimaryinputtoy.
-
7/31/2019 Expo Potencia en Fpga
11/27
SwitchingAcvityPrediconModel
PRy:Predicvefunconthatrepresents
theseverityofglitchingonysoutputs.
GENy:Amountofglitchinggeneratedby
y.
PROPy:Amountofglitchingpropagated
byysinputs.
Dy:Depthofthenodey.
PLy:representthesetofdifferentpath
lengthsfromaprimaryinputtonode.
-
7/31/2019 Expo Potencia en Fpga
12/27
GENy:Amountofglitchinggeneratedbyy.
PROPy:Amountofglitchingpropagatedbyysinputs.
-
7/31/2019 Expo Potencia en Fpga
13/27
3.2Capacitance
EarlycapacitanceprediconforFPGAsisnotwellstudied,andisverydifferenttocalculateitinFPGAsthaninASICbecause
oftheprogrammablenatureofFPGAinterconnecon.
Earlyworksforesmatescapacitancevaluesusedgeneric,non-architecturespecificparameterstopredictit.
-
7/31/2019 Expo Potencia en Fpga
14/27
InterconnectCapacitancePredicon
Model
CADapplicaonsaredesignedtocalculatecapacitanceveryquicklyastheyare
neededtotheinnerloopofdesignandsimulaonsalgorithms.Soparametersare
chosenbyalowcomputaonalcriteria.Someofthesearenotneededbuttheyare
menoned.
-
7/31/2019 Expo Potencia en Fpga
15/27
Results
-
7/31/2019 Expo Potencia en Fpga
16/27
4.Powerdissipaon:
FPGAvs.ASIC
Vdd=voltagesourcesupply.
Vt=thresholdvoltageofthetransistor.
ASIC:
-
7/31/2019 Expo Potencia en Fpga
17/27
4.1ASIC
-
7/31/2019 Expo Potencia en Fpga
18/27
ASIC
AllthesetechniquesareASICorientedand
theirefficiencywhenimplementedinFPGA
hasnotyetbeendemonstrated.
-
7/31/2019 Expo Potencia en Fpga
19/27
4.2FPGA
Therearethreepowercomponents:
Power-upcomponentConfiguraoncomponent
Execuoncomponent
-
7/31/2019 Expo Potencia en Fpga
20/27
4.3ExperimentalResults
ASIC:SynopsysDesignCompiler,PowerCompiler,VCS,PrimePower.
FPGA:QuartusIIv4.2,Powerplay.
-
7/31/2019 Expo Potencia en Fpga
21/27
4.3.1Counters
-
7/31/2019 Expo Potencia en Fpga
22/27
4.3.1Counters
-
7/31/2019 Expo Potencia en Fpga
23/27
4.3.2HadamardTransformIP
-
7/31/2019 Expo Potencia en Fpga
24/27
4.3.2HadamardTransformIP
IPpowerdissipaoninASIC
-
7/31/2019 Expo Potencia en Fpga
25/27
4.3.2HadamardTransformIP
-
7/31/2019 Expo Potencia en Fpga
26/27
5.CONCLUSIONS
FPGAdeviceswillnevercompetewithASICforapplicaonswherelowpowerisanissue
becausetheirintrinsicgenericarchitecture.
TheFPGAwillbeconfinedtocircuitprototypingforfunconalvalidaonor
reconfigurablecompung.
-
7/31/2019 Expo Potencia en Fpga
27/27
BIBLIOGRAPHICREFERNCES
[1]AMARAAMARA,FredericyAMIEL,Thomas.FPGAvs.ASICforlowpowerapplica3onsInstutoSuperiordeElectronica
deParis.2005.
[2]ANDERSON,JasonH.NAJM,FaridN.Poweres3ma3onTechniquesforFPGAs2004.