Exploring the Silicon Design Limits of Thin Wafer IGBT Technology

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Exploring the Silicon Design Limits of

Thin Wafer IGBT Technology:

The Controlled Punch Through (CPT) IGBT

J . Vobeck, M. Rahimo, A. Kopta, S. Linder

ISPSD, May 2008, Orlando, USA

Copyright [2008] IEEE. Reprinted from the International Symposium on PowerSemiconductor Devices & IC's.

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Exploring the Silicon Design Limits of

Thin Wafer IGBT Technology:

The Controlled Punch Through (CPT) IGBT

J. Vobeck, M. Rahimo, A. Kopta, S. LinderABB Switzerland Ltd, Semiconductors, Fabrikstrasse 3, CH - 5600 Lenzburg, Switzerland

Abstract-The paper introduces a new Controlled Punch Through(CPT) IGBT buffer for next generation devices, which utilise thin

wafers technology. The new concept is based on very shallow

buffers with optimized doping profiles enabling minimum silicon

design thicknesses close to the theoretical limit for a given voltage

class. The advanced shaping of the buffer doping profile brings

additional degree of freedom in IGBT design. The work was car-

ried out for 1200V IGBTs, but the CPT buffer can be applied with

advantages to any voltage class. While this approach is targeting

mainly reduced ON-State losses, the IGBT maintains good block-

ing, soft turn-off, wide SOA and good short circuit capability.

I. INTRODUCTION

Thin wafer technology processing for the IGBT has seen con-

tinuous developments in the past ten years especially for powerdevices rated below 2000V. The introduction of Soft/LightPunch Through/Field Stop buffer concepts has enabled modern

IGBTs to achieve very low losses due to the very thin siliconspecifications for a given voltage class [1][2][3]. However,

current SPT/FS type buffer designs are more and more ap-proaching the silicon design limits and time comes to considera new and more efficient buffer concept for further loss reduc-

tions while retaining good overall performance.

Todays 1200V IGBT are designed with a total thickness rang-

ing between 120 m up to 140 m. A large portion (25%-30%)of this thickness consists of the buffer region. The main pur-pose for such a thick buffer is to ensure good and controllable

switching behaviour (softness) and stable reverse blocking. Thebuffer is relatively low doped and does not effectively utilizesilicon thus giving a potential for further improvement of total

IGBT losses. In addition, other performance parameters such asleakage current at higher operating temperatures and the rug-gedness under short circuit conditions are heavily influenced

by the bipolar transistor gain, which is largely dependent on the

shape of the buffer design and the anode strength [4]. Last butnot least, thin wafer processing requires that the majority of the

backside processing is done after the front side cathode is com-pleted, including metallisation. This limits the temperaturetreatments after thinning to below 500C and so the means forforming both the buffer and anode regions are very limited. Inspite of such obstacles, the new concept of a very thin Con-

trolled-Punch-Through (CPT) buffer keeping all common re-quirements laid on the state-of-the-art SPT-IGBT is proposedin Fig.1 and described below.

Fig.1: SPT IGBT (top) and the new CPT-IGBT (bottom).

II. THIN BUFFER OPTIMIZATION

Using the existing SPT buffer for the 1200V IGBT, the rate ofreduction the ON-State voltage VCEsat with decreasing thick-

ness is 5 mV/m at 25oC and 9 mV/m at 125oC. However,by doing so, the breakdown voltage VBR is reduced by about

7 V/m at 25oC. Hence, the reduction from the current thick-

ness down to 100 m decreases VCEsat by approximately

300 mV, while VBR drops well below 1200 V. In order to re-cover VBR back to above 1200 V, the point of stopping theelectric field must be moved closer to the anode by about 15 -

20 m. The simplest way consists of replacing the SPT buffer

by a narrow Gaussian profile as shown for a 100 m thick de-vice in Fig.2a. This "Single buffer" can be obtained by ion im-plantation and subsequent annealing. While the positioning of

this peak relatively to anode does not change VCEsat, it affects

mainly the VBR and especially the leakage current. To obtainlow leakage and high VBR, the buffer must be positioned awayfrom the anode and its concentration well above 1x1016 cm-3.To rely on precise and reproducible processing of the singlepeak with concentrations above 1x1016 cm-3 using post implan-

tation annealing below 500oC at aggressively thinned wafers is

impractical. Moreover, there is an insufficient degree of free-dom for setting all relevant parameters which are usually acting

in trade-offs. Such drawbacks may be eliminated by the intro-duction of a second buffer peak as shown below.

ABB Switzerland Ltd.

ISPSD Page 1 of 4 Orlando 2008


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Fig.2b shows a "double buffer" that consists of two Gaussian

peaks. The first one (N1) is placed at a certain distance fromthe anode and its role is to fully stop the electric field and keepthe base width of PNP transistor independent of applied anode

voltage. The second buffer (N2) is adjacent to the anode withthe purpose of adjusting an optimal bipolar transistor gain evenwhen utilizing high anode strengths. While the influence ofbuffers' parameters on the VCEsat is quantitatively similar, the

leakage current is suppressed already from a peak concentra-tion of N1 = 5x10

15cm

-3and VBR is increased as well. A suit-

able choice of various buffer peak concentrations N1 and N2already brings a sufficient degree of freedom to the overalldevice design. The degree of freedom can be extended by

modifying the donor concentration between N1 and N2 by in-complete annealing of implantation defects below 500

oC.

SPT Buffer

Anode

Single Buffer N

P

1x1015

1x1016

1x1017

1.60

1.65

1.70

1.75

Single Buffer: depth1



VCESAT

(V)

Buffer Peak Concentration (cm-3)

1x1015

1x1016

1x1017

500

600

700

800

900

1000

11001200




BreakdownVoltage(V

)


Buffer Peak

Concentration

1x1015

1x1016

1x1017

0

10

20

3040

50

60 Single Buffer: depth1



LeakageCurrent

(a.u.)


Depth

Fig. 2a: Simulated static parameters of the IGBT with a single peak N-buffer

and total thickness of 100 m. Vcesat is simulated at T = 400K, the breakdown

voltage and leakage current at T = 300K. The buffer depth from the anode is

varied in the order ofm: depth3>depth2 >depth1. Depth1 represents a buffer

connected to the anode. Anode doping is identical for all simulated points.

The incomplete annealing modifies carrier lifetime within the

buffer. As this controls the recombination rate in the base ofthe PNP transistor, it also modifies the bipolar gain and herebyrelevant device parameters. All this results in what we refer to

as the Controlled-Punch-Through (CPT) Buffer that is illus-trated in Fig.2b) (hollow circles, top).

The overall concept of the ON-state loss reduction is schemati-

cally summarized in Fig.1. The vertical arrow shows the pointof stopping the electric field. It is actually the much steeper and

higher doping profile of the CPT buffer N1 at the point of stop-ping the electric field that allows for reduction of the overallbuffer thickness. The missing part of the SPT buffer is then

more efficiently compensated for by the buffer peak N2.

1x1015

1x1016

1x1017

0

10

20

30

40

50

60 Double Buffer N1=2.1015

cm-3

Double Buffer N1=5.1015

cm-3


cm-3

LeakageCurrent

(a.u.)

Buffer N2 Peak Concentration (cm-3)

1x1015

1x1016

1x1017

500

600

700

800

900

1000

11001200


cm-3


cm-3


cm-3

BreakdownVoltage(V

)


1x1015

1x1016

1x1017

1.60

1.65

1.70

1.75Double Buffer N1=2.10

15cm

-3


cm-3


cm-3

VCESAT

(V)


0.5 0.6 0.7 0.8 0.9 1.0

100

101

102

103

104

Doping

Concentration(a.u.)

Depth (a. u.)

SPT Buffer

Anode

Double Buffer

CPT BufferN2N1

P

Fig. 2b Simulated static parameters of the IGBT with a double peak N-buffer

and total thickness of 100 m. Vcesat is simulated at T = 400K, the breakdown

voltage and leakage current at T = 300K. The CPT buffer is shown without any

electrical data for illustration (top). The arrows show the area of practical im-

portance. Anode doping is identical for all simulated points.




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III. EXPERIMENTAL RESULTS

The new buffer design was implemented on 100A/1200V

IGBT devices with an active area of 1cm2. This device also

incorporates additional enhancement of the planar cell designfor further loss reduction schematically shown in Fig.3 [5].

Fig. 3 The concept of Enhanced Planar (EP) IGBT.

The positive effect of the second buffer peak N2 on the reduc-

tion of leakage current simulated in Fig.2b) is experimentallyacknowledged in Fig.4 for devices thinned to ~100um. Thesmaller rise of leakage with increasing voltage and reduced

spread in the leakage current values between individual sam-ples with the double buffer is obvious.

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

200 300 400 500 600 700 800 900

Blocking Voltage (V)

LeakageCurrenta

t125C(mA)

Double Buffer

Single Buffer

Fig. 4 Leakage current for 100A/1200V IGBTs with Single N1 and Double

Buffer peaks N1 and N2.

Fig.5 shows the technology points (VCE vs. Eoff) of the standard

Enhanced Planar (EP) 1200V SPT-IGBT, and the Optimized

EP 1200V SPT-IGBT. Fig.5 also includes the latest cathodetechnology implemented on the CPT-IGBT having a 25% thin-

ner silicon substrate (thickness ~ 100um) with different anodestrengths (A, B & C).During this work, the doping concentra-tion of the silicon base regions was unaltered to evaluate the

effect of the thickness alone on device softness. The total VCEsatreduction for the same Eoff was around 100mV for the Opti-mized EP technology with a further reduction of 300mV for theCPT-IGBT.

0

2

4

6

8

10

12

14

16

18

1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2

Vce (V) (100A, 125C)

Eoff(mJ)

(600V,

100A,

125C)

EP SPT-IGBT

Optimized EP

SPT-IGBT

Optimized EP CPT IGBT

A

BC

Fig. 5 Technology Performance Chart for 100A/1200V IGBTs.

0

50

100

150

200

250

300

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Optimized EP CPT B 25C

Optimized EP CPT B 125C

Optimized EP SPT 25C

Optimized EP SPT 125C

Ic(A

)

Vce (V)

Fig. 6 Output characteristics for the 100A/1200V SPT-IGBT (dashed) and newCPT-IGBT (solid) measured at 25 and 125 oC.

This reduction of VCEsa at a rated current of 100 A between theOptimized EP and Optimized CPT technologies is evident from

Fig.6 including the ON-state thermal coefficients of VCEsat.

The turn-off waveforms of the different design versions arealso shown in Fig.7. A higher anode strength is clearly neededto enhance softness of the thinner CPT design as indicated by

the turn-off charts.

Turn-off waveforms (600V, 100A, 125C)

0

20

40

60

80100

120

140

160

Time (100nsec/div)

Ic(A)

0

100

200

300

400500

600

700

800

Vce(V)

Ic

Vce

A

BC

Optimized EP CPT IGBT:

Optimized EP SPT IGBT

Fig. 7: Turn-off softness waveforms under nominal conditions.




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The SOA waveforms at 1000V and 3x nominal current for the

CPT-IGBT design B are shown in Fig.8 under dynamic ava-lanche and Switching-Self-Clamping-Mode SSCM [6]. Themaximal voltage during clamping gives evidence of good ava-

lanche capability of so aggressively thinned device.

Turn off RBSOA waveforms (1000V, 300A, 125C)

0

50

100

150

200

250

300350

Time (100nsec/div)

Ic(A)

0

200

400

600

800

1000

12001400

Vce(V)

Optimized EP CPT-IGBT

Split B

Ic

Vce

Fig. 8: Turn-off waveforms under SOA and switching self-clamp conditions

for the CPT-IGBT.

Finally, Fig.9 presents the nominal turn-on waveforms andFig.10 short circuit performance at 900V for the same CPT-

IGBT split B. The devices show a reasonable controlled behav-iour despite of the thinner silicon design. However, furtheroptimisation will be required in this area.

Turn on waveforms (600V, 100A, 125C)

0

100

200

300

400

500

600

700

Time (100nsec/div)

Vce(V)

0

50

100

150

200

250

300

350

Ic

(A)

Optimized EP CPT-IGBT

Split B

Ic

Vce

Fig. 9: Turn-on waveforms for the CPT-IGBT.

Short Circuit waveforms (900V, 125C)

0

200

400

600

800

1000

1200

Time (2usec/div)

Vce(V)

0

200

400

600

800

1000

1200

Ic(A)

Optimized EP

CPT-IGBT

Split BIc

Vce

Fig. 10: Short Circuit waveforms for the CPT-IGBT.

We have observed that the state-of-the-art SPT-IGBT inherits a

clear trade-off between the short circuit, SSCM and the leakagecurrent. Hence, the optimisation of the CPT-IGBT internalPNP bipolar transistor gain plays the key role in the design

process. Investigations show that high PNP gain designs willalways improve the short circuit and SSCM capability whilehaving the drawback of increased leakage currents especially athigh temperatures, which is very critical for the device block-

ing stability. The CPT-IGBT buffer concept provided a betterdegree of freedom for optimising the device performance spe-cifically with regard to the short circuit ruggedness vs. leakagecurrent trade-off.

IV. CONCLUSIONS

A new IGBT design concept referred to as the Controlled-Punch-Through (CPT) IGBT has been introduced in order tomaximize the effect of using thin wafer technology for the re-

duction of the device overall losses. The device comprises avery shallow N-buffer with an optimized doping distribution tomaintain good blocking, soft turn-off, wide safe operation area,

and very good short circuit capability. With an estimated400mV potential reduction in VCEsat, the new CPT-IGBT offersa very significant advantage over state-of-the-art devices tar-

geting power electronics applications striving on minimisinglosses while maintaining good overall behaviour.

Although presented only for 1200 V IGBT, the concept of theCPT buffer can be employed for any voltage platform with anincreased degree of freedom in the optimization of device pa-

rameters closely related to anode and buffer design properties.

V. ACKNOWLEDGMENT

The initial phase of development was carried out in co-

operation with the Research Centre LC06041 at the CzechTechnical University in Prague supported by the Ministry ofEducation, Youth and Sports of the Czech Republic. Wolfgang

Janisch and Frank Ritchie are acknowledged for advancedprocessing of thin wafers.

REFERENCES

[1] T. Laska et al Short circuit properties of Trench/Field Stop IGBTs design

aspects for a superior robustness, Proc. ISPSD2003, p. 152.[2] M. Rahimo et al Extending the boundary limits of high voltage IGBTs and

diodes to above 8kV, Proc. ISPSD'2002, p. 41.

[3] H K. Nakamura et al Advanced wide cell pitch IGBT having Light Punch

Through (LPT) structures, Proc. ISPSD2002, p. 277.

[4] A. Nakagawa et al MOSFET-mode Ultra Thin Wafer PTIGBTs for SoftSwitching Application Theory and Experiments, Proc. ISPSD2004, p.

103.

[5] M. Rahimo et al "Novel EnhancedPlanar IGBT Technology Rated up to

6.5kV for lower Losses and Higher SOA Capability", Proc. ISPSD2006,

p. 33.

[6] M. Rahimo et al " Switching-Self-Clamping-Mode SSCM, a break-

through in SOA performance for high voltage IGBTs and Diodes ", Proc.

ISPSD2004, p. 437.



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