Explore, Acquire, Analyze, Decide.

MILITARY / AEROSPACE / GOVERNMENT

Deliver Sooner, Better.

System Expertise

Productivity & Technology

Design Flow

Military Communications

ISR, Radar, EW

Avionics, Missile Defense

Intelligence / Cyber Security

Space

Unparalleled Productivity

OpenCL™

Full-Throttle Performance

Best-in-Class IP

FPGA Designers

GPU Programmers

Embedded Developers

AlteraMilitary /Aerospace / Government

Solutions Portfolio

Explore more ideas quickly.

Acquire new concepts easily.

Deliver designs sooner, better. You win.

First Floating-Point FPGA

10+ TFLOPS at 100 GFLOPS/Watt

500 GFLOPS FFT 50 Gsps FFT Generation

Cholesky and QRD Up to 1,000,000 Matrices/Sec

Industry’s Longest Product Life Cycle

OpenCL Conformant

Only On-Shore, High-End FPGA Fabric

Unparalleled Productivity• Hardware in the Loop integrated reference designs• DSP Builder Advanced Blockset is high-level, schematic-entry design: – Constraint-driven design (select fMAX, latency, number of

channels, device family, etc.) – Single datapath logic system clock – Automatic pipelining, register balancing – Fast, automatic timing closure

Best-in-Class IP• Finite impulse response (FIR) filters – Support multichannel, time-division multiplexed (TDM), and

sample rate >> clock rate • Fast Fourier transforms (FFTs) fixed and floating point• Cascaded Integrator Comb (CIC) filters and waveform generating

or mixing blocks• Largest, fastest portfolio of floating-point functions

FPGA Designers

GPU Programmers

Embedded Developers

Full-Throttle Performance• Industry’s first floating-point FPGA• 10 TFLOPS at 100 GFLOPS/Watt • Up to 26 TMACs and 1 GHz fabric• Common environment for system architect and design engineers

OpenCL• Productivity: heterogeneous design platform including FPGA• Performance: optimum throughput and latency for data and

task-parallel algorithms• Efficiency: industry-leading performance per watt

Design-visible COTS boards

HDL automatically optimized

Conformant to Open Systems

C-Tools direct to ARM

Real-time verification with System-in-the-Loop

Military / Aerospace / Government

Avionics, Missile Defense• Support for DO-254 and DO-178C• Package and radiation reliability report• Guidance and control IP with

reference designs

Intelligence / Cyber Security• OpenCL accelerator FPGA cards• High-performance IP for Cyber• Enable software developers to program FPGAs• Open Source Security and extensive ecosystem• Expedite time to mission

Military Communications• 28 Gbps serializer/deserializer (SERDES) transceivers• Densest logic count in small-form-factor (SFF) packages• Cryptographic partner IP cores • Government-approved design methodologies• Assured design for information assurance

Space• Latch-up immunity• Radiation test report and analysis• LEO application-capable• Custom screening and bare die

System Expertise

Productivity & Technology

Design Flow

ISR, Radar, EW• Solution for digitization of phased-array antennas• Fastest digital signal processing (DSP) blocks• Comprehensive floating point and linear algebra library• Modular Open Systems Architecture — commercial

off-the-shelf (COTS) solutions• System Integration Framework for rapid system development

Solutions & Benefits

Integration

Military Security• NIST AES-256 bitstream encryption• NIST HMAC SHA-256 bitstream authentication• Hard configuration error detection and correction• On-chip voltage and temperature sensors• 64 bit unique device ID• Type-I and CSfC compliant solutions• Security Supervisor IP (SSIP)• Robust cryptographic partner IP

Commitment to Defense Industry• Domestic fabrication — 14 nm Intel partnership• Dedicated engineering support• Pin-compatible migration (device migration)

Reliability and Longevity• Industry’s longest product life cycle• Test above industry standard for package quality• Leaded packages• Broad selection of military temperature devices• Latch-up immune

ADC RF Front

EndJESD 204B Tx

DAC JESD 204B Rx

Wideband Converters

ADC RF Front

EndLVDS

DAC LVDS

Data Converters

JESD 204B TxJESD 204B Rx

LVDSLVDS

LogicElements

DSP

Security

AXI4

Avalo

n (ST

, MM,

etc.)ARM

Processor

ARMProcessor

MulticoreDSP

GeneralPurpose

Processor

FPGAor other

Chip

FPGAor other

ChipUser

Memory

Ethernet (GigE, 10GE)

HyperLink

HyperLink

PCIe

Mem

SL III

Auro

raSR

IO G

1, 2Altera FPGA

Network Interface

DDR2/3/4 Memory

Board-levelInterconnect

Packet-switch Interconnect(chip, board, backplane)

Point-to-Point Link Layer(chip, board, backplane)

Baseboard Digital Processing

12000

10000

8000

6000

4000

2000

0

12

10

8

6

4SP TFLOPs

2

065 nm 40 nm 28 nm 14 nm

Altera Product Leadership

Process Node

Multi

plier

s

SP FP Mults

18x18 Mults

Space Time Adaptive Processing (STAP)Angle (degrees)

Norm

alize

d Dop

pler

Freq

uenc

y

Data Snapshot Angle Doppler Response

-80 -60 -40 -20 0 20 40 60 80-0.5

0

0.5

Powe

r (dB

)

-100-80-60-40

Angle (degrees)

Norm

alize

d Dop

pler

Freq

uenc

y

SMI Weights Angle Doppler Response

-80 -60 -40 -20 0 20 40 60 80-0.5

0

0.5

Powe

r (dB

)

-80-60-40-200

Pulse Doppler Processing

Input Signal NInput Signal 2

Target Input Signal

Delay Techniques

Perfect Reconstruction

21 3

Ultra-Wideband Channelizer

0 100 200-50

050-150-100-50

050

Range

Beamformed and Pulse Compressed Output — 3D

Azimuth

Beamformed and Pulse CompressionOutput — Top View

Distance (Range Bin)

Azim

uth

50 100 150 200 250-60-40-20

0204060

-120-100-80-60-40-20020

TargetEmulation TxRx

Time DelayBeamformingRx Noise

Emulation

WaveformGenerator

PulseCompression

FPGA

Matlab API

Digital Beamforming with System-in-the-Loop

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Training: www.altera.com/education/edu-index.html

Purchasing: www.altera.com/buy/buy-index.html

Contact:mil@altera.com

Learn More About Altera Military Solutionshttp://www.altera.com/b/military-design-solutions.html