8/17/2019 Experiment No. 3.2

1/3

2.

above fig

transistor 

edge and

that the st

charge le

rate is not

updated.

Cedge if th

register.

addressed 

data sam

ynamic Tra

 fully dynam

re. This imp

. The hold tifurther input

orage nodes

kage, due to

an issue sin

lock overlape overlap per 

he data mus

 by making s

led by the m

nsmission G

ic positive ed 

lementation

e is approxi

 changes are

i.e., the state

diode leakag

e the registe

is an importaod is large — 

 be stable du

ure that there

ster stage do

te Edge Tri

ge-triggered

f an edge-tri

mately zero,

ignored. On

) has to be re

e as well as s

s are periodi

nt concern f  — obviously a

ing the high-

 is enough d 

es not propa

ggered D-Fl

register base

ggered regist

since the tra

 important c

freshed at pe

ub-threshold

ally clocked 

r this registen undesirabl

high (1-1) o

lay between

ate through

ipflop

d on the mas

er is very eff 

smission gat

nsideration

iodic interva

currents. In

, and the stor 

r. The outputeffect for a

erlap period.

the D input a

to the slave s

ter-slave con

icient as it re

e is turned oor such a dy

ls to prevent

atapath circ

age nodes ar 

Q can chang positive edge

. The 0-0 ove

nd node 2 en

tage.

ept is show

quires only 8

 on the cloc

amic registe

a loss due to

its, the refre

 constantly

e on the falli-triggered

rlap can be

suring that n

 in

r is

h

g

w

CLK 

gnd

      M      0

      M      3

 VDD

CLKBAR 

Data

gnd

M8

 VDD

M10

CLK 

 VDD

      M      1

      M      2

CLKBAR 

gnd

 VDD

M9

M7

gnd

Q

gnd

M12

CLK CLKBAR  

M13

 VDD

gnd

CLK 

val0=1.8val1=0

Data

val0=0val1=1.8

Data

gnd gnd

 VDD

 VDD

CLK 

Schematic Diagram:

8/17/2019 Experiment No. 3.2

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       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

CLK 

       V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1Data

       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.139

0 5n 10n 15n 20n 25n 30n 35n 40n 45n 48nQtime, s A1:(16.15000ns, 900.00000mV); A2:(16.12000ns, 900.00000mV); dif:(30.00000ps, 0.00000V) 

       V

SEL>>

0.4

0.60.8

1

1.2

1.4

1.6

1.8

-0.1CLK 

       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.148

0 5n 10n 15n 20n 25n 30n 35n 40n 45n 48n

Q

time, s A1:(16.15000ns, 900.00000mV); A2:(16.11200ns, 900.00000mV); dif:(38.00000ps, -14.32188fV) 

The D-input edge is skewed relative to the clock signal until the output Q stops following D-input.

For a skew of 30 ps, the incorrect value of input D is sampled and an incorrect value propagates to

the output Q .

For a skew of 38 ps, output Q follows D-input.

∴  =  

8/17/2019 Experiment No. 3.2

3/3

       V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1

CLK 

       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.148

0 5n 10n 15n 20n 25n 30n 35n 40n 45n 48n

Q

time, s

 A1:(16.21889ns, 900.00000mV); A2:(16.15000ns, 900.00000mV); dif:(68.89092ps, 0.00000V)

Date/Time Run: 4/8/2016 10:37:07 AM

SymSpice

       V

SEL>>

0.4

0.6

0.81

1.2

1.4

1.6

1.8

-0.1

CLK 

       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

       V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.148

0 5n 10n 15n 20n 25n 30n 35n 40n 45n 48n

Q

time, s

 A1:(16.21889ns, 900.00000mV); A2:(16.11200ns, 900.00000mV); dif:(106.89092ps, 0.00000V)

Date/Time Run: 4/8/2016 10:37:07 AM

SymSpice

∴ Clock-to-Q delay

  .

∴ Data-to-Q delay

  .