Exercise Solution) 2

Role # ____________________ Section TE-A TE-B TE-C TE-D CE

COMPTER ORGANIZATION AND ARCHITECTURE (All Sections)

MIDTERM 2 (WEDNESDAY, APRIL 25, 2007)

COMPUTER ARITHMATIC, INSTRUCTION SETS, REGISTERS, PIPLINING

SOLUTION

Question 1 (10 points): AllAll of the following questions carry 2 point and no partial credit for these questions. Please provide a single line explanation for you answers even if you have to state the obvious. Otherwise you will get a 0.

i. What is the difference between General Purpose Registers (GPR) and Special Purpose Registers (SPR)? GPR are for general use, user visible and needs to have address bits in the machine code. SPR are special purpose, do not need explicit address bits and may be user visible or not

ii. What is the difference between a floating point number and a fixed point number?A floating number has an exponent part via which it floats whereas Fixed point as the name says is fixed and no exponent

iii. What is difference between a pre-indexing and post-indexing addressing mode?Indexing Indirection VS Indirection Indexing

iv. If a microprocessor does not have an Accumulator register, can it still work?Yes, it can use any of the general purpose registers but will need to use explicit address bits.

v. Why it is better to follow orthogonality principal for an instruction set?That provides completeness via making the whole Op code useable for operation coding

Question 2 (20 points): Computer Arithmetica. Check if overflow occurs after addition of following 2’s compliment signed 16-bit numbers. Perform all the necessary calculations. (7 points)

Principal: if one number is already big enough then any number added with the same sign will cause an overflow e.g. to FFFF add any number (other than 0) and it will cause an overflow.

-12345 and -54321 - Overflow 12345 and 54321 - Overflow

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12345 and -54321 – no Overflow

b. Convert following IEEE 754 double precision numbers to their equivalent decimal value. (7 points) – This is a binary number represented using Hex.

40F0000000000000h = 0100 0000 11110 (13*4 zeros) = 1.0 x 2100 0000 1111 - 1111111111 = 1 x 21000 = 65536 413F424000000000h= 0100 0001 0011 1111 0100 0010 0100 (9*4 zeros) =1. 1111 0100 0010 01 x 210000010011- 1111111111 = 1. 1111 0100 0010 01 x 210100 = (approx) 1.11 x 210100 = (Approx) 1835008

c. Express the following numbers in IEEE 32 bit floating point format. (6 points)

-1/64 = -1 x 2-110 = 1 (11111111-110) 1 (22 zeroes) =1 01111001 00000000000000000000000 -2.625 = 2 + 5/8 = 10 + 101 x 2-11 = 10101 x 2-11 = 1 (11111111-11) 10101 (18 zeroes)= 1 01111100 01010000000000000000000

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Question 3 (20 points): Instruction Sets – Addressing ModesFor the following instructions assuming that 1st operand is destination fill in values in the blank (shaded) cells in the following table.

00004100 = 00005100;00004105 = 0000000A;00004150 = 00000003;00004200= 00000002;00004206= 0000000A;0000420D = 00000006;00005100 = 00000006;0000E100 = 00004100;0000E106= 00004200;R2= 00004105;R3=00000005;PC= 00004000;

Address Instruction Source Addressing Mode

Destination Addressing Mode

Source Effective Address

Destination Effective Address

Contents of Destination

2100 Load R1, 4100 Indirect Register (4100) R1 06

2101 MPY 4150,(E100)R1 Pre-Indexing

Direct (E100 + (R1)) = (E106) = 4200

4150 (4200)*(4150) = 2*3 =6

2102 ADD 200,0001 Immediate Relative to PC

NA 4200 (4200)+0001 = 03

2103 SUB R1( E106), R2 Register Indirect

Post-Indexing 4105 (E106) + (R1) = 4206

(4206) - (4105) = A-A = 0

2104 Pop 300 Stack Relative addressing

SP = FFFFABCD

4300 ( FFFFABCD) = 8

2105 ADD R2,R1(E100) Indexing Register Indirect

E100+(R1) = E106

4105 (4105)+(E106) = A + 4200 = 420A

2106 Push R3(E100) Post Indexing

Stack 4105 FFFFABCD (4105) = A

2107 DIV R2,0002; Immediate Register Indirect

NA (R2) = 4105 (4105)/2 = A/2 = 5

2108 ADD R1, R2(3) Base Register

Register (R2) + 3 = 4108 R1 (R1) + (4105)

SP = FFFFABCD;FFFFABCD = 00000008;

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Question 4 (20 points): Instruction Sets – Instruction Format, Registers

Following table shows machine code for data move and add instructions of a microprocessor, the only user visible SPR (Special Purpose Register) is Program Counter - PC:

No. Instruction mnemonics

Machine code (hex) Meaning

1 MOVE R1,(A10) FF 0 01 A10 R1 (A10)2 MOVE R1,R2,#5 FF 1 01 02 5 R1 ((R2) + 5)3 MOVE R1,R2,#A10 FF 1 01 02 A10 R1 (A10 + (R2))4 MOVE R1,R2 FF 3 01 02 R1 R25 STORE R1, (B10) FE 0 01 B10 R1 (B10)5 ADD R1,#55 AA 2 01 55 R1 R1 + 556 ADD R1,R2 AA 6 01 02 R1 R1+R27 ADD R1,R2,R3 AA 7 01 02 03 R1 R2+R3

Now answers the following:

i. What is the optimal length of for the instructionThis is a fixed length instruction therefore look at the largest instruction from the table. The largest Instruction is 10 Hex numbers (No. 3) = 40 bits.

ii. Does this follow orthogonality? If yes then how many mode bits and for what purpose (coding)Yes, because op codes for all MOVE and ADD are the same. One Hex number is used for the mode but that hex number is from 0-7. Therefore mode bits can be 3 or 4. In case of 3 mode bits the use is for identification of Addressing Modes.

iii. How many GPRs (general purpose registers) does this microprocessor have?The Machine code for any register instruction contains 01 for R1, 02 for R2 and so on therefore either 2 hex numbers are used for a GPR address or one hex. In case of one hex # of GPRS = 28

iv. How many addressing modes are supported?Due to 3 mode bits max Addressing modes supported are 28 (not all the modes are shown in the table above). OR simply count addressing modes in the table.

v. What is the size of directly accessible memory?Max size of instruction = 40 bits; 8 bits are for op code, 3 for mode, 8 bits are needed for a GRPS address bits available for direct addressing = 40 – 8 – 3 - 8 = 21 bits.

vi. How many maximum operations this microprocessor supports?Op code = 8 bits therefore 28 max operations.

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vii. Is this has fixed instruction length or variable?The instruction length is fixed because there are no mode bits to determine a particular length.

viii. In the above table entry 1, can you replace R1 with some SPR to increase directly accessible memory?

Yes, PC (the only SPR available) can be used in the relative mode

ix. What SPRS will you add and why?AC will be a good choice so that more direct bits become available for other addressing modes. IX can also be added to provide help for indexing mode.

x. What is the word size for this microprocessor?Word size = optimal instruction length = 40 bits

Question 5 (20 Points):PipelineThe 6 basic stages for instruction fetch and execute are:Fetch Instruction (FI), Decode Instruction (DI), Calculate Operands (CO), Fetch Operands (FO), Write Operand (WO)TABLE A1: TABLE A2:No. Address Instruction MeaningI1 F000 MOVE R1,(A100) R1 (A100)I2 F001 MOVE R2, (B100) R2 (B100)I3 F002 ADD R3, R1, R2 R3 R1+R2I4 F003 SUB R4,R1,R2 R4 R1-R2I5 F004 DIV R5,R3,R4 R5 R3/R4I6 F005 STORE R5,(B100) R5 (B100)

a. Above table A1 shows 6 instructions and Table A2 shows data values for some locations, please fill the following pipeline table B to execute these instructions. Please watch out for the data dependency and if certain instruction do not need an stage then skip it i.e. if WO stages is not needed then do not use it.

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Address DataA100 5B100 A


TABEL B: (only one instruction can be in one stage at a time)TIME FI DI CO FO EI WO1 I12 I2 I13 I3 I2 I14 I4 I3 I2 I15 I5 I4 I3 I2 I16 I5 I4 I3 I2 I17 I5 I4 I3 I28 I6 I5 I4 I39 I6 I5 I4 I310 I6 I5 I4 I311 I6 I5 I412 I6 I513 I6 I514 I6 I515 I616 I6

Shaded areas are due to data dependencies.

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b. No. Address Instruction Meaning JUMP

RESULTI3 F002 ADD R3, R1, R2 R3 R1+R2I4 F003 SUB R4,R1,R2 R4 R1-R2I5 F004 JZ F002 Jump on Zero NOT TAKENI6 F005 ADD R5,R3,R4I7 F006 JC FF03 Jump on carry TAKENI8 F007 SUB R6,R5,R1I9 F009 JN FF05 Jump on

NegativeTAKEN

I10 F00A MUL R7,R1,R2I11 F00B JO FF07 Jump on

OverflowNOT TAKEN

I12 F00C JUMP F002 PC F002I13 F00D STORE R7,(B100) R5 (B100)

FF03 JUMP F007 PC F007FF05 JUMP F00A PC F00AFF07 JUMP F002 PC F002

Fill the following branch history table for the above code for 2 iterations:No. Address of Branch

InstructionState (2 bit history, use T for taken and NT for not taken)

Target Instruction

Previous branch previous to previous branch

1 F004 (1st iteration) ----------------------- --------------------- I32 F006 NT --------------------- JUMP F0073 FF03 T NT I84 F009 T T JUMP F00A5 FF05 T T I106 F00B T T JUMP F0027 F00C NT T I38 F004 (2nd iteration) NT T I39 F006 NT NT JUMP F00710 FF03 T NT I811 F009 T T JUMP F00A12 FF05 T T I1013 F00B T T JUMP F00214 F00C NT T I3

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Exercise Solution) 2

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