Exam2 Review

Dr. Bernard Chen Ph.D.University of Central Arkansas

Spring 2009

Floating-Point Representation 32-bit floating point format. Leftmost bit = sign bit (0 positive or 1

negative). Exponent in the next 8 bits. Use a biased

representation. Final portion of word (23 bits in this example)

is the significant (sometimes called mantissa).

Example Convert the following number;37.75 into floating point

format to fit in 32 bit register. Convert the number from decimal into binary

100101.11 Normalize all digits including the fraction to

determine the exponent. 1.0010111 x 25

0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0

signsign EXPEXP Significant

Bus Transfer

For register R0 to R3 in a 4 bit system

1 03 2

4*1MUX 3

1 03 2

1 03 2

4*1MUX 0

1 03 2

1 03 2

4*1MUX 1

1 03 2

1 03 2

4*1MUX 2

1 03 2

S1 S0 Register selected 0 0 A 0 1 B 1 0 C 1 1 D

S1S0

4-linecommonbus

Register D Register C Register B Register A

Used for highest bit from each register

Used for lowest bit

Question

For register R0 to R63 in a 16 bit system: What is the MUX size we use? How many MUX we need? How many select bit?

Memory Transfer

The transfer of information from a memory word to the outside environment is called a read operation

The transfer of new information to be stored into the memory is called a write operation

Memory Read and Write

AR: address register DR: data register

Read: DR M[AR]

Write: M[AR] R1

Arithmetic Microoperations

A single circuit does both arithmetic addition and subtraction depending on control signals.

• Arithmetic addition: R3 R1 + R2 (Here + is not

logical OR. It denotes addition)

Arithmetic Microoperations

Arithmetic subtraction: R3 R1 + R2 + 1 where R2 is the 1’s complement of

R2. Adding 1 to the one’s complement

is equivalent to taking the 2’s complement of R2 and adding it to R1.

BINARY ADDER

Binary adder is constructed with full-adder circuits connected in cascade.

BINARY ADDER-SUBTRACTOR

4-bit Binary Incrementer

x

S

y

C

HA

x

S

y

C

HA

x

S

y

C

HA

x

S

y

C

HA

B3 B2 B1 B0 1

Always added to 1

C4 S3 S2 S1 S0

Shift Microoperations

Symbolic designation Description

R ← shl R Shift-left register R R ← shr R Shift-right register R R ← cil R Circular shift-left register R R ← cir R Circular shift-right register R R ← ashl R Arithmetic shift-left R R ← ashr R Arithmetic shift-right R

TABLE 4-7. Shift Microoperations

Logical Shift A logical shift transfers 0 through the

serial input The bit transferred to the end position

through the serial input is assumed to be 0 during a logical shift (Zero inserted)

22

11

RshrR

RshlR

0 0

Circular Shift The circular shift circulates the bits of

the register around the two ends without loss of information

Arithmetic Shift An arithmetic shift shifts a signed

binary number to the left or right An arithmetic shift-left multiplies a

signed binary number by 2 An arithmetic shift-right divides the

number by 2 In arithmetic shifts the sign bit receives a

special treatment

Arithmetic Shift Right Arithmetic right-shift: Rn-1 remains

unchanged; Rn-2 receives Rn-1, Rn-3 receives Rn-2, so on. For a negative number, 1 is shifted from the

sign bit to the right. A negative number is represented by the 2’s complement. The sign bit remained unchanged.

Arithmetic Shift Left

22 RashlR

LSB

Carry outSign bit

Rn-1 Rn-2

Vs=1 : OverflowVs=0 : use sign bit

LSB

0 insert

The operation is same with Logic shift-left

The only difference is you need to check overflow problem

Purpose of Chapter5

In this chapter we introduce a basic computer and show how its operation can be specified with register transfer statements.

Instruction Codes

A process is controlled by a program A program is a set of instructions

that specify the operations, data, and the control sequence

An instruction is stored in binary code that specifies a sequence of microoperations

Instruction codes together with data are stored in memory (Stored Program Concept)

Program statements and computer instructions

Computer instruction

Field specifying the operation to be executed

Field specifying the dataTo be operated on

Instruction code format Instruction code format with two

parts : Op. Code + Address Op. Code : specify 16 possible operations(4

bits) Address : specify the address of an

operand(12 bits) If an operation in an instruction code does

not need an operand from memory, the rest of the bits in the instruction(address field) can be used for other purpose

Op. Code Address

15 12 11 0

instruction

data

15 12 11 0

Not an instruction

Direct address

2. Address is selected in memory and its Data placed on the bus to be loaded into the Data Register to be used for requested instructions

Occurs When the Operand Part Contains the Address of Needed Data.

1. Address part of IR is placed on the bus and loaded back into the AR

Direct address

Indirect address

3. New Address is selected in memory and placed on the bus to be loaded into the DR to use later

2. Address is selected in memory and placed on the bus to be loaded Back into the AR

Occurs When the Operand Contains the Address of the Address of Needed Data.

1. Address part of IR is placed on the bus and loaded back into the AR

Indirect address

Effective address:

• Effective address: Address where an operand is physically located

Effective address: 457 Effective address: 1350

Accumulator(AC) : takes input from ALUThe ALU takes input from DR, AC and INPR : ADD DR to AC, AND DR to AC

Note) Input register is not connected to the bus.The input register is connected only to the ALU

Computer Registers

5-2 Computer Registers Data Register(DR) : hold the operand(Data) read from memory

Accumulator Register(AC) : general purpose processing register

Instruction Register(IR) : hold the instruction read from memory

Temporary Register(TR) : hold a temporary data during processing

Address Register(AR) : hold a memory address, 12 bit width

5-2 Computer Registers Program Counter(PC) :

hold the address of the next instruction to be read from memory after the current instruction is executed

Instruction words are read and executed in sequence unless a branch instruction is encountered

A branch instruction calls for a transfer to a nonconsecutive instruction in the program

The address part of a branch instruction is transferred to PC to become the address of the next instruction

To read instruction, memory read cycle is initiated, and PC is incremented by one(next instruction fetch)

5-2 Computer Registers Input Register(INPR) : receive an

8-bit character from an input device

Output Register(OUTR) : hold an 8-bit character for an output device

Mano's simple Computer: Instructions

000 AND 100 BUN001 ADD (Branch Unconditional)010 LDA 101 BSA

(Load Accumulator) (Branch and Store Address)011 STA 110 ISZ

(Store Accumulator) (Increment and Skip if Zero)

015 12 11

IAny bits other than 0111 and 1111 are called memory reference instructions

3 Instruction Code Formats : Fig. 5-5

Memory-reference instructionOpcode = 000 110

I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx

Register-reference instruction7xxx (7800 ~ 7001) : CLA, CMA,

Input-Output instructionFxxx(F800 ~ F040) : INP, OUT, ION, SKI,

I Opcode Address

15 14 12 11 0I=0 : Direct, I=1 : Indirect

0 1 1 1 Register Operation

15 14 12 11 0

1 1 1 1 I/O Operation

15 14 12 11 0

Hex CodeSymbol I = 0 I = 1 DescriptionAND 0xxx 8xxx And memory word to ACADD 1xxx 9xxx Add memory word to ACLDA 2xxx Axxx Load memory word to ACSTA 3xxx Bxxx Store content of AC in memoryBUN 4xxx Cxxx Branch unconditionallyBSA 5xxx Dxxx Branch and Save return addressISZ 6xxx Exxx Increment and skip if zeroCLA 7800 Clear ACCLE 7400 Clear ECMS 7200 Complement ACCME 7100 Comp le m e nt ECIR 7080 Circulate right AC and ECIL 7040 Circulate left AC and EINC 7020 Increment ACSPA 7010 Skip next instruction if AC positiveSNA 7008 Skip next instruction if AC negativeSZA 7004 Skip next instruction if AC zeroSZE 7002 Skip next instruction if E is 0HLT 7001 Halt computerINP F800 Input character to ACOUT F400 Output character from ACSKI F200 Skip on input flagSKO F100 Skip on output flagION F080 Interrup t O nIOF F040 Inter ru p t O ff

5-3. Computer Instruction

Buss1 s2s0

16-bit common bus

ClockLD

LD

LD

INR

OUTR

IR

INPR

LD INR CLR

LD INR CLR

LD INR CLR

LD INR CLR

WRITEAddress

Adder & Logic

E

DR

PC

AR

CLR

7

1

2

3

4

5

6

Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.

AC

Mano’s Computer Figure 5-4

READ

Memory Unit 4096x16

TR

A 4-bit binary sequence counter (SC) to count from 0 to 15 to achieve time sequencing;> A 4x16 decoder to decode the output of the counter into 16 timing signals, T0, ..., T15

A digital circuit with inputs D0, ..., D7, T0, ..., T15, I, and address bits in IR (11-0) to generate control outputs supplied to control inputs and select signals of registers , bus.

Instruction and Interrupt cycles

Fetch, decodeNext

Instruction

Fetch, decodeNext

Instruction

ExecuteInstruction

ExecuteInstructionSTARTSTART

HALTHALT

Instruction cycle

Interrupt cycle

Interrupt cycle

Interrupt Cycle

Inte

rru

pts

Ena

ble

d

Interrupts Disabled

REGISTER-REFERENCE INSTRUCTIONS• The 12 register-reference instructions are recognized by I = 0 and D7 = 1 (IR(12-14) = 111). Each operation is designated by the presence of 1 in one of the bits in IR(0-11). Therefore D7I`T3 r = 1 is common to all register-transfer instructions.

For example

• B7 = 007 (in hexadecimal)., In binary this is equivalent to: 0000 0000 0111 (CIR)

• B6 = 006 (in hexadecimal)., In binary this is equivalent to: 0000 0000 0110 (CIL)

For example

• B3 = 008 (in hexadecimal)., In binary this is equivalent to: 0000 0000 1000 (Complement E)

• B4 = 010 (Bi=bit in position i =4) in binary is 0000 0001 0000 (skip if positive)

5.6 Memory Reference Instructions• Opcode (000 - 110) or the decoded output Di (i = 0, ..., 6) are used to select one memory-reference operation out of 7.

5.7 IO and Interrupt • Input-Output Configuration :

– Input Register(INPR), Output Register(OUTR)

• These two registers communicate with a communication interface serially and with the AC in parallel

• Each quantity of information has eight bits of an alphanumeric code

IO and Interrupt

• Input Flag(FGI), Output Flag(FGO)

– FGI : set when INPR has information, clear when INPR is empty

– FGO : set when operation is completed, clear when output device is active (for example a printer is in the process of printing)

R

Fetch and decodeinstruction

Executeinstruction

FG I

FG O

IE N

IEN 0 R 0

Store return address in location 0M[ 0] PC

Branch to location 1PC 1

R 1

=0 =1

=0

=0

=0

=1

=1

=1

Instruction cyc le Interrupt cyc le

1:))(('2'

1'

0 RFGOFGIIENTTT

Program Interrupt

• Demonstration of the interrupt cycle : – The memory location at address 0 is the

place for storing the return address– Interrupt Branch to memory location 1– Interrupt cycle IEN=0

256(return address)

0 BUN 1120

Main Program

Interrupt

Service Routine

1 BUN 0

0

PC = 1

255

256

1120

InterruptHere

Save Return Address(PC) at 0

0,0,0,1:

0,][:

,0:

2

1

0

SCRIENPCPCRT

PCTRARMRT

PCTRARRT

Jump to 1(PC=1)

Program Interrupt

Demonstration of the interrupt cycle : The memory location at address 0 is

the place for storing the return address

Interrupt Branch to memory location 1

Interrupt cycle IEN=0

256(return address)

0 BUN 1120

Main Program

Interrupt

Service Routine

1 BUN 0

0

PC = 1

255

256

1120

InterruptHere

Save Return Address(PC) at 0

0,0,0,1:

0,][:

,0:

2

1

0

SCRIENPCPCRT

PCTRARMRT

PCTRARRT

Jump to 1(PC=1)

8-2. General Register Organization

R1

R2

R4

R3

R6

R7

R5

3× 8decoder

MUX MUX

Arithmetic logic unit(ALU)

C lock Input

Load(7 lines)

SELA SELB

A bus B bus

OPR

Output

SELD

(a) Block diagram

(b) C ontrol word

SELA SELDSELB OPR3 533

Bus organization for 7 CPU registers:

2 MUX

BUS A and BUS B

ALU

3 X 8 Decoder

8-2. General Register Organization Bus organization for 7 CPU registers:

2 MUX: select one of 7 register or external data input by SELA and SELB

BUS A and BUS B : form the inputs to a common ALU

ALU : OPR determine the arithmetic or logic microoperation

The result of the microoperation is available for external data output and also goes into the inputs of all registers

3 X 8 Decoder: select the register (by SELD) that receives the information from ALU

Encoding of Register Selection Fields:

»SELA or SELB = 000 (External Input) : MUX selects the external data

»SELD = 000 (None) : no destination register is selected but the contents of the output bus are available in the external output

(Example 2)1. Micro-operationR1 R2 - R3

2. Control wordField: SELA SELB SELD OPRSymbol: R2 R3 R1

SUBControl word: 010 011 001 00101

Example

Hex CodeSymbol I = 0 I = 1 DescriptionAND 0xxx 8xxx And memory word to ACADD 1xxx 9xxx Add memory word to ACLDA 2xxx Axxx Load memory word to ACSTA 3xxx Bxxx Store content of AC in memoryBUN 4xxx Cxxx Branch unconditionallyBSA 5xxx Dxxx Branch and Save return addressISZ 6xxx Exxx Increment and skip if zeroCLA 7800 Clear ACCLE 7400 Clear ECMS 7200 Complement ACCME 7100 Comp le m e nt ECIR 7080 Circulate right AC and ECIL 7040 Circulate left AC and EINC 7020 Increment ACSPA 7010 Skip next instruction if AC positiveSNA 7008 Skip next instruction if AC negativeSZA 7004 Skip next instruction if AC zeroSZE 7002 Skip next instruction if E is 0HLT 7001 Halt computerINP F800 Input character to ACOUT F400 Output character from ACSKI F200 Skip on input flagSKO F100 Skip on output flagION F080 Interrup t O nIOF F040 Inter ru p t O ff

Mano's Computer: RTL

Register Transfer Statement

E AC DR PC AR M[AR] IR

Initial Values

0 2A34 00C7 025 237 0400 0000

Instru 1 0 2A34 00C7 026 200 2A34 3200

Instru 2 0 2A34 2A34 027 200 2A34 0200

Instru 3 0 2A34 2A34 619 619 B200 4619

Instru 4 0 2A34 2A34 620 400 2A34 B200

Instru 5 0 2A34 2A34 621 400 2A34 8200

Instru 6 0 D5CB 2A34 622 200 0400 7200

Instru 7 0 151A 2A34 623 080 Not shown

7080