Evolving quantumcircuits and an FPGA-

based QuantumComputing Emulator

GORAN NEGOVETIC, MAREK PERKOWSKI,MARTIN LUKAC, ANDRZEJ BULLER*

Portland Quantum Logic Group

Department of Electrical and Computer Engineering,Portland State University, Portland, Oregon 97207-0751, 1900 SW Fourth Ave, mperkows@ee.pdx.edu,* Human Information Science Laboratories,Advanced Telecommunications Research InstituteInternational, 2-2-2 Hikaridai, Seika-cho, Soraku-gun, Kyoto 619-0288, Japan, buller@atr.co.jp

1.0 The goal of this researchThe goal of the PQLG group is to develop completemethodologies, software tools and circuits forquantum logic. Our interests are mainly in logicsynthesis for quantum circuits and quantum systemdesign [10]. Emulation of quantum circuits usingstandard reconfigurable FPGA technology andFPGA-based Evolvable Quantum Hardware,proposed here, are research areas not yet dealt withby other research groups. A parallel softwaresimulator was presented in [13].1.1 Quantum Logic and GatesUnlike classical bits that are realized as electricalvoltages or currents present on a wire, quantum logicoperations manipulate qubits [12]. Qubits aremicroscopic entities such as a photon or atomic spin.Boolean quantities of 0 and 1 are represented by apair of distinguishable different states of a qubit.These states can be a photon’s horizontal or verticalpolarization denoted by |1> or |2>, or an elementarypartice’s spin denoted by |#> or |∃> for spin up andspin down, respectively. After encoding thesedistinguishable quantities into Boolean constants, acommon notation for qubit states is |0> and |1>.Qubits exist in a linear superposition of states, andare characterized by a wavefunction ψ. As anexample, it is possible to have light polarizationsother than purely horizontal or vertical, such as slant45° corresponding to the linear superposition ofψ=½[√2|0>+√2|1>]. In general, the notation for thissuperposition is α|0>+β|1>. These intermediatestates cannot be distinguished, rather a measurementwill yield that the qubit is in one of the basis states,|0> or |1>. The probability that a measurement of aqubit yields state |0> is |α|2, and the probability is |β|2

for state |1>. The absolute values are required since,in general, α and β are complex quantities.Pairs of qubits are capable of representing fourdistinct Boolean states, |00>, |01>, |10> and |11>, aswell as all possible superposition of the states. Thisproperty is known as “entanglement”, and may bemathematically described using the Kroneckerproduct operation ⊗ [5]. As an example, considertwo qubits with ψ1=α1|0>+β1|1> andψ2=α2|0>+β2|1>. When the two qubits areconsidered to represent a state, that state ψ12 is thesuperposition of all possible combinations of theoriginal qubit, whereψ12= ψ1⊗ψ2 = α1α2|00> + α1β2|01> + α2β1|10> +β1β2|11>. (1)This property permits qubit states to growdimensionly much faster than classical bits. In aclassical system, N bits represents 2N distinct states,whereas N qubits corresponds to a superposition of2N states.In terms of logic operations, anything that changes avector of qubit states can be considered as anoperator. We can model this phenomena using theanalogy of a “quantum circuit”, where wires do nottransmit signals corresponding to Boolean constants,but transmit pairs of complex values, α and β. Logicgates with this quantum circuit transform thecomplex values on their inputs to new set of valueson their outputs. Quantum logic gates can bemodeled as matrix operations. Typically the notation|0> and |1> are not present in the matrix formulationof the equations, only the probability amplitudes (i.e.α and β) are included; however, there are kept inEquation (2) for illustrative purposes.

| 0 | 0 |1

|1 | 0 |1

a b a b

c d c d

α α ββ α β

> > + > = > > + > (2)

Because the qubit probabilities must be preserved atthe output of the quantum gate, it is noted that allmatrices representing them are unitary, i.e. U*U=I.An important unitary matrix property is that of fullrank. This property implies that quantum gate matrixrows and columns are orthonormal. Therefore, pastresults from spectral methods for classic digital logicare directly applicable to quantum logic synthesis.Furthermore, since quantum logic gates arerepresented by unitary orthonormal matrices, theyrepresent logically reversible gates. Theseobservations mean that the single input/outputquantum logic gates as represented in Equation (2)are rotation matrices characterized by some particularrotation angle θ, where, for example, a=cosθ, b=sinθ,c=-sinθ and d=cosθ. With this viewpoint, it can beseen that there are, in fact, an infinite number ofsingle input/output qubit gates. However, three

elementary gates can be used to generate any rotation[1]. These are the R, S, and T gates described inmatrix notation by

cos sin 1 0 0

sin cos 0 0

j

j j

eR S T

e e

θ

θ θ

θ θθ θ −

= = = − . (3)

A quantum gate that is often mentioned in theliterature is the quantum XOR gate. This gate allowsinputs of |00> and |01> to appear unchanged at theoutputs, but interchanges the pairs |10> and |11>. Forexample, consider the quantum XOR gate’s operationfor an input |10>.

1 0 0 0 0 0

0 1 0 0 1 1

0 0 0 1 1 0

0 0 1 0 0 1

=

(4)

In this example, the input is|10>=(0)|0>+(1)|1>+(1)|0>+(0)|1>, and the inputvector is represented by the coefficients shown inparentheses. It is a significant fact that the unitarygates described by Equations (3) and (4) can realizeany quantum logic function [1] (including standardbinary). There are several strong similarities ofquantum logic and classic digital circuit design usingAND/XOR logic which are used in our research. 2. Standard Hardware Implementation ofQuantum Circuit Models2. 1. Advantages of Modern FPGAs

Since truly quantum computers are for very smallfunctions at present and many research groups cannotafford even those, verification of most of the researchin this area is done now using software-basedquantum circuit simulators. Several such simulatorshave been developed and are available either inpublic domain or commercially. However, because ofmassive parallelism of quantum algorithms, onlysmall circuits can be simulated because of anexcessive time. We believe therefore that it will bebeneficial for the research community to develop afast hardware simulator (emulator) of quantumcircuits. Our approach proposed here uses electricallyreconfigurable Field Programmable Gate Arrays(FPGAs). In our preliminary research we developed asmall FPGA-based quantum hardware simulator. Ourgoal is a further development of simulator technologyand employing it to practical quantum circuits suchas Quantum: Search, Factorization, AssociativeMemories, Spectral Memories and Neural Nets[4,6,7,9,11,14,15,16]. Below we will explain in asimplified way the main ideas of our simulator.

Quantum calculations obey the laws of quantummechanics - quantum computation performsexponential amount of calculation in a polynomialamount of space and time. As observed by Feynman,this is the reason why simulating in current (classical)computer technologies even limited size circuitsrequires exponential amount of memory andprocessing time. Physicists need thus supercomputersto simulate quantum world. However, quantumcircuit operation exhibits a large amount of regularityand micro-scale parallelism, which suggests thatclassical supercomputers may be not the best mediumfor quantum mechanics simulation, which is the sameas the simulation of quantum logic circuits. This ledus to an idea of using FPGA-based hardware forquantum circuit simulation. It is important to realizethat this circuit can be only of a finite size to meet thehardware resources. However, today's FPGA offervery large amount of memory and flip- flops, as wellas hard-wired arithmetic operations such asmultipliers. Below we present work done so far andwe discuss how it can be expanded. One of possibleapproaches is to build a special board with powerfulnew generation Xilinx chips. Other approach is to usethe CBM FPGA-based computer of ATR and adoptthe software developed for it [12].

2.2. Emulating Quantum Circuits in standardbinary hardware

Quantum circuits are composed of quantum logicgates. There exist in theory an infinite number ofelementary quantum gates, many such gates havebeen proposed; however, only a subset of these arerequired to implement an arbitrary size quantumcircuit. Penalty for smaller set of gates is paid with alarger overall circuit.

As presented in previous section, the basic storageunit in a quantum computer is a qubit. A qubit cantake value of zero, one, and a superposition of |0>and |1>. In the superposition state, complexamplitudes are used to represent probabilities of thequbit being in one of states, |0> and |1>. For aregister of N bits, there are superpositions of 2N

states. This is the root of parallelism, since allpossible states are calculated in parallel; this is also afundamental difference of standard and quantumcomputing and is reflected in our simulator design.When the state of a qubit is observed, its probabilitycollapses to either 0 or 1, hence the superposition isdestroyed. This is another quantum peculiarity whichcalls for massive probabilistic circuits in a simulator.Also, since only finite precision can be employed foreither software or hardware quantum circuitsimulation, there is accumulated error that propagatesthrough the system.

Quantum gate operations can be expressed as matrixoperations. Each gate operation is expressed asmultiplying 2N-dimensional vector by the 2N x 2N

transformation matrix. This makes a next requirementfor the simulator – it is a matrix manipulator inhardware. Thus, techniques borrowed from DSP,image processing and other classical areas can beborrowed. Going from M x 2N-dimensional Quantumvectors to one 2M+N vector, we employ the Kroneckerproduct (tensor product) matrix operation. Also, sincein our prototype hardware simulator we will use onlygates that operate on a small number of qubits (N = 1or 2), these matrices are 2x2 or 4x4 matrices,respectively, replicated many times.

To simplify our presentation, most of the followingtext is based on an example. A simple three-gatequantum circuit is presented. Different issues andaspects of the hardware implementation are discussedsubsequently. At the end, algorithms for conversionof quantum netlist to HDL description of hardwarecircuit are briefly outlined and open research anddevelopment issues are presented.

2.3. Example

2.3.1. Basics

Figure 1 below presents a simple quantum circuitwith unitary quantum gates, inverter δx , and

Hadamard H.

In matrix notation,

The whole circuit before the observation gate can berepresented in a matrix transform notation. Thetransform is calculated by Kronecker tensor product.The transform matrix QC is then: QC = δx ⊗ δx ⊗ H,where ⊗ denotes the Kronecker product.

Let

then

How are matrix operations implemented in standardhardware?

This type of matrix operations is done in hardwarevia butterflies. Butterflies are known from DSP andimage processing. However, in contrast, for quantumsimulation, the butterfly structure is always the same,but operations used in the butterflies will differ.Elementary generalized butterfly structure is shownin Figure 2.

2.3.2. Model of Quantum Circuit as a network ofbutterflies

Single δx gate can be implemented as in Figure 3.

A single qubit requires two registers; one to storevalue α for |0> and another to store value β for |1>.Thus, δx requires four registers. It is a permuter. Allquantum circuits that are also circuits of classicalreversible (binary) logic are permuters. Thissimplifies the logic of the simulator. What aboutrealizing in standard binary hardware the quantumcircuit from Figure 4 ?

Fig.1

Fig.2

.

Fig.3

.

Fig.4

This piece of circuit means that there are fourpossible states the circuit can be in (2N, N=2). Unlikebits in normal circuits, qubits are entangled (usingmatrices, this entanglement is achieved by taking theKronecker product). This circuit is implementedusing the δx butterflies, as presented in Figure 5.

Observation: Stages I and II are identical; they justoperate on different numbers of channels (bits orgroups of bits).

The following question arises: Is it possible to make ageneral butterfly, regardless of number of channels?

2.3.3. Generalized butterfly element

Two-by-two δx quantum gate is described as follows.For any input vector [A, B]T (where T is the matrixtranspose), the output vector is [B, A]T. By analogy,N-by-N δx quantum gate is described; for inputvector [(a1, a2,…, aN), (b1, b2,…, bN)]T, the outputvector is [(b1, b2,…, bN), (a1, a2,…, aN)]T, where ‘N’is the number of channels of the δx gate. This gatecan look as follows, Figure 6:

The two-gate circuit can be build using only thesetypes of δx gate. On the first level, though, only twochannels are needed, and N-2 channels are wasted(where N is total number of channels). Directhardware implementation would be very inefficient,wasting many registers (in the case of δx gate onlyregisters, but in others, like Hadamard, multipliersand adders as well). However, consider the wholeFPGA quantum simulator design flow: after thequantum netlist is transformed (synthesized) to theregular circuit design (HDL file), the subsequentsteps are exactly the same as for any other circuit:logic synthesis, technology mapping, place and route,and target device programming. It is possible toremove unutilized resources (unused channels of theδx gate) in the next processing stages.

2.3.4. HDL Experiment

The following HDL Verilog file, Figure 7, is tested.The source represents a 2-channel δx gate. The first

module is the gate itself, and the second modulecontains the gate module instantiation. Because onechannel is unused, two inputs are replaced with“8’hx” which in Verilog means 8-bit wide wire withconstant value of “unknown”. The two outputs are 8-bit wires “tmp”. These wires do not appear in themodule input-output list (next to keyword “module”).The project is synthesized, and the log file is created.Synthesis tool used by us in our preliminary researchwas Synplify by Simplicity, (for the lack of spaces,several details will be not presented). On this logfile, the two warnings appear in bold type. Synthesistool realized the unused combinatorial logic (registersin this case) and removed it from the implementation.This is an important result. Even if the source code isvery resource inefficient, if parts of codes areinstantiated properly (with knowing what the toolwill do), the tool will remove unused parts of thedesign leading to an efficient implementation.

Fig.6.

Fig.7

Fig.8

Fig.5

The following figures, Figure 8, Figure 9, showparts of the hardware implementation of the HDLsource.

Next, the example circuit will be implementhese findings in mind.

2.3.5 Example circuit implementation

The example circuit consists of two inverters (δx gates) and one Hadamard gate4). Direct matrix multiplication looks as follo

In general, a, b,…,h are complex numbeschematics of the hardware circuit is shown i10. Aside from needing gates of sufficient nuinputs and outputs, it is also required to mixbetween the gates. This mixing is always ordexample bit reversal or logic shift of bits. Bitis already used for many algorithms, like FasTransform. On the other hand, can simplified? Using the knowledge about unusremoval, consider the two-gate circuit seen bis implemented in hardware and presented asimilarly as in Figure 13. Even though thlooks wasteful on the schematics, its hrealization is efficient. This is the main prinwill use for the FPGA based quantumsimulation.

2.3.6. Observation Gate

In the quantum circuit, states of the bits aresuperposed. This means that the circuit is in manystates at the same time. However, once the circuitstate is observed, the uncertainty is destroyed, and allbits collapse to the familiar ‘0’ and ‘1’ state (this andother quantum circuit properties are coming from therules of quantum physics). In the simulation circuit,

Fig.9

ted with

quantum (Figurews:

rs. Then Figurember of the bitsered, for shiftingt Fourierthis beed logicefore. Its a file,

e circuitardwareciple we circuit

there must be a gate to simulate this behavior: fromall superimposed circuit states, only one will be validafter this gate; the state is chosen based onprobabilities. Output state is then: |α1> A1 + |α2>A2 + … + |α2

n>A2 n, where A1, A2, … are n-bit

binary states, α1, α2, … are square roots ofprobabilities of the output being in that state, andfrom probability theory, magnitude of probability isequal to one.

In order to build a hardware circuit to simulate the“observe” gate, a random number generator isneeded. A circuit often used for pseudo-randomnumber generation in hardware is LFSR (LinearFeedback Shift Register) circuit. We can use LFSRtheory and tables to calculate such circuits veryefficiently and insert their generators to our CADsoftware package for designing automatically thereconfigurable quantum simulators (for lack of spacethis topic is not presented).

How to set bits based on probabilities? LFSRprovides ½ probability. If two LFSR areuncorrelated, ANDing them will give ¼ probability.Hence, logic AND multiples probabilities: A ⊗ B =A * B (where ⊕ is logic AND, and * arithmeticoperator). Similarly, logic OR and XOR operatorsgive following probabilistic (arithmetic) operations:A ‘+’ B = A + B – A*B (logic OR), and A ⊕ B = A+ B – 2*A*B (logic XOR). Using these operators onthe probabilities available, all probabilities can bederived. However, this approach is not feasible toimplement for large number of probabilities. Largerset of probabilities can be achieved either by someother hardware method, or offline, in software.

One way to implement the quantum observation gatewould be by using RAM memory and LFSR’s. ForN Q-bits, there are 2N possible quantum states theobserved quantum wires (registers) could be in at atime. If there is a RAM memory with 2N locations, Naddress lines are needed to encode all memorylocations. Filling the RAM with appropriate values,randomly generated address would choose the outputvalue of the observation gate. For instance, outexample circuit has 3 input/outputs. There 23 = 8possible output states (000, 001, 010… 111), eachassociated with a certain probability (based on input

values and circuit content). Lets say our input was[010]. In vector notation, input vector is [00100000];this can be interpreted as probability of zero for[000], zero for [001], one for [010], zero for [011],etc.

Matlab function represents the example quantumcircuit in matrix notation

function OutVector = qcir(InVector) %Gate definitionsr = 1/sqrt(2);

H = [r -r; r r]; inv = [0 1;1 0];[sizeX, sizeY] = size(InVector); if(([sizeX, sizeY] == [1 8]) ~= [0 1]), error('Invalid Input Vector Size!'); end%Circuit definitionsTransform = kron(H, kron(inv, inv));OutVector = (Transform * InVector').^2;% expressed as probabilityRunning the function with the input vector, we getoutput vector: [0, 0.5, 0, 0, 0, 0.5, 0, 0] – expressed inprobability. It means that output [001] and [101] bothoccur with ½ probability (50% of time).

How to implement this in hardware? RAM with 8 addresses (to account for estate). It has to be filled with states accoprobability. Figure 11. (Note: ordering ocontent is not important, since it is chosenAddress is randomly generated (wprobability of all states). For this case, thneeded to encode 8 addresses; so three LFare needed (these should be uncorrelated)content is based on the inputs, so it hasdynamically (meaning, it cannot be preHowever, the structure of the RAM preserved regardless on the inputs. For ethe circuit examined, all possible inputsonly two possible outputs with ½ probaThis observation can lead to somewhardware implementation – Fig. 12.

2

Fig.10

We need aach possiblerding to thef the RAM randomly.)ith equalree bits areSR outputs. The RAM

to be filled-compiled).content is

xample, for would givebility each.

hat simpler

There are many formats for net-list

Most often, a netlist first defines all the design, naming them with undesignators, and than lists all nets wnames and lists of component and pin

Fig.1

3

Fig 1

representation.

Figure 11

components inique referenceith their unique names they go

to. For a quantum circuit, in addition to this, therecan be a time slice where a gate or sub-circuitbelongs. This is true because in a quantum circuitoperation on qubits are done in parallel, such that inone time slice the qubits are updated even if aparticular qubit does not go trough a gate. The reasonfor this is that qubits have values of probabilities ofbeing a particular state, so changing a probability ofone qubit, affects probabilities of other qubit states(due to probability theory).

There are many technical question that we skip here;quantum circuit netlist representation, quantumnetlist to Verilog conversion, and others. Wedeveloped CAD tools for them which will be furtherextended and improved, possibly using the CBMtools developed in ATR Japan [2]. The technicalquestions solved and to be solved are similar as instandard CAD tools for translation from high levellanguages (Verilog, VHDL and higher) to logicdescriptions, using libraries and optimizing designson logic and register-transfer levels. Verilog sourcecreated with our current (not totally optimized)algorithm is shown in Figure 13. Concluding, we cantell that our tool is a dynamic preprocessor to convertquantum netlist to a standard Verilog FPGA-baseddesign system.

3. Extrinsic and Intrinsic Evolvable QuantumHardware (EQHW)

There are different views on what is evolvablehardware (EHW). For instance, A. Hirst definesEHW as “applications of evolutionary techniques tocircuit synthesis." This is a very broad definition thatincludes any evolutionary software applied to anykind of synthesis or optimization in circuit design.Using this definition in quantum domain we obtainthe following definition “Evolvable QuantumHardware (EQHW) is application of evolutionarytechniques to quantum circuit synthesis”. Exampleof such an approach realized in software (extrinsicapproach) is presented in Ref. [10]. T. Higuchi et aldefine EHW as “hardware that is capable of on-lineadaptation through reconfiguring its architecturedynamically and autonomously”. In quantum domainthis definition would correspond to any kind oflearning and adapting quantum circuits[4,7,9,11,14,16], but evolutionary algorithms wouldbe not required. Finally, Hugo De Garis definesEHW as “a Genetic Algorithm realized inhardware”. This narrowest definition is calledIntrinsic Evolvable Hardware, in contrast to extrinsicEHW in which the entire learning is performed insoftware. Following this definition, “EvolvableQuantum Hardware is a Genetic Algorithm realizedin quantum hardware.”

Observe first, that with present technology EvolvableQuantum Hardware is still a speculation sinceprogrammable quantum hardware is available. It ispossible, however, to develop evolvable technologyfor FPGA models of quantum circuits, as presentedin the previous sections. Using this understanding,the combination of our evolutionary software fordesigning automatically quantum circuit netlists [10]and the presented above method of building FPGAaccelerators for quantum netlists, leads to therealization of a complete quantum-system-modeled-in-a-binary-system evolvable hardware, based on theavailable standard FPGA technology. In thisproposed by us approach, the GA-based softwareprogram will generate a new netlist satisfyingproblem constraints. Next this netlist is translated toVerilog as above, and finally Verilog-based CADtools are used for mapping to FPGA hardware. Thedifference between extrinsic and intrinsic hardware iswhether the fitness function is calculated in softwareor in hardware. If calculated in software, then theapproach would be extrinsic. If calculated inhardware and the process of GA-based net-listgeneration is repeated for populations, this would bean example of software-hardware extrinsic-intrinsicapproach to quantum evolvable hardware. Anotherapproach would be to realize the QC-generating GAentirely in hardware, where it would directlyconfigure RAM bits that program logic andconnections of the model. This works well withreconfigurable hardware such as FPGAs from Xilinx"http://www.xilinx.com/". One argument for thedirect approach is to exploit emulator hardwareresources for unconstrained hardware evolution. Suchwork is as an attempt towards adaptive hardware, notnecessarily following the human-provided circuitdescription (like unitary matrix of a truth table) as adesign specification for GA [10]. The differencewould be here the same as between the binary logicfunction synthesis and data mining. In logicsynthesis the truth table must be strictly followed anda solution candidate with even one minterm notverified in fitness function is bad. In contrast, in datamining the fitness function attempts to satisfypredominantly the Occam’s Razor and to minimizethe learning error so that solution that differ from thespecification are acceptable. Such adaptive quantumlearning will explore larger design spaces and thusmay be able to discover novel designs for whichunitary matrices are even not known but some otherconstraints are given. It will not assume a prioriknowledge and thus can be applied to variousdomains and obtain feedback from the environmentrather than from the human designer. By notrequiring exact problem specifications complexsystems can be possibly designed, which cannot be

handled by conventional specification-basedevolutionary and non-evolutionary (such asbacktracking or A* search [17,18]) designapproaches to quantum circuit synthesis.

4. Conclusions and future work

We presented two new ideas: (1) design of an FPGA-based hardware accelerator for quantum computing,(2) design of an FPGA-based hardware evolver ofquantum computers. These approaches can worktogether. We did not discuss the sizes of quantumcircuits that can be simulated, because the reportedwork was for single Xilinx chip only. In future, wewill design the board with many chips and this boardwill be linked to a PC development workstation. Theproblem of building the board with chips, selection ofbest chips, how many boards - are all technicalquestions that will be addressed in future research. Itis possible that after more detailed analysis we willcome to the conclusion that instead of building theentire simulator from scratch we should purchase oneof existing FPGA-based programmable emulatorsand only develop a new software for it, or that weshould use CBM.

Although quantum computers are still in earlyresearch phase, the quantum accelerator and thequantum evolver, when build, can be directly usedfor practical tasks; such as simulation of quantumsearch, cryptography or robot control. They can bealso used in research on quantum computing and forsimulation of tough problems in quantum mechanics.

Acknowledgment. We appreciate help of MitchThornton, Jerry Bruce, Jong-Hwan Kim, IgorMarkov, Alan Mishchenko, George Lendaris, andMikhail Pivtoraiko.

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