Evolution of the Smart Power and High Voltage Technologies ... · PDF fileEvolution of the...

Evolution of the Smart Power and High Voltage

Technologies, Design and Simulations

Giulio Ricotti

Design Director and Technical Fellow

Technology R&D – Smart Power and High Voltage Technology

STMicroelectronics – Cornaredo – ITALY

Agenda

Smart Power & High Voltage Technology overview

Application example of HV Design:

µMirrors HV driver

Echography

Industry Challenge and Requests for Simulation and Verification

May 9th 2016SIP 2016 - Turin

2

Agenda



µMirrors HV driver

Echography



3

Microelectronics Scenario

SIP 2016 - Turin May 9th 2016

4

1

BCD Smart Power

A concept invented by ST in the mid-80s [1][2][3] widely used today in the industry

[1] Single Chip Carries Three technologies, Electronics Week, December 10, 1984

[2] C. Cini, C. Contiero, C. Diazzi, P. Galbiati, D. Rossi, "A New Bipolar, CMOS, DMOS Mixed Technology for Intelligent

Power Applications", ESSDERC '85 Proceedings, Aachen (Germany), September 1985

[3] A. Andreini, C. Contiero, P. Galbiati, "A New Integrated Silicon Gate Technology Combining Bipolar Linear, CMOS

Logic and DMOS Power Parts", IEEE Transactions on Electron Devices, Vol. ED-33 No.12, December 1986


5

“More than Moore” BCD diversificationroadmap splitting in three main DIRECTIONS(*)

BCD1

250VBCD2

100/120V

BCD2

170V

BCD2

20/60/80V

BCD5/5s

16/20/45/70V

BCD6/6s

20/45/70/100V

BCD3s

16/40/60/80V

BCDSOI

100/170/200V

ND20

BCD1

100V

BCD1

60V

BCD4

40V/65/80V

BCD4s

40/65/80/90V

BCD-Offline

700V

BCD2s/2As

20/30/45V

BCD3

16/40/60/80/90V

CD20II

CDx40VBCD6s-Offline

800VBCD6s_SOI

100/190VBCD8s-SOI

300V

HVG8BCD8/8s

8/20/40/70VBCD8sP

8/18/25/42V

Time Line 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2003 2004 2006 2008 2010 2012 20141984

4.0µm VDMOS

2.5µm JI - Locos - 2M

2.0µm JI - Locos - 2M

1.2µm 5V CMOS - Locos - 3M

1.0µm 5V CMOS - JI/SOI - Locos - 3M

0.8/0.72µm 5V CMOS - Locos - 3M

0.6/0.57µm 5V CMOS + E/E2PROM - Locos - 3M

0.35/0.32µm 3.3V CMOS + OTP/FTP – R.Locos - JI/SOI - 4M (Thick Cu)

0.18/0.16µm 1.8/3.3V CMOS + OTP/FTP - STI&DTI - JI/SOI - 4M (Thick Cu)

0.16-0.11µm 1.8V CMOS + OTP/FTP - STI&DTI - 4M (Thin & Thick Cu)

0.090 1.2V CMOS + OTP/FTP - STI&DTI - 5/7M (Thin & Thick Cu) BCD-10

BCD9s

20/40/65V


6

Example of BCD product:

Analog + Digital + NVM + Power & HV on one chip

High Voltage & Power section

(DMOS) to drive external loads

Memory: RAM

NVM: ePCM (embedded

Phase Change Memory)

Analog blocks

to interface the external world

to the digital systems


Digital core (CMOS)

for signal processing

7

8X40V Nch DMOS

32KB

ePCM

8KB RAMANALOG

BCD Technology Platform by Segment

Technology Platform Application Fields

BCD6s Offline - 0.32µm – 800V

HV Transformer – Galvanic

Isolation 5KV

BCD8s SOI - 0.16µm

1.8 V CMOS - 70V/100V/140V/200V

BCD8sP - 0.16µm

1.8 V CMOS -8V/18V/27V/42V/60V

BCD8sAUTO DTI - 0.16µm

3.3V CMOS, 40V/65V/100V

BCD9s - 0.11µm – Full Cu BE

1.8V CMOS 8V/40V/60V

BCD9sL-0.11µm – Full Cu BE

3.3V CMOS, 40V/65V/100V

BCD10 – 90nm –

8V to 65V

BCD 65nm

8V to 40V

HVG8A - 0.18µm

16V CMOS

Off

-Lin

e

BC

D

SO

I

BC

D

Ad

va

nc

ed

BC

D

Hig

h

Vo

lta

ge

CM

OS

Lighting Motors Electrical Car

AMOLED Power Supply

Automotive

Sensor IC

Ecography

Full digital amplifier

HDD

Printers

Power

Line

modems

GDI

Audio amplifier

ESP

Body

Airbag

ABS Power Supply

Bio Medical TSH7x

+

_

0V

Vcc

Advanced Analog


8

ISOLATION & INTEGRATION

SCHEME

• Junction Isolation

• DTI (Deep Trench Isolation)

• SOILARGE CURRENT ROUTING

• Thick Cu Metallization

POWER DEVICES

POOR GAIN from

GEOMETRY SCALING

Innovative Architectures

to optimize performance

Thick Copper

LOGIC CORES

• Integration challenge

for std CMOS

• NVM memories without extra masks

ANALOG FEATURES

• Optimize Analog performances &

enrich basic devices offer (bipolar,

passive devices)

Challenges in Smart Power Technologies


9

Substrate active parasitic

P Substrate

nPocket

Capacitor, Diffused Resistor,

npn Collector, nMOS Drain…

P Substrate

nPocket

Capacitor, Diffused Resistor,

npn Collector, nMOS Drain…


10

CMOS components are self shielded


11

Isolation & Integration Schemes

DEEP

TRENCH

ISOLATION

(DTI)

SiO

2

P/P+

N

JUNCTION

ISOLATION

(JI)

N

P or P/P+

DSG

N-LDMOS

DIELECTRIC

ISOLATION

(SOI)SiO2

N

N or P

SiO

2


12

Thick Cu Metallization schemes

for Large Current, High Power, Robust Bonding over Active Areas

• Thick Cu Metallizationfor High Current / High Power

• Ni/Pd Pad Finishing for

• Robust Bonding over Active Areas

• Extended Temperature (>>150C) Reliability

Cu

NiPd

• Cu-RDL:

• higher thickness

• larger Cu-wire diameter on active Areas

Cu-Damascene + Al-cap

METAL3

Al-cap

(Pad finishing)

Al

Au

WIRE

Cu

METAL3

Cu

WIRE

Cu-Damascene + Ni/Pd

Ni/Pd

(Pad finishing)

Cu

PdNi

Cu-RDL (Cu + Ni/Pd)

Ni/Pd

(Metal Interconnect finishing)

Cu Cu

PdNi

Cu

WIRE

Cu

Ni/Pd

• Cu-Damascene:

• finer line pitches


13

EMC/EMITemperature

Range

Design Challenges from Specific Application: Automotive

Reliability

14


14

Design Challenges from Specific Application: Automotive

Cluster / Body

Engine Mngt

Car Radio

Entertainment

Suspensions - ABS

(safety in general)

Airbag

Transmission - Gear

15


15

Other quick examples to complete

the technology overview …


16

Enrichment of Device offer:Example: Integrated HV Coreless Transformer for Galvanic Isolation

Galvanic Isolation: Separated functional sections No electrical current flow

Inductive Signal Transmission: signal sent through a coreless transformer

Isolation is obtained with dielectric between primary and secondary coils

Gate driver: 1500V operative

4kV/6kV galvanic isolation capability

BCD Driver die BCD Receiver die

TX RXSignal

ISOLATION

Transmitter IC Receiver IC

SIP 2016 - Turin

Cu

W

M2M1

Dielectric

PassivationAl cap

Cu

Oxide thickness

> 10µm Co

rele

ss

Tra

nsfo

rmer

Mo

du

le

BC

Dx

SECONDARY COIL

PRIMARY COIL

Primary coil

Receiver ICTransmitter IC

Secondary coilDielectric

May 9th 2016

17

Enrichment of Device offer:Example: Integrated Magnetic Material

• Current Hall Sensor with Fully integrated (sputtered) Magnetic Concentrator

Advantages: low thickness and profile, optimized shape, alignment control

Nitride

Oxide

Co-rich film

ControlCircuit

IntegratedMagnetic

Concentrator


18

Ink Jet Cartridge


19

Lab on Chip


20

MEMS examples


22

Agenda



µMirrors HV driver

Echography



23

picoPROJECTOR HV Driver


24

SOI-BCD8s MEMS uMirror driver

• Main Application: Perceptual

computing (Computer)

• HV Mirror Driver IC as companion

chip for MEMS product


25

Exploring the IVCAM System


27

BCD-OFFLINE Application Example - Lighting

High Voltage

Gate Driver

Application examples:• High Voltage Smart Gate drivers

• Power supply: Combo PFC & Resonant Controller

• Lighting: Fluorescent & LED driver

• Automotive: Battery management for Hybrid / Electrical vehicles


28

Toward High Density even in HV Drivers

-50%

SOI-BCD200 (1.0µm)

PLASMA

MONITOR

MODULEData Drivers

Scan

Drivers

Susta

in

Am

plif

ier

High Voltage

Power Supply

Video

Processing

Control &

Power

Electronics

Video Input

(24 bits)

Sync

Main

PDP

NTSC 16:9

JI Process


29

http://images.google.com/imgres?imgurl=www.iwantaplasmatv.com/pt-50phd4-p.jpg&imgrefurl=http://www.iwantaplasmatv.com/&h=276&w=350&sz=21&tbnid=uKqdwLYc_jgJ:&tbnh=91&tbnw=115&prev=/images?q=plasma+tv&start=40&svnum=10&hl=en&lr=&ie=UTF-8&oe=UTF-8&sa=N

http://images.google.com/imgres?imgurl=www.iwantaplasmatv.com/pt-50phd4-p.jpg&imgrefurl=http://www.iwantaplasmatv.com/&h=276&w=350&sz=21&tbnid=uKqdwLYc_jgJ:&tbnh=91&tbnw=115&prev=/images?q=plasma+tv&start=40&svnum=10&hl=en&lr=&ie=UTF-8&oe=UTF-8&sa=N

From 2D to 4D Ecography systems

For the image of a 2-dimensions section just a few channels

(pixel) are enough (64 to 128). The electronic circuitry is in the

console machine implemented by discrete components. In the

cable there are tens of coaxial wires. To explore a volume the

doctor has to move the probe, but the “machine” doesn’t know

the beam direction

This is a real 3D image exploring a solid

angle or a volume: the “machine” knows

the direction of the echo and can

reconstruct a vectorial coordinate

description of the observed objects. The

channels are organized in a matrix of

thousand transducers. The electronic

circuitry is now inside the probe and

dedicated asics are needed.

Ultra Ultra low power HV-HF design

technique is mandatory.


31

From actual Ultrasound images to new concept


32

Concept of TX and RX Beam Forming


35

Echography Product characteristics

May 9th 2016

• Continuous Sales Grow

• Long life production (8-12 Years)

• High End Analog with great added value

• Market with very high barrier to enter

(similar to Automotive) Once inside get stability

• Enabling Know How to enter in consumer application

SIP 2016 - Turin

38

Agenda



µMirrors HV driver

Echography



39

Two Different Kinds of Needs

• Tool very effective with standard CMOS

• Some extra effort needed to have equivalent advantages in Smart Power Technologies

Smart Power extra needs for standard tools

• For the technology

• For the applications

• Several “niches” for new tools

• Today homemade by IDM or done by small startup

Smart Power specific needs

40


40

Sample schematic

You design

this amplifier

and think it’s

quite simple,

robust and

predictable

by simulation


41

Sample schematic and parasitic components

This is what

you get from

silicon, some

effects are

included in

device

models, but

many are not!

subα*Ipwr

IpwrMay 9th 2016SIP 2016 - Turin

42

BCD extra effort needed

Extra Needs for Standard Tools


43


Spice, Fast Spice:

precision, speed and reliability



44


Spice, Fast Spice:


Voltage Dependent

Rules:

i.e. DRC, ERC, Router



45


Spice, Fast Spice:


Voltage Dependent

Rules:

i.e. DRC, ERC, Router

Digital Flow:

AoT, Router with few metal

levels and DFM, aspect

ratio



46

Smart Power Specific

Specific Needs


47


Substrate Tools

Specific Needs


48


Substrate Tools

Power Device Design

and verification

Specific Needs


49


Substrate Tools

Power Device Design

and verification

Circuital Electro-Thermal analysis

Specific Needs


50


Substrate Tools

Power Device Design

and verification

Circuital Electro-Thermal analysis

45 degrees

Routing for thick copper

Specific Needs

Ni/Pd

(Metal Interconnect

finishing)

CuCu

Cu

WIRE


51

Silicon substrate simulations industry needs

• To compute the effect of

minority carrier inside the

silicon substrate

• To verify voltage potential raise

of p-substrate after current

recirculation phenomena

• Estimation of lateral NPN BJT

parasitic devices between

multiple n-well sockets

• Criteria for avoiding of latch-up

phenomena in layered devices

• EMC/EMI immunity

computation of device


52Original Layout View Abstract View

Test Chip for thermal analysis


53

• Capability to estimate in each design phase from early

floorplan.

• Self-heating of single MOS device and mutual heating between

aggressor and victims

• Electrical SPICE compact model with embedded thermal node

• Both thermal and electro-thermal simulation for energy

capability device dimensioning

• Computation of electro and electro-mechanical stress on

metals and other back-end material for avoiding reliability

issues

• Needs of system thermal simulation involving silicon, package

and environment (i.e Engine Control Unit) to verify the full

scenario dynamic working temperature

Resistance Analysis

BCD chip Resistive map of GNDA net

Most critical resistive

parts of GNDA net

Resistive analysis can be used as DRC / LVS

Design

LVS - Parasitic

EXtraction

Resistance

Analysis

Post-layout

simulation

IRdrop/EM

analysis

Electro Migration & IR drop


54

IR Drop Analysis

• IR-drop analysis is the voltage drop across nets modeled

by parasitic elements

Voltage drop on OUTM and OUTP

50mV limit in

voltage drop map Design

LVS - Parasitic

EXtraction

Resistance

Analysis

Post-layout

simulation

IRdrop/EM

analysis

BCD chip


55

Electro Migration & IR drop

Electro-Migration Analysis

• Electro-migration analysis:

• AVG/RMS/Peak/Self-heating checks performed at the same time

EM analysis on OUTP

Detail of

EM violation map Design

LVS - Parasitic

EXtraction

Resistance

Analysis

Post-layout

simulation

IRdrop/EM

analysis

BCD chip


56

Electrical Rules Checks

• Basic Device classification

• elements always conducting (R/L)

• elements never conducting (C/Q/D/HDL-A)

• conditional rules (MOS)

• Voltage Propagation

• Pattern Matching (logic, level shifter, analog, …)

• Rules (SOA, el-violations, good practices)

• Programmability

5.0 analog

1.8 digital

5.0 digital 5.0 analog

1.8 digital

5.0 digital

ERC


57

• ISO 26262 – Road Vehicles – Functional Safety Standard

• Typical design composition for Analog Diagnostic Coverage

• Function Block

• Diagnostic Block

• Diagnostic Coverage

Analog Fault Injection

𝐷𝑖𝑎𝑔𝑛𝑜𝑠𝑡𝑖𝑐 𝐵𝑙𝑜𝑐𝑓()


58

Conclusions

• Importance of “More than Moore”

• BCD Technology • Products still present in all ST business segments

• BCD peculiarities and challenges• Technology

• Design

• Applications

• EDA space for improvement opportunities

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