Eval Programmation Complete
-
Upload
salah-dahouathi -
Category
Documents
-
view
225 -
download
0
Transcript of Eval Programmation Complete
-
8/13/2019 Eval Programmation Complete
1/47
Evaluation programmation
Partie 1 : questionnement crit (9 pages)
Partie 2 : questionnement TP (10 pages)
Partie 3 : document ressource (4 pages)
Partie 4 : extrait documentationconstructeur PIC16F877
-
8/13/2019 Eval Programmation Complete
2/47
Evaluation programmation
Partie 1
Questionnement crit
-
8/13/2019 Eval Programmation Complete
3/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
I Analyse de la version en langage assembleur
I.1 Sous programme INIT
Question1A partir du schma structurel du PIC16F877, indiquerdans le tableau du document
rponse 1, les configurations des diffrents ports dentres/sorties.Indiquergalement quel est le signal affect chacune des broches.
Question2Par dfaut et dune manire gnrale, comment sont configures les broches
dentres/sorties du PIC16F877 ?
Configuration du PORTD :
Question3
Ecrireles instructions assembleurs permettant daccder la banque0. Justifiervotrerponse.
Complteralors la partie intitule slection de la banque 0 par dfaut dudocument rponse 2.
Question4Quel est le nom du registre de configuration du PORTD ?
Quelle doit tre la valeur stocke dans ce registre pour configurer correctement le
PORTD. Justifiervotre rponse.
Question5Ecrireles instructions assembleurs permettant de configurer le PORTD correctement.Complteralors la partie intitule Configuration du PORTD du document
rponse 2.
Question6En considrant les signaux affects aux broches du PORTD, indiquerquels devront
tre leurs tats logiques lorsque le systme est mis sous tension. Justifiervotre rponse.Ecrireles instructions assembleurs permettant dinitialiser correctement ces broches.Complterla partie intitule Configuration du PORTD du document rponse2.
Configuration du PORTA et du PORTD :
La particularit de ces entres est quelles peuvent tre configures soit enanalogique soit en numrique.
Question7Dans le cas de notre systme technique, doit on utiliser ces broches en numriques ou
en analogiques. Justifiervotre rponse.
Question8Daprs la documentation constructeur, quel est le registre permettant de configurer
lutilisation des entres en analogique ou en numrique.
Dans quelle banque se trouve ce registre ?
-
8/13/2019 Eval Programmation Complete
4/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
Question9En supposant que le bit ADFM=1, indiquerquelle devra tre la valeur de ce registre.
Justifiervotre rponse.
Question10Ecrireles instructions assembleurs permettant de configurer correctement le PORTA
et le PORTE.Complterla partie intitule configuration du PORTA et du PORTE du
document rponse 2.
I.2 Programme principal
On souhaite crire en langage assembleur, le programme correspondant
lalgorigramme du programme principal (voir document ressource).
On utilisera les dclarations du fichier Decla.h pour une lisibilit du programme.
Test FC_AV=0 :Dans le fichier de dclarations on a la ligne suivante :
#DEFINE FC_AV PORTE,1
Test VAR_GV=1 :VAR_GV est le bit0 de la variable 8 bits VAR_GRANDE_VIT :
#DEFINE VAR_GV VAR_GRANDE_VIT,0
Test BP_MVT_SENS actifsOn dcomposera ce test de cette manire.
Z est un bit du registre STATUS. Pour tester ce bit on pourra utiliser la syntaxe
suivante : STATUS,Z
Action sur VAR_DEP :VAR_DEP est une variable sur 8 bits.
BP_MVT_SENSactifs
?
OUI
NON
W=$FF
PORTC-W
Z=0
?
OUI
NON
-
8/13/2019 Eval Programmation Complete
5/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
Test IMA_ACC :Dans le fichier de dclarations on a la ligne suivante :
#DEFINE IMA_ACC PORTE,0
Test BP_M=0, BP_CONDUCT1=0 et BP_CONDUCT2=0 :Dans le fichier de dclarations on a les lignes suivantes :
#DEFINE BP_M PORTB,1
#DEFINE BP_CONDUCT1 PORTB,2
#DEFINE BP_CONDUCT2 PORTB,3
Question11Ecrirele programme principal en langage assembleur correspondant lalgorigramme
du programme principal. Justifiertoutes vos instructions par des commentaires.
Complterle document rponse 3.
II Analyse de la version en langage C
II.1 Etude du sous programme detect_sens
Question12Dfinirla sortie DIR (voir description de F1.3.3 Dtecterle sens de rotation des
moteurs ).
Question13Rappeler le rsultats des oprations suivantes :
-a0,
-a1,
-a+0,
-a+1.
Sachant que acorrespond une variable sur 1 bit.
Question14En dduire quelle est lopration raliser avec DIRpour mettre 1la variable
DIR_GLIsans modifier les autres variables.
Question15Quelle est lopration raliser avec DIR pour mettre 0la variable DIR_GLIsans
modifier les autres variables.
-
8/13/2019 Eval Programmation Complete
6/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
On rappelle les instructions suivantes du langage C :
Les oprateurs logiques bit bit :
Ces oprateurs agissent sur des mots binaires. Ils effectuent entre deux mots une
opration logique sur les bits de mme rang.
Oprateur Fonction Notation
& ET Z=X&Y
| OU Z=X|Y
^ OU exclusif Z=X^Y
~ NON Z=~Y
>> Dcalage droite des bitsZ=X>>4 (Z prend la valeur de X
aprs le dcalage droite de 4 bits)
-
8/13/2019 Eval Programmation Complete
7/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
II.2 Etude du sous programme inc_pos_gli
Le sous programme inc_pos_gli permet dincrmenter une seule fois la variable
POS_GLI.
Nous pouvons agir uniquement sur les variables POS_GLI_H et POS_GLI_L.
Question17Dfinirla variable POS_GLI(voir description de F1.3 Calculer la position
courante ).
Question18Dfinirles variables POS_GLI_H et POS_GLI_L.En supposant que POS_GLI=$8153, indiquerles valeurs prises par POS_GLI_Het
POS_GLI_L.
Question19Dessinerun tableau montrant la variable POS_GLIsincrmentant de $7FFD
$8002 ainsi que les variables POS_GLI_Het POS_GLI_Lcorrespondantes.
Question20Proposerun algorigramme permettant de raliser le sous programme inc_pos_gli.
Il faut saider des questions prcdentes.
Question21Ecrirele programme en langage C correspondant lalgorigramme inc_pos_gli.
II.3 Etude du sous programme dec_pos_gli
Le sous programme dec_pos_gli permet de dcrmenter une seule fois la
variable POS_GLI.
Nous ne pouvons agir uniquement sur les variables POS_GLI_H et POS_GLI_L.
Question22Proposerun algorigramme permettant de raliser le sous programme dec_pos_gli.
Question23
Ecrirele programme en langage C correspondant lalgorigramme dec_pos_gli.
-
8/13/2019 Eval Programmation Complete
8/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
DOCUMENT REPONSE 1
Nom de la broche Configuration (E, S ou NU (Non Utilis)) Nom du signal
RA0
RA1
RA2
RA3
RA4
RA5
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
-
8/13/2019 Eval Programmation Complete
9/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
DOCUMENT REPONSE 2
;***********************************************************************
;* sous programme initialisation (init) partiel *
;***********************************************************************;* Ce sous programme permet d'initialiser toutes les variables, et les registres *
;* du PIC16F877 *
;***********************************************************************
init
;***********************************************************************
;* A complter : slection banque 0 (par dfaut) *
;***********************************************************************
;***********************************************************************
;* Initialisation des variables *
;***********************************************************************
BCF DEP_RAP1
BCF DEP_RAP2
BCF DEP
CLRF DIR
CLRF VAR_TEMPO
CLRF VAR_GRANDE_VIT
CLRF POS_GLI_PREC_L
;***********************************************************************
;* partie complter : configuration du PORTD *
;***********************************************************************
;***********************************************************************;* partie complter : configuration du PORTA et PORTE *
;***********************************************************************
RETURN
-
8/13/2019 Eval Programmation Complete
10/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
DOCUMENT REPONSE 3;***********************************************************************
;* PROGRAMME PRINCIPAL *
;***********************************************************************
LIST p=16F877#include
ORG 0x0000 ; adresse de dpart aprs Reset
GOTO DEBUT
DEBUT ORG 0x060
;***********************************************************************
;* Partie complter : on dbute par lappel du sous programme init *
;* Il faut crire tout le programme principal en langage assembleur *
;***********************************************************************
-
8/13/2019 Eval Programmation Complete
11/47
Sige 406 Evaluation programmationQuestionnement de la partie crite
-
8/13/2019 Eval Programmation Complete
12/47
Evaluation programmation
Partie 2
Questionnement TP
-
8/13/2019 Eval Programmation Complete
13/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
I Cration du projet
Critres dvaluations :
PMC1 :mettre jour un projet existant ou crer un projet
PMC1.1 :ouvrir ou crer un projet
PMC1.2 :choisir loutil de construction
PMC1.3 :configurer les paramtres de constructions
PMC1.4 :choisir le microcontrleur
PMC1.7 :ajouter le fichier source et les fichiers include au projet
PMC2 :compiler le projet
PMC2.1 :lancer la compilation
PMC2.2 : dtecter les erreurs
PMC2.3:corriger les erreurs
On dispose de trois fichiers :-406.c,-Decla.h,-pic1687x.
Ces fichiers sont stocks dans votre rpertoire de travail.On dsire crer un projet nomm 406 dans un autre rpertoire nomm 406_TPx
(x=1 si vous passez en premier, x=2 si vous passez en second).Ce rpertoire sera crer.
Question1Copierles trois fichiers fournis dans le nouveau rpertoire.Crerle projet permettant dutiliser les fichiers fournis.Compilervotre projet.
Une fois le projet compil correctement appeler le professeur pour valider votretravail en lui expliquant les diffrentes tapes.
-
8/13/2019 Eval Programmation Complete
14/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
II Programmation et test de la mmorisation sur le sige 406
Critres dvaluations :
PMC4 :programmer le microcontrleur
PMC4.1 :enregistrer le fichier de programmation
PMC4.2 :mettre en uvre le programmateur
PMC4.3 :placer correctement le microcontrleur
PMC4.4 :slectionner le composant programmer laide dun logicielPMC4.5 :charger le fichier de programmationPMC4.6 : programmer le composant
PMC5 :rdiger le compte rendu
PMC5.3 : proposer une mthode de tests du programme
PMC5.4 : traduire les rsultats observs
PMC5.5 :conclure sur la validit du programme test
Le programme 406.c permet de :-calculer la position courante du sige,-mmoriser une position dun conducteur,-rappeler les positions mmorises
Ce programme ne gre pas la grande vitesse.
On souhaite :-programmer le PIC16F877,-tester le programme par une observation sur le systme sige 406 .
Question2A partir du dossier technique, rappelerquelle est la procdure de mmorisation.Que se passe-t-il la fin de la mmorisation ?
Question3A partir du dossier technique, rappelerquelle est la procdure de rappel dune
position mmorise.
Que se passe-t-il la fin du rappel.
Question4 : critre PMC5.3 : proposer une mthode de testProposerune mthode de test par lobservation sur le systme sige 406 pour
vrifier que le programme permet bien :
-de mmoriser la position de conduite n1,
-de rappeler la position de conduite mmorise n1,
Une fois la mthode trouve et rdige, vous pouvez passer la question suivante.
-
8/13/2019 Eval Programmation Complete
15/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
La question suivante se fait sur le poste de programmation et sur le sige 406.Si la place est occupe ne perdez pas de temps et passez la 3 partie Test du sous
programme memo grce au logiciel MPLAB.
Question5 : critre PMC4 : programmer le microcontrleurProgrammerle PIC16F877avec le fichier adquat.
Question6 : critre PMC5.4 : traduire les rsultats des tests observs et PMC5.5 :conclure sur la validit du programme test
Placercorrectement le PIC16F877sur la carte PIC .Insrerla carte PIC dans le rack.Procder aux tests et validerle fonctionnement du programme.Vous devez faire valider le fonctionnement par le professeur.Rdigerlobservation de vos tests.
-
8/13/2019 Eval Programmation Complete
16/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
III Test du sous programme memo grce au logiciel MPLAB
Critres dvaluations :
PMC3 :simuler le programme en mode pas pas
PMC3.1 :crer des stimuli
PMC3.2 :crer une fentre de visualisation
PMC3.3 :observer le contenu des mmoires du microcontrleur
PMC3.4 :faire dfiler le programme pour diffrents cas de fonctionnement
PMC3.4.1 :montrer le droulement du programme quand rien ne se passe
PMC3.4.2 : montrer le droulement du programme lorsque lon agit surcertaines entres et/ou certaines variables
PMC3.4.3 :montrer laction du programme sur les sorties et/ou lesvariables et/ou le contenu des mmoires.
PMC3.4.4 :conclure sur le fonctionnement du programme
PMC5 :rdiger le compte rendu
PMC5.3 : proposer une mthode de tests du programme
PMC5.4 : traduire les rsultats observs
PMC5.5 :conclure sur la validit du programme test
Dans cette partie on souhaite valider par la simulation la mmorisation de laposition de conduite 1.
III.1 Initialisation des entres
Question7Complterle document rponse 1 en indiquant :
-les correspondances des broches dentres du PIC16F877 avec les noms des
signaux,
-les niveaux logiques de toutes les entres du PIC16F877 lorsque le sige est
au repos.
Il faut saider de la description de la fonction F12 Acqurir les consignes
Question8 : critre PMC3.1 : crer les stimuliCrer trois stimuli diffrents sauvegarder dans le rpertoire du projet intituls :
-PORTC.Psti,
-PORTB.Psti,-PORTE.Psti
Question9En procdant de la manire suivante, configurerles entres du PIC16F877
correspondant un fonctionnement du sige au repos :
Lancer la simulation du programme (touche F9).
Ouvrir le stimulus PORTB.Psti
Configurer les niveaux logiques des entres du port B (sige au repos).
Fermer le stimulus PORTB.Psti
Recommencer pour les ports C et E.
Question10 : critre PMC3.2 : crer une fentre de visualisationVrifierque les entres du PIC16F877 sont configures correctement.
-
8/13/2019 Eval Programmation Complete
17/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
Question11 : critre PMC3.4.1 : montrer le droulement du programme quand rienne se passe
En simulant le programme en pas pas vrifierque son excution correspond bien lvolution de lalgorigramme du programme principal lorsque le sige est au repos.
Faire valider par le professeur.
III.2 Test du sous programme memo
III.2.1 Dfinition du cahier des charges du sous programme memo
Il faut saider de la description des fonctions F13 Calculer la position courante et F14 Mmoriser la position
Cette partie vise exploiter le dossier technique afin de mieux comprendre le rle dusous programme memo .
Si vous tes bloqu vous pouvez passer la suite et revenir ensuite cette partie.Ne perdez pas de temps sur cette partie
Question12A votre avis, dans quel type de mmoire est stocke la position courante du sige ?
Question13Indiquer le nombre de variables qui composent la position courante du sige (voir
F13 Calculer la position courante )Nommerces variables.Dterminer alors le nombre doctets ncessaires pour avoir une information sur la
position courante du sige.
Question14
A partir de lextrait de la documentation constructeur du PIC16F877, dterminer lacapacit de la mmoire utilis pour stocker la position courante du sige.
Est-elle suffisante ?(on suppose quil faut stocker 2 positions de conduite plus la
position courante). Justifiervotre rponse.
On donne un extrait du fichier Decla.h :
static unsigned char POS_GLI_MEM1_L=0x00;static unsigned char POS_GLI_MEM1_H=0x01;static unsigned char POS_REHA_MEM1_L=0x02;static unsigned char POS_REHA_MEM1_H=0x03;static unsigned char POS_SITE_MEM1_L=0x04;static unsigned char POS_SITE_MEM1_H=0x05;static unsigned char POS_DOS_MEM1_L=0x06;static unsigned char POS_DOS_MEM1_H=0x07;
Question15Nommerles adresses o seront stockes les variables reprsentant la position
courante.
Indiquer les valeurs de ces adresses.
Question16Reprsenterpartiellement la mmoire o seront stockes les variables reprsentant la
position courante en indiquant :
-les noms des variables,
-les nom des adresses,
-les valeurs des adresses.
-
8/13/2019 Eval Programmation Complete
18/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
III.2.2 Test du sous programme memo
Procdure de test : critre PMC5.3 : proposer une mthode de test du programme
Question17
Proposerune procdure de test pour vrifier que lon stocke correctement lesvariables en mmoire.
On veut notamment voir dans cette procdure les tapes suivantes :
-modification des variables reprsentant la position courante (on sait que la
position initiale pour tous les mouvements est $7FFF). On se fixe 4 valeurs fixer qui sontles suivantes :
-POS_GLI=$8150,-POS_REHA=$7F32,-POS_SITE=$80AB,-POS_DOS=$7E6A
-mthode pour excuter le sous programme memo ,
-mthode pour mmoriser le position,-observation des variables reprsentant la position courante stockes en
mmoire aux bonnes adresses.
Tests : critres dvaluation :
PMC3 :simuler le programme en mode pas pas
PMC3.2 :crer une fentre de visualisation
PMC3.3 :observer le contenu des mmoires du microcontrleur
PMC3.4 :faire dfiler le programme pour diffrents cas de fonctionnement
PMC3.4.1 :montrer le droulement du programme quand rien ne se passe
PMC3.4.2 : montrer le droulement du programme lorsque lon agit surcertaines entres et/ou certaines variables
PMC3.4.3 :montrer laction du programme sur les sorties et/ou lesvariables et/ou le contenu des mmoires.
Question18Effectuerles tests en vrifiant que le programme fonctionne selon vos attentes.Attention :le sous programme prod_sign_sonore utilise des temporisations vous
resterez bloqu dedans. Pour en sortir il faudra faire un reset et excuter de nouveau le
programme principal lorsque le sige est au repos.
Faire valider par le professeur
-
8/13/2019 Eval Programmation Complete
19/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
Transcription des rsultats : critre PMC5.5 : conclure sur la validit du programmetest
Question19On souhaite savoir ce que vous avez observez tape par tape.
Transcrirealors les rsultats observs.
Question20Reprsenterle contenu de la mmoire (partiel : uniquement ce qui nous intresse) en
indiquant :
-o se trouvent les adresses en notant leurs noms sur cette reprsentation
-o se trouvent les donnes stockes en notant leurs noms sur cette
reprsentation.
-
8/13/2019 Eval Programmation Complete
20/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
IV Validation que la position est mmorise
Dans cette partie on souhaite valider que lon crit rellement dans la mmoire duPIC16F877 par une lecture de son contenu.
On sait que ladresse de dbut de la mmoire du PIC16F877 est $4200.Que la deuxime adresses est $4202.
Etc
Critres dvaluation :
PMC4 :programmer le composant programmable
PMC4.7 : lire le contenu du composant
PMC5 :rdiger le compte rendu
PMC5.3 : proposer une mthode de test du programme
PMC5.4 : traduire les rsultats observs
PMC5.5 :conclure sur la validit du programme test
Question21Proposerune mthode pour vrifier que lon stocke rellement les positions en
mmoire.
La question suivante se fait sur le poste de programmation et sur le sige 406.Si ces postes sont occups, ne perdez pas de temps et passez la 5 partie
Modification du programme pour mmoriser la position du conducteur2 .
Question22Vrifierque la position du sige est bien mmorise en mmoire en appliquant votre
mthode.
Faire valider par le professeur en expliquant la mthode et en commentant lecontenu de la mmoire du PIC16F877.
Vous noterez notamment :
-les actions ralises sur le sige,-les valeurs contenues dans la mmoire,
-la conclusion.
-
8/13/2019 Eval Programmation Complete
21/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
V Modification du programme pour mmoriser la position du conducteur2
On souhaite modifier lalgorigramme et le programme afin que lon puissemmoriser les deux positions de conduites.
Question23Proposerun nouvel algorigramme.
Question24Modifierle sous programme memo .
Question25Testervotre nouveau programme.
Faire valider par le professeur.
Question26Testervotre programme sur le sige 406.
Faire valider par le professeur.
-
8/13/2019 Eval Programmation Complete
22/47
Sige 406 Evaluation programmationQuestionnement de la partie TP
DOCUMENT REPONSE 1
Nom de la broche Nom du signal Etat logique lorsque le sige est au
repos
RB1
RB2
RB3
RB4 CAPT_GLI 0RB5 CAPT_REHA 0RB6 CAPT_SITE 0RB7 CAPT_DOS 0
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RE0 IMA_ACC 1RE1 FC_AV 1RE2 FC_AR 0
-
8/13/2019 Eval Programmation Complete
23/47
Evaluation programmation
Partie 3
Document ressource
-
8/13/2019 Eval Programmation Complete
24/47
Evaluation programmation Document ressource
1. ALGORIGRAMMES
1.1 Programme principal du sige 406
Systmealiment
?
OUI
init
FIN
DEBUT
gvGR_VIT,COM_GLI_AV,COM_GLI_AR,VAR GV
FC_AV=0?
NON
OUI
GR_VIT,COM_GLI_AV,COM_GLI_AR,VAR_GV
VAR_GV=1?
NON
OUI
gv
DIR
BP_MVT_SENSactifs ?
NON
detect_sens
OUI
VAR_GV0?
OUI
NON
VAR_DEP=$01
VAR_DEP=$01?
NON
OUI
DIRmem_pos_cour
VAR_DEP=$00
IMA_ACC1?
OUI
NON
NON
BP_M=0 ?NON
memo
OUI POS_MVT_MEM1,
POS_MVT_MEM2,COM_BUZ
BP_CONDUCT1=0?
NON
rappel1
OUI
COM_MVT_SENS,COM_BUZ
POS_MVT,POS_MVT_MEM1
BP_CONDUCT2=0?
NON
OUI
COM_MVT_SENS,COM BUZ
POS_MVT,POS MVT MEM2
rappel2
-
8/13/2019 Eval Programmation Complete
25/47
Evaluation programmation Document ressource
1.2 Sous-programme detect_sens
BP_GLI_AV=0?
OUI
NON
DIR_GLI=1
DEBUT
BP_GLI_AR=0?
OUI
NON
DIR_GLI=0
BP_REHA_MONT=0?
OUI
NON
DIR_REHA=1
BP_REHA_DESC=0?
OUI
NON
DIR_REHA=0
BP_SITE_MONT=0?
OUI
NON
DIR_SITE=1
BP_SITE_DESC=0?
OUI
NON
DIR_SITE=0
BP_DOS_AV=0?
OUI
NON
DIR_DOS=1
BP_DOS_AR=0?
OUI
NON
DIR_DOS=0
DEBUT
-
8/13/2019 Eval Programmation Complete
26/47
Evaluation programmation Document ressource
1.3 Programme dinterruption calculer_position_courante
bit 4 de CHANG_CAPT
bit 4 de MEM_CAPT
?
OUI
NON
dec_pos_gli
DEBUT
Sauvegarder les nouveaux
tats des capteurs dansCHANG_CAPT
DIR_GLI=0?
OUI
NON
inc_pos_gli
bit 5 de CHANG_CAPT
bit 5 de MEM_CAPT
?
OUI
NON
dec_pos_reha
DIR_REHA=0
?OUI
NON
inc_pos_reha
bit 6 de CHANG_CAPT
bit 6 de MEM_CAPT
?
OUI
NON
dec_pos_site
DIR_SITE=0?
OUI
NON
inc_pos_site
1
1
bit 7 de CHANG_CAPT
bit 7 de MEM_CAPT
?
OUI
NON
dec_pos_dos
DIR_DOS=0?
OUI
NON
inc_pos_dos
Mmoriser les nouveaux tats descapteurs
MEM_CAPT=CHANG_CAPT
FIN
-
8/13/2019 Eval Programmation Complete
27/47
Evaluation programmation Document ressource
1.4 Sous-programme memo partiel permettant de mmoriser uniquementune position de conduite
BP_M=0?
OUI
NON
FIN_MEMO=1
DEBUT
BP_M=0ET
BP_CONDUCT1=0?
OUI
mem1
prod_sign_sonore
BP_M=0OU
BP_CONDUCT1=0?
NON
NON
OUI
FIN
-
8/13/2019 Eval Programmation Complete
28/47
Evaluation programmation
Partie 4
Documentation constructeur PIC16F877
-
8/13/2019 Eval Programmation Complete
29/47
2001 Microchip Technology Inc. DS30292C-page 1
PIC16F87X
Devices Included in this Data Sheet:
Microcontroller Core Features:
High performance RISC CPU
Only 35 single word instructions to learn
All single cycle instructions except for program
branches which are two cycle
Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
Up to 256 x 8 bytes of EEPROM Data Memory
Pinout compatible to the PIC16C73B/74B/76/77
Interrupt capability (up to 14 sources)
Eight level deep hardware stack
Direct, indirect and relative addressing modes
Power-on Reset (POR)
Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Programmable code protection
Power saving SLEEP mode
Selectable oscillator options
Low power, high speed CMOS FLASH/EEPROM
technology
Fully static design
In-Circuit Serial Programming (ICSP)via two
pins
Single 5V In-Circuit Serial Programming capability
In-Circuit Debugging via two pins
Processor read/write access to program memory
Wide operating voltage range: 2.0V to 5.5V
High Sink/Source Current: 25 mA
Commercial, Industrial and Extended temperature
ranges
Low-power consumption:
- < 0.6 mA typical @ 3V, 4 MHz
- 20 A typical @ 3V, 32 kHz
- < 1 A typical standby current
Pin Diagram
Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler,can be incremented during SLEEP via external
crystal/clock
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
10-bit multi-channel Analog-to-Digital converter
Synchronous Serial Port (SSP) with SPI(Master
mode) and I2C (Master/Slave)
Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
Brown-out detection circuitry for
Brown-out Reset (BOR)
PIC16F873
PIC16F874
PIC16F876
PIC16F877RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F
877/874
PDIP
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
-
8/13/2019 Eval Programmation Complete
30/47
PIC16F87X
DS30292C-page 6 2001 Microchip Technology Inc.
FIGURE 1-2: PIC16F874 AND PIC16F877 BLOCK DIAGRAM
FLASH
ProgramMemory
13 Data Bus 8
14Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
FileRegisters
Direct Addr 7
RAM Addr(1) 9
Addr MUX
IndirectAddr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-upTimer
OscillatorStart-up Timer
Power-onReset
WatchdogTimer
InstructionDecode &
Control
TimingGeneration
OSC1/CLKINOSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKIRA5/AN4/SS
RC0/T1OSO/T1CKIRC1/T1OSI/CCP2RC2/CCP1
RC3/SCK/SCLRC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
8
8
Brown-outReset
Note 1: Higher order bits are from the STATUS register.
USARTCCP1,2 Synchronous
10-bit A/DTimer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Parallel Slave Port
8
3
Data EEPROM
RB0/INTRB1RB2
RB3/PGM
RB4
RB5
RB6/PGCRB7/PGD
DeviceProgram
FLASHData Memory
Data
EEPROM
PIC16F874 4K 192 Bytes 128 Bytes
PIC16F877 8K 368 Bytes 256 Bytes
In-CircuitDebugger
Low-Voltage
Programming
RD0/PSP0RD1/PSP1
RD2/PSP2
RD3/PSP3RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
-
8/13/2019 Eval Programmation Complete
31/47
PIC16F87X
DS30292C-page 12 2001 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS)
and RP0 (STATUS) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTERFILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register (FSR).
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Note: EEPROM Data Memory description can be
found in Section 4.0 of this data sheet.
-
8/13/2019 Eval Programmation Complete
32/47
2001 Microchip Technology Inc. DS30292C-page 13
PIC16F87X
FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCLSTATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCLSTATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFhBank 0 Bank 1
Unimplemented data memory locations, read as 0.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876.
2: These registers are reserved, maintain these registers clear.
FileAddress
Indirect addr.(*) Indirect addr.(*)
PCLSTATUS
FSR
PCLATH
INTCON
PCLSTATUS
FSR
PCLATH
INTCON
100h
101h
102h103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
180h
181h
182h183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
120h 1A0h
17Fh 1FFhBank 2 Bank 3
Indirect addr.(*)
PORTD(1)
PORTE(1)TRISD(1)
ADRESL
TRISE(1)
TMR0 OPTION_REG
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
TXSTA
SPBRG
ADCON1
GeneralPurposeRegister
GeneralPurposeRegister
GeneralPurposeRegister
GeneralPurposeRegister
1EFh
1F0haccesses70h - 7Fh
EFh
F0haccesses70h-7Fh
16Fh
170haccesses70h-7Fh
GeneralPurposeRegister
GeneralPurposeRegister
TRISBPORTB
96 Bytes 80 Bytes 80 Bytes 80 Bytes
16 Bytes 16 Bytes
SSPCON2
EEDATA
EEADR
EECON1
EECON2
EEDATHEEADRH
Reserved(2)
Reserved(2)
FileAddress
FileAddress
FileAddress
FileAddress
-
8/13/2019 Eval Programmation Complete
33/47
2001 Microchip Technology Inc. DS30292C-page 15
PIC16F87X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on:
POR,BOR
Detailson
page:
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
01h TMR0 Timer0 Module Register xxxx xxxx 47
02h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 26
03h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18
04h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27
05h PORTA PORTA Data Latch when written: PORTA pins when read --0x 0000 29
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31
07h PORTC PORTC Data Latch when writ ten: PORTC pins when read xxxx xxxx 33
08h(4)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 3509h(4) PORTE RE2 RE1 RE0 ---- -xxx 36
0Ah(1,3) PCLATH Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 22
0Dh PIR2 (5) EEIF BCLIF CCP2IF -r-0 0--0 24
0Eh TMR1L Holding register for the Least Signif icant Byte of the 16-bit TMR1 Register xxxx xxxx 52
0Fh TMR1H Holding register for the Most Signif icant Byte of the 16-bit TMR1 Register xxxx xxxx 52
10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 51
11h TMR2 Timer2 Module Register 0000 0000 55
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55
13h SSPBUF Synchronous Serial Port Rece ive Buffer/Transmit Register xxxx xxxx 70, 73
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx 57
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx 5717h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 58
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 96
19h TXREG USART Transmit Data Register 0000 0000 99
1Ah RCREG USART Receive Data Register 0000 0000 101
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx 57
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx 57
1Dh CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 116
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 00-0 111
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.Shaded locations are unimplemented, read as 0.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whosecontents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as 0.5: PIR2 and PIE2 are reserved on these devices; always maintain these bits clear.
-
8/13/2019 Eval Programmation Complete
34/47
PIC16F87X
DS30292C-page 16 2001 Microchip Technology Inc.
Bank 1
80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19
82h(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 2683h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18
84h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27
85h TRISA PORTA Data Direction Register --11 1111 29
86h TRISB PORTB Data Direction Register 1111 1111 31
87h TRISC PORTC Data Direction Register 1111 1111 33
88h(4) TRISD PORTD Data Direction Register 1111 1111 35
89h(4) TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 37
8Ah(1,3) PCLATH Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
8Ch PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 21
8Dh PIE2 (5) EEIE BCLIE CCP2IE -r-0 0--0 23
8Eh PCON POR BOR ---- --qq 25
8Fh Unimplemented
90h Unimplemented 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 68
92h PR2 Timer2 Period Register 1111 1111 55
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 73, 74
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 66
95h Unimplemented
96h Unimplemented
97h Unimplemented
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 95
99h SPBRG Baud Rate Generator Register 0000 0000 97
9Ah Unimplemented
9Bh Unimplemented
9Ch Unimplemented
9Dh Unimplemented
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 116
9Fh ADCON1 ADFM PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 112
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on:
POR,BOR
Detailson
page:
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.Shaded locations are unimplemented, read as 0.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whosecontents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.3: These registers can be addressed from any bank.4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as 0.5: PIR2 and PIE2 are reserved on these devices; always maintain these bits clear.
-
8/13/2019 Eval Programmation Complete
35/47
2001 Microchip Technology Inc. DS30292C-page 17
PIC16F87X
Bank 2
100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
101h TMR0 Timer0 Module Register xxxx xxxx 47
102h(3) PCL Program Counters (PC) Least Significant Byte 0000 0000 26
103h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18
104h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27
105h Unimplemented
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31
107h Unimplemented
108h Unimplemented
109h Unimplemented
10Ah(1,3) PCLATH Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
10Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 41
10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 41
10Eh EEDATH EEPROM Data Register High Byte xxxx xxxx 41
10Fh EEADRH EEPROM Address Register High Byte xxxx xxxx 41
Bank 3
180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19
182h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 26
183h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18
184h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27
185h Unimplemented
186h TRISB PORTB Data Direction Register 1111 1111 31
187h Unimplemented
188h Unimplemented
189h Unimplemented
18Ah(1,3) PCLATH Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
18Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
18Ch EECON1 EEPGD WRERR WREN WR RD x--- x000 41, 42
18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- 41
18Eh Reserved maintain clear 0000 0000
18Fh Reserved maintain clear 0000 0000
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on:
POR,BOR
Detailson
page:
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.Shaded locations are unimplemented, read as 0.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whosecontents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.3: These registers can be addressed from any bank.4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as 0.5: PIR2 and PIE2 are reserved on these devices; always maintain these bits clear.
-
8/13/2019 Eval Programmation Complete
36/47
PIC16F87X
DS30292C-page 18 2001 Microchip Technology Inc.
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see theInstruction Set Summary."
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
bit 3 PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
bit 2 Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWFinstructions)
(for borrow, the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the twos
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
- n = Value at POR 1= Bit is set 0= Bit is cleared x = Bit is unknown
-
8/13/2019 Eval Programmation Complete
37/47
2001 Microchip Technology Inc. DS30292C-page 33
PIC16F87X
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting aTRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., putthe contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC
pins can be configured with normal I2C levels, or with
SMBus levels by using the CKE bit (SSPSTAT).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-write instructions (BSF, BCF, XORWF) with TRISC as
destination, should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5: PORTC BLOCK DIAGRAM(PERIPHERAL OUTPUT
OVERRIDE) RC,RC
FIGURE 3-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUTOVERRIDE) RC
Port/Peripheral Select(2)
Data BusWRPort
WRTRIS
RD
Data Latch
TRIS Latch
RD
SchmittTrigger
QD
QCK
Q D
EN
Peripheral Data Out0
1
QD
QCK
P
N
VDD
VSS
Port
Peripheral
OE(3)
Peripheral Input
I/Opin(1)
Note 1: I/O pins have diode protection to VDDand VSS.
2: Port/Peripheral select signal selects between portdata and peripheral output.
3: Peripheral OE (output enable) is only activated ifperipheral select is active.
TRIS
Port/Peripheral Select(2)
Data Bus
WRPort
WRTRIS
RD
Data Latch
TRIS Latch
RD
SchmittTrigger
QD
QCK
Q D
EN
Peripheral Data Out0
1
QD
QCK
P
N
VDD
Vss
Port
Peripheral
OE(3)
SSPl Input
I/Opin(1)
Note 1: I/O pins have diode protection to VDDand VSS.2: Port/Peripheral select signal selects between port data
and peripheral output.3: Peripheral OE (output enable) is only activated if
peripheral select is active.
0
1
CKE
SSPSTAT
SchmittTriggerwithSMBuslevels
TRIS
-
8/13/2019 Eval Programmation Complete
38/47
PIC16F87X
DS30292C-page 34 2001 Microchip Technology Inc.
TABLE 3-5: PORTC FUNCTIONS
TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output.
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI
and I2C modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or
Synchronous Data.
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other
RESETS
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged
-
8/13/2019 Eval Programmation Complete
39/47
PIC16F87X
DS30292C-page 112 2001 Microchip Technology Inc.
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-ister pair, the GO/DONE bit (ADCON0) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit1= Right justified. 6 Most Significant bits of ADRESH are read as 0.
0= Left justified. 6 Least Significant bits of ADRESL are read as 0.
bit 6-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1: These channels are not available on PIC16F873/876 devices.
2: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
- n = Value at POR 1= Bit is set 0= Bit is cleared x = Bit is unknown
A = Analog input D = Digital I/O
PCFG3:
PCFG0
AN7(1)
RE2
AN6(1)
RE1
AN5(1)
RE0
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0VREF+ VREF-
CHAN/
Refs(2)
0000 A A A A A A A A VDD VSS 8/0
0001 A A A A VREF+ A A A RA3 VSS 7/1
0010 D D D A A A A A VDD VSS 5/0
0011 D D D A VREF+ A A A RA3 VSS 4/1
0100 D D D D A D A A VDD VSS 3/00101 D D D D VREF+ D A A RA3 VSS 2/1
011x D D D D D D D D VDD VSS 0/0
1000 A A A A VREF+ VREF- A A RA3 RA2 6/2
1001 D D A A A A A A VDD VSS 6/0
1010 D D A A VREF+ A A A RA3 VSS 5/1
1011 D D A A VREF+ VREF- A A RA3 RA2 4/2
1100 D D D A VREF+ VREF- A A RA3 RA2 3/2
1101 D D D D VREF+ VREF- A A RA3 RA2 2/2
1110 D D D D D D D A VDD VSS 1/0
1111 D D D D VREF+ VREF- D A RA3 RA2 1/2
-
8/13/2019 Eval Programmation Complete
40/47
2001 Microchip Technology Inc. DS30292C-page 135
PIC16F87X
13.0 INSTRUCTION SET SUMMARY
Each PIC16F87X instruction is a 14-bit word, divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16F87X instruction
set summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and controloperations. Table 13-1shows the opcode field descriptions.
For byte-orientedinstructions, frepresents a file reg-
ister designator and drepresents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If dis zero, the result is
placed in the W register. If dis one, the result is placed
in the file register specified in the instruction.
For bit-orientedinstructions, brepresents a bit field
designator which selects the number of the bit affected
by the operation, while frepresents the address of the
file in which the bit is located.
For literal and controloperations, k represents an
eight or eleven bit constant or literal value.
TABLE 13-1: OPCODE FIELDDESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories:
Byte-orientedoperations
Bit-orientedoperations
Literal and controloperations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true, or theprogram counter is changed as a result of an instruc-
tion, the instruction execution time is 2 s.
Table 13-2 lists the instructions recognized by the
MPASMTMassembler.
Figure 13-1 shows the general formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FORINSTRUCTIONS
A description of each instruction is available in the
PICmicroMid-Range Reference Manual, (DS33023).
Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don't care location (= 0or 1).The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-down bit
Note: To maintain upward compatibility with
future PIC16F87X products, do not use the
OPTIONand TRISinstructions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination ff = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit addressf = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALLand GOTOinstructions only
-
8/13/2019 Eval Programmation Complete
41/47
PIC16F87X
DS30292C-page 136 2001 Microchip Technology Inc.
TABLE 13-2: PIC16F87X INSTRUCTION SET
Mnemonic,
OperandsDescription Cycles
14-Bit Opcode Status
AffectedNotes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPFXORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, df, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in fExclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
11
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,21,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro Mid-Range MCU
Family Reference Manual (DS33023).
-
8/13/2019 Eval Programmation Complete
42/47
2001 Microchip Technology Inc. DS30292C-page 137
PIC16F87X
13.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [label] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight bit literal k
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [label] ADDWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register f. If dis 0, the result
is stored in the W register. If dis
1, the result is stored back in
register f.
ANDLW AND Literal with W
Syntax: [label] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
ANDed with the eight bit literal
'k'. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [label] ANDWF f,d
Operands: 0 f 127d [0,1]
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
BCF Bit Clear f
Syntax: [label] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f)
Status Affected: None
Description: Bit 'b' in register 'f' is cleared.
BSF Bit Set f
Syntax: [label] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
BTFSS Bit Test f, Skip if Set
Syntax: [label] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f) = 1
Status Affected: None
Description: If bit 'b' in register 'f' is '0', the next
instruction is executed.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOPis
executed instead, making this a
2TCYinstruction.
BTFSC Bit Test, Skip if Clear
Syntax: [label] BTFSC f,b
Operands: 0 f 1270 b 7
Operation: skip if (f) = 0
Status Affected: None
Description: If bit 'b' in register 'f' is '1', the next
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCYinstruction.
-
8/13/2019 Eval Programmation Complete
43/47
PIC16F87X
DS30292C-page 138 2001 Microchip Technology Inc.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1TOS,
k PC,(PCLATH) PC
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
. The upper bits of the PC
are loaded from PCLATH.CALLis
a two-cycle instruction.
CLRF Clear f
Syntax: [label] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Description: The contents of register fare
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,1 TO
1 PD
Status Affected: TO, PD
Description: CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affected: Z
Description: The contents of register fare
complemented. If dis 0, the
result is stored in W. If dis 1, the
result is stored back in register f.
DECF Decrement f
Syntax: [label] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affected: Z
Description: Decrement register f. If dis 0,
the result is stored in the W
register. If dis 1, the result is
stored back in register f.
-
8/13/2019 Eval Programmation Complete
44/47
-
8/13/2019 Eval Programmation Complete
45/47
PIC16F87X
DS30292C-page 140 2001 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)Status Affected: Z
Description: The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The eight bit literal kis loaded
into W register. The dont cares
will assemble as 0s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)Status Affected: None
Description: Move data from W register to
register 'f'.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: NoneDescription: No operation.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);TOS PC
Status Affected: None
Description: The W register is loaded with the
eight bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
-
8/13/2019 Eval Programmation Complete
46/47
2001 Microchip Technology Inc. DS30292C-page 141
PIC16F87X
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description belowStatus Affected: C
Description: The contents of register fare rotated
one bit to the left through the Carry
Flag. If dis 0, the result is placed in
the W register. If dis 1, the result is
stored back in register f.
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register fare
rotated one bit to the right through
the Carry Flag. If dis 0, the result
is placed in the W register. If dis
1, the result is placed back in
register f.
Register fC
Register fC
SLEEP
Syntax: [ label] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,1 TO,
0 PD
Status Affected: TO, PD
Description: The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2s
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) (destination)
Status
Affected:
C, DC, Z
Description: Subtract (2s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
-
8/13/2019 Eval Programmation Complete
47/47
PIC16F87X
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination),(f) (destination)
Status Affected: None
Description: The upper and lower nibbles of
register fare exchanged. If dis
0, the result is placed in the W
register. If dis 1, the result is
placed in register f.
XORLW Exclusive OR Literal with W
Syntax: [label] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k (W)
Status Affected: Z
Description: The contents of the W register
are XORed with the eight-bit lit-
eral 'k'. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [label] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) (destination)Status Affected: Z
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.