EVAL-ADAS3022EDZ User Guide - Analog Devices · configuration register allows the user to configure...

EVAL-ADAS3022EDZ User Guide UG-484

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluation Board for the ADAS3022 16-Bit, 8-Channel,

1 MSPS Data Acquisition System

Rev. A | of 32

FEATURES Full-featured evaluation board for the ADAS3022 Versatile analog signal conditioning circuitry On-board reference, clock oscillator, and buffers Converter evaluation and development board (EVAL-CED1Z)

compatible PC software for control and data analysis (time and

frequency domain)

KIT CONTENTS EVAL-ADAS3022EDZ evaluation board

ADDITIONAL EQUIPMENT NEEDED EVAL-CED1Z board Precision signal source World-compatible 7 V dc supply (enclosed with EVAL-CED1Z) USB cable

EVALUATION BOARD DESCRIPTION The EVAL-ADAS3022EDZ is an evaluation board for the ADAS3022 16-bit data acquisition system (DAS). This device integrates an 8-channel multiplexer, a high impedance programmable gain instrumentation amplifier (PGIA) stage with a high common-mode rejection, a precision 16-bit successive

approximation (no latency) analog-to-digital converter and precision 4.096 V reference offering an aggregate throughput of 1 million samples per second (1 MSPS).

The evaluation board is designed to demonstrate the perform-ance of the ADAS3022 and to provide an easy-to-understand interface for a variety of system applications. A full description of this product is available in the data sheet and should be consulted when utilizing this evaluation board.

The evaluation board is intended to be used with the Analog Devices, Inc., converter evaluation and development (CED) board, EVAL-CED1Z, a USB-based capture board connected to P4, the 96-pin interface.

On-board components include a high precision, buffered band gap 4.096 V reference (ADR434), reference buffers (AD8032), passive signal conditioning circuitry, and an FPGA for deserializing the serial conversion results and configuring the ADAS3022 via a 4-wire serial interface.

The P3 connector allows users to test their own interface with or without the optional Altera FPGA, U6 (programmed using the P2 and passive serial EEPROM, U5).

Figure 1. EVAL-ADAS3022EDZ Evaluation Board

ADAS3022PROTOTYPE AREA

FPGAPROGRAMMING

PORT

96-PININTERFACE

FPGA

40-PIN IDCSERIALINTERFACE

POWER

ANALOGINPUTS

1106

4-00

1

http://www.analog.com/ADAS3022?doc=UG-484

http://www.analog.com/adas3022?doc=UG-484.pdf


http://www.analog.com/eval-adas3022?doc=UG-484.pdf








http://www.analog.com/adr434?doc=UG-484.pdf

http://www.analog.com/ad8032?doc=UG-484.pdf



http://www.analog.com

UG-484 EVAL-ADAS3022EDZ User Guide

Rev. A | of 32

TABLE OF CONTENTS Features .............................................................................................. 1 Kit Contents ...................................................................................... 1 Additional Equipment Needed ....................................................... 1 Evaluation Board Description ......................................................... 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3

Overview ........................................................................................ 3 Device Description ....................................................................... 3 Jumpers, Solder Pads, and Test Points ....................................... 3 Analog Interface ........................................................................... 3 FPGA .............................................................................................. 4 Reference ....................................................................................... 4 Evaluation Board Schematics/PCB Layout ............................... 5 Basic Hardware Setup .................................................................. 5

Jumpers and Test Points ...............................................................6 Evaluation Board Software ...............................................................8

Software Installation .....................................................................8 Powering Up the Board ............................................................. 11 Running the Software with the Hardware Connected .......... 11 Software Operation .................................................................... 12 Time Domain Tab ...................................................................... 15 Histogram Tab ............................................................................ 16 Spectrum Tab .............................................................................. 17 Summary Tab .............................................................................. 18

Evaluation Board Schematics and Artwork ................................ 19 Products on this Evaluation Board .............................................. 27

Bill of Materials ........................................................................... 27 Related Links ................................................................................... 29

REVISION HISTORY 2/14—Rev. 0 to Rev. A Changes to Kit Contents Section .................................................... 1 Changes to Reference Section ......................................................... 4 Changes to Evaluation Board Schematics/PCB Layout Section . 5 Changes to Software Installation Section and Figure 4 through Figure 12; Renumbered Sequentially ............................................. 8 Changes to Running the Software with the Hardware Connected Section.......................................................................... 11 Changes to Software Operation Section and Figure 18; Added Figure 19 through Figure 27; Renumbered Sequentially .......... 12 Changes to Time Domain Tab Section and Figure 28 ............... 15 Changes to Histogram Tab Section and Figure 29 ..................... 16 Moved DC Testing Section and AC Testing Section ................. 16 Changes to Spectrum Tab Section and Figure 30 ...................... 17 Moved Summary Tab Section and Figure 31 .............................. 18

11/12—Revision 0: Initial Version


Rev. A | of 32

EVALUATION BOARD HARDWARE OVERVIEW The EVAL-ADAS3022EDZ evaluation board is designed to offer a simple evaluation of these revolutionary devices. From a block diagram perspective, the board uses a set of analog input test points (or an IDC header), some passive footprints for RC filtering and external reference, the ADAS3022 device, a serial interface to the on-board FPGA, and power that can be supplied locally or via EVAL-CED1Z or externally. Note that the ADAS3022 devices also have an on-chip reference; however, external circuitry is provided for users wanting to test other suitable options.

The small prototyping area can be useful for building additional circuitry, if desired. Each block has a specific function as defined in the following sections.

DEVICE DESCRIPTION The ADAS3022 is a complete data acquisition system (DAS) on a single chip that is capable of converting up to 1 MSPS and can resolve 8 single-ended inputs or 4 fully differential inputs up to ±24.576 V when using ±15 V supplies. It can accept the commonly used bipolar differential, bipolar single-ended, pseudo bipolar, or pseudo unipolar input signals as shown in Table 1 thus allowing the use of almost any direct sensor interface.

The ADAS3022 is an ideal replacement for a typical 16-bit 1 MSPS precision data acquisition system that simplifies the design challenges by eliminating signal buffering, level shifting, amplification/attenuation, common-mode rejection, settling time, or any of the other analog signal conditioning challenges while allowing smaller form factor, faster time to market, and lower costs.

Data communication to and from the ADAS3022 occurs asynchronously without any pipeline delay using a common 4-wire serial interface compatible with SPI, FPGA, and DSP.

A rising edge on CNV samples the differential analog inputs of a channel or channel pair. The ADAS3022 configuration register allows the user to configure the number of enabled channels, the differential input voltage range, and the interface mode using the evaluation board and software as detailed in this user guide. Complete specifications for the ADAS3022 are provided in the product data sheet and should be consulted in conjunction with this user guide when using the evaluation board. Full details on the EVAL-CED1Z are available on the Analog Devices website.

Table 1. Typical Input Range Selection Signals Input Range, VIN (V) Differential

±1 V ±1.28 V ±2.5 V ±2.56 V ±5 V ±10.24 V ±10 V ±20.48 V

Single Ended1 0 V to 1 V ±0.64 V 0 V to 2.5 V ±1.28 V 0 V to 5 V ±2.56 V 0 V to 10 V ±5.12 V

1 VCM adjusted to half the maximum input voltage.

JUMPERS, SOLDER PADS, AND TEST POINTS Numerous solder pads and test points are provided on the evaluation board and are detailed fully in Table 4, Table 5, and Table 6. Note the nomenclature for this evaluation board for a signal that is also connected to an IDC connector would be signal_I. The two 3-pin user selectable jumpers are used for the ADCs reference selection and are fully described in the Reference section.

ANALOG INTERFACE The analog interface is provided with test points for each of the analog inputs IN[7:0] and COM (that is, IN0_I is common to both the test point and to P1). The passive device footprints can be used for filtering, if desired. A simple RC filter made up of 22 Ω and 2700 pF NPO capacitors is provided. Note that the use of stable dielectric capacitors, such as NPO or COG, is required in the analog signal path to preserve the ADAS3022 distortion. Using X5R or other capacitors in the analog signal path greatly reduces the performance of the system. Also, note that many bench top arbitrary waveform generators (AWGs) use 12-bit or 14-bit digital-to-analog converter outputs such that the 16-bit ADAS3022 devices digitize this directly resulting in erroneous looking data. If such an AWG is used, a high-order band-pass filter should be used to filter the unwanted noise from these sources.

The ADAS3022 COM input can be routed to P1 or GND using P31. Set the jumper across Pin 1 and Pin 2 to route to P1. Set the jumper across Pin 2 to Pin 3 to GND COM. This is useful for single-ended applications.

For dynamic performance, an FFT test can be done by applying a very low distortion ac source, such as an Audio Precision System 2702. This source can be set for balanced or unbalanced, and can be floated or grounded depending on the user’s choice.















Rev. A | of 32

FPGA The on-board FPGA performs a number of digital functions, one of them being the sample rate conversion controlled using the software. Another function is deserializing the serial conversion results as the CED data capture board uses a 16-bit parallel interface. If desired, the deserialized data can be monitored on the 96-pin edge connecter P1, BD[15:0]. The CED uses a buffered busy signal, BBUSY, as the general interrupt for the data transfer to the CED board.

The FPGA also provides the necessary ADAS3022 asynchron-ous control signals for RESET and power down (PD).

The signals from the FPGA to the ADAS3022 can be bypassed by modifying the default solder pad connections. As shown in Figure 2, each digital signal on the ADAS3022 is connected to the larger (top) pad of the three. The default configuration is the small pad and larger pad (no text) which connects the FPGA to the ADAS3022 (CNV, BUSY, and SDO signals shown). The labeled pads, CNV_I, BUSY_I, SDO_I, and so on, are the signals that are routed to P3. To use P3 instead of the FPGA, unsolder the default connections and resolder from the large pad to the xxx_I pads. The FPGA will remain powered; however, if all the signals are bypassed in this fashion, it will not have any influence on the ADAS3022.

Figure 2. Digital Interface Solder Pads—Partial View

Serial Interface

The 4-wire serial interface consisting of CS, DIN, SCK, and SDO is present on the digital interface test points and is controlled by the FPGA. The FPGA can be bypassed by using the solder pads.

REFERENCE The ADAS3022 has an internal 4.096 V reference, along with an internal buffer, useful for using an external reference or one can use an external 4.096 V reference directly, such as the ADR434 provided on the evaluation board. The evaluation board can be configured to use any of these references. Two jumpers (P5 and P9) are used for setting the reference in conjunction with software control.

External Reference–Factory Configuration

The evaluation board includes the ADR434, A1, which is a 4.096 V precision voltage reference. This reference can drive the ADC REF1 or REF2 (REFx) pin directly or it can also be buffered with U20, the AD8032; both of these are set to the factory default setting.

Table 2. Factory Reference Jumper Configuration

Jumper Setting

P5 REFIN to GND1

P9 REF to BUF (U20) 1 The connection is made through R102 = 10 k to GND.

To use another reference source, there are two methods:

• For an external unbuffered reference, remove the P9 jumper and connect a source to the REF test point.

• Since the ADR434 is a standard 8-lead SOIC, it can also be removed and replaced with the user’s reference. In this case, the user reference and the U20 AD8032 buffer can be used as a reference source.

Internal 4.096 V Reference

The ADC has an internal 4.096 V precision reference and can be used on most applications. When enabled, 4.096 V will be present on the ADAS3022 REFx pin and test point, REF. In addition, a voltage will also be present on the ADAS3022 REFIN pin and test point, REFIN. The voltage present on REFIN can be used for other purposes, such as to provide the bias voltage; however, it would need a suitable buffer as the output impedance of the REFIN is on the order of a few kilo ohms and loading this voltage down will degrade the internal reference’s performance.

Table 3. Internal Reference Jumper Configuration

Jumper Setting

P5 Open

P9 Open

Note that the ADAS3022 configuration register needs to be updated either using the included software or by writing the appropriate bits to enable the internal reference.

Internal Reference Buffer

The internal reference buffer is useful when using an external 2.5 V reference. When using the internal reference buffer, applying 2.5 V to REFIN, which is directly connected to the ADC’s REFIN pin, produces 4.096 V at the ADCs REFx pin and REF test point.

Note that the ADAS3022 configuration register needs to be updated either using the included software or by writing the appropriate bits to enable the internal reference buffer.

DEFAULT

CONNECTION TO P3

1106

4-00

3

















Rev. A | of 32

POWER SUPPLIES AND GROUNDING The on-board ADP3334 low dropout regulators are provided for 2.5 V, 3.3 V, and 5 V and also for the FPGA I/O supply which is user configurable and set to 3.3 V by default. The FPGA core is supplied by a pair of ADP1715 devices set for 1.2 V. Additional power is supplies via the CED board for an alternative +5 V analog and digital 3.3 V/5 V digital through P4.

The ADAS3022 device also requires ±15 V supplies for VDDH and VSSH. These must be supplied by the user using a standard lab supply ensuring that the return paths are at the same potential. Refer to CN-0201 for the complete information on generating these ±15 V supplies from a +5 V single supply. The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and VSSH). In other words, the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies.

The evaluation board ground plane consists of a solid plane on one PCB layer shared on another layer with the power plane. To attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths, that is, all analog on one side and digital on the other.

EVALUATION BOARD SCHEMATICS/PCB LAYOUT The evaluation board is a 6-layer board carefully laid out and tested to demonstrate the specific high accuracy performance

of the ADAS3022 devices. The Evaluation Board Schematics and Artwork section of this user guide shows the schematics of the evaluation board.

BASIC HARDWARE SETUP The ADAS3022 evaluation board connects to the EVAL-CED1Z converter evaluation and demonstration board. The EVAL-CED1Z board is the controller board, which is the communi-cation link between the PC and the main evaluation board.

Figure 3 shows a photograph of the connections made between the ADAS3022 daughter board and the EVAL-CED1Z board.

1. Before connecting power, ensure that the EVAL-ADAS3022EDZ and the EVAL-CED1Z boards are connected firmly together.

2. Connect the power supplies on the EVAL-ADAS3022EDZ board. The EVAL-ADAS3022EDZ requires external power supplies of ±15 V. Connect them from a bench top power supply.

3. Connect the EVAL-CED1Z board to the PC via the USB cable enclosed in the EVAL-SDPCB1Z kit. If using a Windows® XP platform, you may need to search for the EVAL-CED1Z drivers. Choose to automatically search for the drivers for the EVAL-CED1Z board if prompted by the operating system.

4. Proceed to the Software Installation section to install the software. Note that the EVAL-CED1Z board must not be connected to the PC’s USB port until the software is installed. The 7 V dc supply can be connected, however, to check that the board has power (green LED lit).

Figure 3. Hardware Configuration—Setting up the EVAL-ADAS3022EDZ

SIGNAL SOURCEEVAL-ADAS3022EDZ

EVAL-CED1Z

USB

TO WALL WART

PC

1106

4-00

2

http://www.analog.com/adp3334?doc=ug-484.pdf

http://www.analog.com/adp1715?doc=UG-484.pdf


http://www.analog.com/cn-0201?doc=ug-484.pdf



















Rev. A | of 32

JUMPERS AND TEST POINTS Three-pin jumpers are used to configure the ADC reference. Refer to the Reference section for further details and settings.

Table 4. Pin Jumper Descriptions Jumper Default Function P5 REFIN to

GND REFIN Select. Buffered reference input selection. Use in conjunction with P7. Note that the ADAS3022 REFx pin and any other circuit traces/test points will produce 4.096 V when using the buffered reference configuration; P7 must be left in the open position.

REFIN to A2: Uses the on-board ADR381, A2 (2.5 V) reference. The ADAS3022 must use the buffered reference configuration.

REFIN to GND: Disables the ADAS3022 internal reference. The ADAS3022 must use the full external reference configuration.

Open: For use either when using the ADAS3022 on-chip reference or when applying an external 2.5 V source. When using the on chip reference, a voltage is present on Pin 2 and any other circuit traces/test points. When using an external source, the ADAS3022 must use the buffered reference configuration.

P7 REF to BUF

REF Select. External 4.096 V reference input selection. Use in conjunction with P5. Note that the ADAS3022 REFIN pin and any other circuit traces/test points produce 2.5 V when using the internal or external reference configuration and P5 must be left in the open position.

REF to A1: Uses the on-board ADR434, A1 (4.096 V), reference. The ADAS3022 must use the external reference configuration.

REF to BUF: Uses the on-board ADR434 followed by the AD8032, U20 unity gain buffer. This allows some adjustment to the reference voltage by use of some resistors around the AD8032. The ADAS3022 must use the external reference configuration.

Open: For use when using the ADAS3022 on-chip reference or an externally applied source connected directly to Pin 2 or the REF test point.

P31 COM to PIN 1

COM Input Select. Center pin connected to ADAS3022 COM pin. Center pin to PIN1 routes COM to P1. Center to PIN3 routes COM to GND.

Solder pads jumpers are factory configured and can be changed by the user.

Table 5. Analog and Digital Solder Pads Descriptions Jumper Name Default Function P9 SDO 1 to 3 SDO Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P34. P16 DIN 1 to 3 DIN Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P35. P17 CNV 1 to 3 CNV Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P36. P18 SCK 1 to 3 SCK Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P33. P19 BUSY 1 to 3 BUSY Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P37. P27 RESET 1 to 3 RESET Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P38. P28 PD 1 to 3 PD Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P39. P29 CS 1 to 3 CS Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P40.

P25 DSPCLK Soldered CED Clock Source.


http://www.analog.com/adr381?doc=ug-484.pdf
















Rev. A | of 32

Table 6. Power Supply Solder Pads Jumper Name Default Function P6 VDDH Soldered VDDH Supply. P13 VSSH Soldered VSSH Supply. P8 AVDD +5VA AVDD Supply. Selection of +5 V A, analog supply from the CED board or +5 V from U3. P10 – Soldered VIO Supply. This solder pad can be used to power the FPGA VIO and ADAS3022 VIO together. P11 – Soldered FPGA VIO Supply. Supplied from U8, 3.3 V, dedicated digital supply. P12 VIO Open VIO Supply. Selection of 2.5 V (2V5), 3.3 V (3V3), or DVDD (5V). Note that the ADAS3022 digital outputs are set to

this level and are directly wired to the FPGA, U6, which is 3.3 V max. When using the 5 V setting, the ADAS3022 outputs, SDO and BUSY must be resistively divided using the 0603 pads provided on the evaluation board. For this reason, P10 is used as the default.

P14 DVDD +5VD DVDD Supply. Selection of +5 V digital, +5 V D, and +5 V from U3. P15 VDRV- −5VA U20 V−/P34 Supply. Selection of −5 V A, analog supply from the CED board or GND. P33 VDRV+ +5VA U20 V+/P35 Supply. Selection of +5 V A, analog supply from the CED board or +5 V from U3. P34 U4 V+ VDRV+ U4 V+ Supply. Selection of VDRV+ or U2. P35 U4 V− VDRV− U4 V− Supply. Selection of VDRV− or GND. P22 −15V Soldered −15 V CED Supply. P23 −5VA Soldered −5 V A (Analog) CED Supply. P24 +5VA Soldered +5 V A (Analog) CED Supply. P26 +5VD Soldered +5 V D (Digital) CED Supply. P30 +15V Soldered +15 V (Analog) CED Supply.

Table 7. Test Points (By Signal Type) Test Point Type Description IN0_I Analog Input Path for IN0 Input. IN1_I Analog Input Path for IN1 Input. IN2_I Analog Input Path for IN2 Input. IN3_I Analog Input Path for IN3 Input. IN4_I Analog Input Path for IN4 Input. IN5_I Analog Input Path for IN5 Input. IN6_I Analog Input Path for IN6 Input. IN7_I Analog Input Path for IN7 Input. COM_I Analog Input Path for COM Input. REF Analog Input Direct Connection to ADAS3022 REFx Pin. REFIN Analog Input Direct Connection to ADAS3022 REFIN Pin. CNV Digital Input Direct Connection to ADAS3022 CNV Pin. BUSY Digital Output Direct Connection to ADAS3022 BUSY Pin. SDO Digital Output Direct Connection to ADAS3022 SDO Pin. SCK Digital Input Direct Connection to ADAS3022 SCK Pin. PD Digital Input Direct Connection to ADAS3022 PD Pin. RESET Digital Input Direct Connection to ADAS3022 RESET Pin. DIN Digital Input Direct Connection to ADAS3022 DIN Pin. CSB Digital Input Direct Connection to ADAS3022 CS Pin.

MSCL Digital Output Eval Board Master Clock Form Y3, 100 MHz Oscillator. VDDH Power Direct Connection to ADAS3022 VDDH Pin. VSSH Power Direct Connection to ADAS3022 VSSH Pin. AVDD Power Direct Connection to ADAS3022 AVDD Pin. DVDD Power Direct Connection to ADAS3022 DVDD Pin. VIO Power Direct Connection to ADAS3022 VIO Pin. +5VA Power Connected to P24; CED +5 V A. −5VA Power Connected to P23; CED −5 V A. +15V Power Connected to P30; CED +5 V A. −15V Power Connected to P22; CED −5 V A. +5VD Power Connected to P26; CED +5 V D. GND(s) Power Connected to Eval Board GND Plane.




















Rev. A | of 32

EVALUATION BOARD SOFTWARE SOFTWARE INSTALLATION Close major Windows applications prior to installing the software.

System Requirements

• Windows XP (SP2, 32-bit), Windows Vista (32-bit or 64-bit), or Windows 7 (32-bit or 64-bit)

• USB 2.0 (for CED board) • Administrator privileges

Website Download

The evaluation board software is available for download from the evaluation board page on Analog Devices website. Click the setup.exe file to run the install. The default location for the software is C:\Program Files (x86)\Analog Devices\ ADAS3022 Evaluation Software.

Install the evaluation software before connecting the evaluation board and EVAL-CED1Z board to the USB port of the PC to ensure that the evaluation system is correctly recognized when connected to the PC.

There are two parts of the software installation process:

• ADAS3022 evaluation board software installation • EVAL-CED1Z board driver installation Figure 4 to Figure 9 show the separate steps to install the ADAS3022 evaluation software, while Figure 10 to Figure 12 show the separate steps to install the EVAL-CED1Z drivers. Proceed through all of the installation steps to allow the soft-ware and drivers to be placed in the appropriate locations. Only connect the EVAL-CED1Z board to the PC after the software and drivers are installed.

Figure 4. ADAS3022 Evaluation Software Installer

Figure 5. ADAS3022 Evaluation Software Destination Directory

Figure 6. ADAS3022 Evaluation Software License Agreement

Figure 7. ADAS3022 Evaluation Software Start Installation

1106

4-10

4

1106

4-10

511

064-

106

1106

4-10

7












Rev. A | of 32

Figure 8. ADAS3022 Evaluation Software, Installation In Progress

Figure 9. ADAS3022 Evaluation Software Installer, Installation Complete

Figure 10. CED Drivers Install Setup Wizard

Figure 11. CED Drivers Install Setup Wizard, Installation In Progress

Figure 12. CED Drivers Install Setup Wizard, Installation Completed

Figure 13. Computer Restart Notice

1106

4-10

811

064-

109

1106

4-11

0

1106

4-11

111

064-

112

1106

4-11

3




Rev. A | of 32

On some PCs, the Found New Hardware Wizard may show up. If so, follow the same procedure to install it properly.

The Device Manager can be used to verify that the driver was installed successfully.

Figure 14. Device Manager

Troubleshooting the Installation

If the driver was not installed successfully, the Device Manager displays a question mark for Other devices because Windows does not recognize the EVAL-CED1Z board.

Figure 15. Device Manager Troubleshooting

The USB Device can be opened to view the uninstalled properties.

Figure 16. USB Device Properties

This is usually the case if the software and drivers were installed by a user without administrator privileges. If so, log on as an administrator with full privileges and reinstall the software.

1106

4-00

6

1106

4-00

7

1106

4-00

8



Rev. A | of 32

POWERING UP THE BOARD The evaluation board, as configured from the factory, uses the local LDOs for power where necessary. A ±15 V dc lab supply must be connected to the board. Test points (yellow and white) are provided for these external supplies.

Figure 17. Test Points

RUNNING THE SOFTWARE WITH THE HARDWARE CONNECTED The evaluation board includes software for analyzing the ADAS3022. The EVAL-CED1Z is required when using the software. The software is used to perform the following tests:

• Histogram tests for determining code transition noise (dc) • Time domain analysis • Fast Fourier transforms (FFT) for signal-to-noise ratio

(SNR), SNR and distortion (SINAD), total harmonic distortion (THD), and spurious free dynamic range (SFDR)

This evaluation software should be located at <local_drive>:\Program Files\Analog Devices\ADAS3022 Evaluation Software.

In order to launch the software, click Start>All Programs> Analog Devices\ADAS3022 Evaluation Software. You can then apply the signal source and capture the data.

To uninstall the program, click Start>Control Panel>Add or Remove Programs>Analog Devices ADAS3022 Evaluation Software.

Refer to Figure 18 to Figure 31 for further details and features of the software.

1106

4-00

9




Rev. A | of 32

SOFTWARE OPERATION This section describes the full software operation and all windows that appear. When the software is launched, the panel opens and the software searches for hardware connected to the PC. The user software panel launches, as shown in Figure 18. The labels listed in this section correspond to the numbered labels in Figure 18.

File Menu (Label 1)

The File menu, labeled 1 in Figure 18, provides the following: • Save Captured Data saves data to a .csv file. • Take Screenshot saves the current screen. • Print prints the window to the default printer. • Exit quits the application.

Edit Menu (Label 2)

The Edit menu, labeled 2, provides the following:

• Initialize to Default Values: This option resets the software to its initial state.

Help Menu (Label 3)

The Help menu, labeled 3, offers help from the following sources:

• Analog Devices website • User Guide • Context Help • About

Throughput (Label 4)

The default throughput (sampling frequency) is 1,000 samples per second (SPS). The ADAS3022 is capable of operating a maximum sample frequency up to 1,000 kSPS.

Samples (Label 5)

Select the number of Samples to analyze when running the software. This number is limited to 65,536 samples.

Single Capture (Label 6) and Continuous Capture (Label 7)

Single Capture performs a single capture, whereas Continuous Capture performs a continuous capture from the ADC.

Tabs

There are four tabs available for displaying the data in different formats.

• Time Domain • Histogram • Spectrum • Summary

To exit the software, go to File>Exit.

Figure 18. Setup Screen

1106

4-11

8

8

1 2 3

4

5 6 7

9 10

11

12



Rev. A | of 32

Figure 19. Dialogue Box for Label 8, MUX Settings

Figure 20. Dialogue Box for Label 8, Input Channel Options

Figure 21. Dialogue Box for Label 8, Alternate Input Channel Options

Figure 22. Dialogue Box for Label 8, Sequence Options

Figure 23. Dialogue Box for Label 8, Advanced Sequencer PGIA Gain

Configuration

Figure 24. Dialogue Box for Label 9, PGIA Settings

Figure 25. Dialogue Box for Label 10, AUX/MUX Settings

Figure 26. Dialogue Box for Label 11, Conversion Mode Settings

Figure 27. Dialogue Box for Label 12, Reference Settings

1106

4-11

911

064-

120

1106

4-12

111

064-

122

1106

4-12

311

064-

124

1106

4-12

511

064-

126

1106

4-12

7


Rev. A | of 32

Start Up Refer to the numbered labels in Figure 18. Clicking the blue buttons reveals the dialog boxes shown in Figure 19 through Figure 27.

To begin evaluating the device, the on-board supplies must be enabled.

• RESET resets the ADAS3022 device to a known state. Click RESET twice: once to reset the ADAS3022 and again to bring it out of the reset state. Note that the CFG is also reset to the default condition.

• Reference Selection: At this time, it is recommended to use the evaluation board’s externally generated reference (default). To select the on-chip reference, remove the P5 and P7 jumpers and click the button in the REF block to display the Reference Settings dialog box, then choose REFERENCE ENABLED.

• Auxiliary (AUX±) Channels Selection: The ADAS3022 allows the user to run it in default MUX ONLY mode or by clicking on it to select the auxiliary channel input pair (AUX+, AUX−) IN0−INX AUX in normal mode or sequencer mode. The IN0−INX AUX option converts a dedicated channel through the internal differential auxiliary channel pair (AUX+, AUX−) with the specified input range of ±VREF. This option bypasses the MUX and programmable gain instrumen-tation amplifier stage, allowing direct access to the SAR ADC core.

• Update CFG: If the default configuration (channel, chan-nel configuration, reference, and so on) is acceptable, clicking Update CFG writes to the ADAS3022 con-figuration register (CFG). The ADAS3022 device is configurable using a 16-bit on-chip register, CFG (refer to the ADAS3022 data sheet for more details). Note that after changing any of the CFG register, this button must be clicked for the new setting to take effect.

Input Channel

To select the input channel, make a selection from the pull-down menu (see Figure 20).

Channel Pairing The channels can be paired (up to 4 maximum) or all channels can be referenced to the COM input (see Figure 21).

Programmable Gain The most useful and innovative feature of the ADAS3022 is the on-chip programmable gain instrumentation amplifier. This amplifier has the added flexibility of allowing for inputs ranging from ±0.64 V to ±24.574 V. Select the appropriate setting for the input voltage span, not including any common-mode signals, since they are rejected. Note that the ADAS3022 devices do not need the usual level shifting that is common in SAR ADC systems. The ADAS3022 devices can accommodate fully differential, single ended, and bipolar input signal types.

Software Controls Within any of the chart panels, these controls are used to control the display.

Controls the cursor.

Controls zooming in and out.

Controls panning.











Rev. A | of 32

TIME DOMAIN TAB Figure 28 illustrates the Time Domain tab. The ADAS3022 output is twos complement output; however, the software outputs the results in straight binary.

Note that Label 1 shows the Waveform Analysis that reports the amplitude recorded from the captured signal in addition to the frequency of the signal tone, and Label 2 shows that Y-axis units can be displayed in volts or code (LSB).

Figure 28. Time Domain Tab

1106

4-13

1

12



Rev. A | of 32

HISTOGRAM TAB The histogram is most often used for dc testing or ac testing, where a user tests the ADC for the code distribution for dc input and computes the mean and standard deviation, or transition noise, of the converter, and displays the results. Raw data is captured and passed to the PC for statistical computations. Figure 29 shows the Histogram tab.

To perform a histogram test,

1. Select the Histogram tab.

2. Click Single Capture or Continuous Capture.

DC Testing

To test other dc values, apply a source to the selected analog inputs IN[7:0]_I via test points or P1. It may be required to

filter the signal to make the dc source noise compatible with that of the ADC. Note that 0805 and 0603 SMT pads are provided in each signal path and can be used for filtering the source, if necessary.

AC Testing

Figure 29 shows the histogram for a 1 kHz sine wave applied to the analog inputs IN[7:0]_I via test points or P1 from a quality precision signal source, such as Audio Precision. It may be required to filter the input signal from the ac source. There is no suggested band-pass filter, but consider all choices carefully. The Waveform Analysis (Label 1) chart displays the various measured histogram values for the ADAS3022.

Figure 29. Histogram Tab

1106

4-12

81



Rev. A | of 32

SPECTRUM TAB Figure 30 shows the FFT spectrum capture tab. This tab tests the traditional ac characteristics of the converter and displays a fast Fourier transform (FFT) of the results. As in the histogram test, raw data is captured and passed to the PC where the FFT is performed, displaying SNR, SINAD, THD, and SFDR.

To perform an ac test, apply a sinusoidal signal to the evaluation board to any of the analog inputs IN[7:0]_I, either via test points or P1. Very low distortion—a better than 130 dB input signal source, such as Audio Precision)—is required to allow true evaluation of the part. One possibility is to filter the input

signal from the ac source. There is no suggested band-pass filter, but carefully consider the choices. Figure 30 displays the results of the captured data.

• The top part of the image displays the FFT results including SNR, dynamic range, THD, SINAD, and noise performance (see Label 1).

• The lower part of the image displays the fundamental frequency and amplitude in addition to the 2nd to 5th harmonics (see Label 2).

Figure 30. FFT Spectrum with FFT Results (Top) and with Spectrum Analysis Results (Bottom)

1106

4-12

9


Rev. A | of 32

SUMMARY TAB Figure 31 shows the Summary tab, which summarizes all the data capture information and displays it in one panel with a synopsis of the information, including key performance parameters such as SNR, THD, and SINAD.

Figure 31. Summary Tab

11

064-

132


Rev. A | of 32

EVALUATION BOARD SCHEMATICS AND ARTWORK

Figure 32. Schematic, DUT, Analog

DU

T C

IRC

UIT

S

DO

NO

T IN

STA

LL IF

VEE

= G

ND

REF

DEC

OU

PLIN

G

PLA

CE

CLO

SE T

O T

HE

DU

T

SUPP

LY D

ECO

UPL

ING

AU

XPA

RTF

OO

TPR

INT

21C

61

21C

64

21C

4821

C54

21C

52

21C

5

21C

221

C58

98765

484746454443424140

4

393837

36 35 34 33 32 31 30

3

29 28 27 26 25

2423222120

2

19181716151413

1211101

U9

1D

CA

P1

AC

AP

1R

CA

P

C82

54

32

1C

OM

54

32

1IN

1

54

32

1IN

0

321P3

5321P3

4

NPC

89

R95

R80

NPC

84C

45

C81

C80

C79

C68

C67

C66

C47

C96

R79

321P3

148

U4

132

U4

756

U4R88

R84

R87

R38

R54

R52

R53

R33

R58

R94

C56

C55

R50

R51 R

34

R35

R36

R37

R38

R39

R40

R71

R63

R61

R65

R67

R64

R68

R66

R62

R60

1CO

M_2

1IN7

1IN6

1IN5

1IN4

1IN3

1IN2

1IN1_

2

1IN0_

2

R81

R85

C93

R82

C94

R86

1A

UX–

I

1A

UX+

I

C38

C92

1C

OM

_I1IN

7_I

1IN

6_I

1IN

5_I

1IN

4_I

1IN

3_I

1IN

2_I

1IN

1_I

1IN

0_I

9876543 262524232221202 191817161514131211101P1

C41

C44

C42

4321P20

R2

R49

R48

R47

C50

C10

C49

C47

R46R

45

R44

R43

C53

C51

C46

C63

C4

C3

C62

C60

C59

R42

R41

C1

C57

C77

C72

C76

C71

C75

C70

C78

C73

C65

PAD

98765

40

4

393837363534333231

30

329 28 27 26 25 24 23 22 21

20

2

191817161514131211

101

U7

2700

pF

DN

ITB

D08

05D

NI

TBD

0805

TBD

0805

DN

I

TBD

0805

DN

I

TBD

0805

DN

I

TBD

0805

DN

I90.9Ω

90.9Ω

TBD

0805

IN1

DN

I

IN4

DN

ITB

D08

05

50Ω

2700

pF

2700

pF

90.Ω9

2700

pFD

NI

0Ω90.9Ω

90.9Ω

2700

pF

2700

pF

90.9Ω

2700

pFIN

7C

OM

IN4

AU

X+

0

2700

pF

RES

ET

AD

AS3

XXX

PSTR

NK

PE41

17

IN2

CH

0I

DN

I

2700

pF

2700

pF

2700

pF

RCAP

DCAP

YEL

YEL

DN

I

DN

I

DN

I

DN

I

DN

I

DN

I

DN

I

DN

I

DN

I

50Ω

BLU

50Ω

CO

MI

CH

4I

AU

X+I

AD

A48

41-2

YRZ

499Ω

VDR

V–

TBD0805

DN

I

22Ω

R57 22Ω

2700

pF

DN

I

TBD

0805

AM

PVC

CA

UX_

AM

PVC

CVD

RV+

AM

PVEE

10µF

AM

PVEE

0.1µ

F

0.1µ

F

10µF

AM

PVEE

AM

PVC

C

AM

PVC

C

AD

A48

41-2

YRZ

BLU

BLU

TBD

0805

90.9Ω

2700

pF

CH

6I

50Ω

TBD

0805

CH

7I

DN

I

DN

I

50Ω

CH

3I

CO

MI

BLU 50

Ω

BLU

50Ω

2700

pF

2700

pF

AU

X–I

0.1µ

F

0Ω0Ω0Ω0Ω

50Ω

CH

2I

90.9Ω

TBD

0402

VSSH

TBD

0805

DN

I

DN

I

499Ω

AD

A48

41-2

YRZ

TBD0805

499Ω TB

D08

05

BLU

499Ω

VCM

_AU

X

499Ω

TBD

0805

499Ω

VCM

_AU

X

499Ω

TBD

0805

TBD

0805B

LU

499Ω

AU

X+I

AU

X–I

0.1µ

F

TBD

0603

TBD

0603

TBD

0603

0.1µ

F0.

1µF

0.1µ

F

0.1µ

F

0.1µ

F

0.1µ

F

DCAP

DVDD

AVD

D

AC

AP

VIO

RC

AP10

µF10

µF0.

1µF

0.1µ

F0.

1µF

REF

INR

EFR

EF

IN2

IN6

IN5 CSB

DIN

SCK

VIO

SDO

BU

SY_A

UX

CN

V

RC

AP

REF

IN

VDD

HVS

SH

AC

AP

TBD

0603

4PJU

MPE

R

REFINRCAP

AVD

DD

VDD

AC

AP

DC

AP

CNVBUSY_AUX

SDOVIO

SCKPD

DIG1RESET

DINCSB

CO

MIN

7IN

6IN

5IN

4A

UX+IN

3IN

2IN

1IN

0

GEN

_48L

QFP

REF

AUX–VDDHVSSH

3M30

326-

6002

HB

BLU

0ΩD

IG1

BLU

CH

5I

50Ω

0Ω

2700

pF

YEL

ACAP

REF

AU

X–

IN1

+2.5

VD

CA

P

IN3

TBD

0805

PD

49Ω9

2700pF

TBD

0805

CH

0I

0

BLU

CH

1I

PSTR

NK

PE41

17PS

TRN

KPE

4117

BLU

IN5

IN6

IN7

CO

M

IN3

CH

1I

90.9Ω

IN0

AVD

DD

VDD

GEN

_QFN

40_6

X6_P

AD

TBD

0603

TBD

0603

TBD0603TBD0603

IN0

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

V–V+

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

G

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

TBD

0805

2700pF

GN

D

GN

D

CO

MM

ON

MO

DE

CA

P

C91

C43

DN

I

AU

X+

AU

X–

10µF

11064-020


Rev. A | of 32

Figure 33. Schematic, Power

GN

DG

ND

GN

DG

ND

AN

ALO

G S

UPP

LIES

+5VD

-5VA

GN

D+5

VA–1

5V+1

5VG

ND

REG

ULA

TES

FPG

A V

IO S

UPP

LIES

TO

3.3

V (M

AX

ALL

OW

ED)

FPG

A S

UPP

LIES

LDO

AD

JUST

ED T

O1.

2V

LDO

AD

JUST

ED T

O 1

.2V

SUPP

LYO

PTIO

NS

INT

REF

BU

F D

ISA

BLE

D3:

EXTE

RN

AL

4.09

6 R

EFER

ENC

E,1:

EXTE

RN

AL

2.5V

BA

ND

GA

P, IN

T R

EF B

UF

OPE

N: I

NTE

RN

AL

2.5V

BA

ND

GA

PR

EFIN

CO

NN

ECTI

ON

:

EXTE

RN

ALR

EFER

ENC

E

1R

EF38

1_O

UT

1VD

D_R

EF38

1

21

JP1

21

JP2

1G

ND

61

GN

D5

R10

2

1VD

RV-

R98

R96

R97

C85

6 PAD

2187

5

3

U2

C86

R100 R99

C87

R10

1

C88

321P3

3

21

3A2

C23

1VD

RV+

C83

R93

R92

R28

R27

R23

321P5

321

P7

R69

R90

R91

1G

ND

31

GN

D1

1G

ND

2

1VD

DH

1VS

SH

1R

EFIN

1R

EF

321P1

5

1–5

VA

R70

R7

1A

VDD

C40

R29

C39

48U

20

6 57

2 31

U20

R24

R25

R26

4321P1

2

321P1

4

321P8

21

P13

21

P6

C20

C17

R1

C35

R22

C36

62

581

73 4

A1

C37

C7

6 PAD

2187

5

3

U8

R56

C8

R55

C9

1G

ND

1+5

VD1

+15V

1-1

5V1

+5VA

1VI

O

1D

VDD

C14 C15

C16

C13

C12

C11

6 PAD

2187

5

3

U12

C34

C28

C27

C33C32

C26

21

R8

21

R9

21

R19

21

R21

21R

20

21

R12

21

R11

R10

2 1C21

2 1C18 2 1

C19

2 1C22

2 1R182 1R17

2 1R142 1R16

21 R6

32

87

65

1 4

U11

21 R5

21 R4

32

87

65

1 4

U10

2

1

R3

2 1C25

2 1C24

2 1C29

21 R13

6 PAD

2187

5

3

U1

2 1C31

2 1R15

U3

2 1C30

+15V

2.2µF

1000pF

+5V

+15V

TBD

0805

0.1µ

F

BLU

VIO

RED

WH

TR

EDB

LKB

LK

+5VD

–5VA

+5VA

–15V

+15V

10µF

+15V

0Ω

0.1µF

2.2µF

0Ω

0.1µF

2.2µF

AD

P171

5AR

MZ-

R7

1kΩ

2kΩ

2.2µF

1kΩ

AD

P171

5AR

MZ-

R7

2kΩ

2.2µF

2.2µF

140kΩ

1000pF

78.7kΩ

AD

P333

4AC

PZ

2.2µF

+5VD

+5VD

VIO

_FPG

A+5

VD

VFPG

A

VPLL

0kΩ

0Ω

0

VCM

_AU

X

AD

8032

VDR

V+

0Ω 2.2µF

1000pF

TBD0805

0Ω 10kΩ

EN_3

.3V_

N

78.7kΩ140kΩ

AD

P333

4AC

PZ

0Ω

300kΩ

2.2µF

60.4kΩ

1000pF

AD

P333

4AC

PZ

2.2µF

TBD0805

0Ω 10kΩ

AVD

D

VIO

_FPG

A

+2.5

V+3

.3V

VIO

_FPG

A

210kΩ 64.9kΩ

AD

P333

4AC

PZ

2.2µF

2.2µF

2.2µF0Ω

TBD0805

AD

P333

4AC

PZ

1000pF

0Ω

10kΩ

2.2µF

AU

X_A

MPV

CC

EN_5

V_N

BLU

+15V

VDD

H

–15V

AVD

D

10µF

+5VA

+5V

+5VD

+5VD

VDD

10µF

BLU

VDR

V–+5

VA+5

V

BLU

VDR

V+

10µF

+3.3

VD

VDD

–5VA

+15V

VIO

_FPG

A

TBD0805

VSSH

0Ω0Ω

EN_2

P5V_

N

0Ω

10kΩ

10kΩ

+2.5

V YELW

HT

BLK

BLKBLK

BLK

10µF

DNI

REF

IN

AD

8032

TBD

0805

0.1µF

AD

R43

4AR

MZ

REF

TBD080536.5kΩ

RED

DNI2.2µF

AD

8032

59K

AD

R38

1AR

TZ

00

AVD

DR

ED

0.1µF

RED

RED 0.1µF

TBD0805

TBD0805

10µF B

LU 10µF

10µF

BLU

BLU

10

TBD0805

DN

I

TBD0805

0Ω

REF

GN

D

GN

D

GN

D

IN1

IN2

OU

T2

IN2

OU

T2

OU

T1

PAD

FBG

ND

SD_N

GN

D

IN1

OU

T1

PAD

FBG

ND

SD_N

GN

D

GN

DVI

N

VOU

T

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

–VS

+VS

+IN

–IN O

UT

GN

D

GN

D

GN

D

TRIM

VIN

GN

DN

C1

TPN

C2

TP1

VOU

T

IN1

IN2

OU

T1O

UT2

PAD

FBG

ND

SD_N

GN

D

GN

D

IN1

IN2

OU

T1O

UT2

PAD

FBG

ND

SD_N

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

AD

J GN

D

EN INAD

J GN

D

EN IN

OU

T

OU

T

6 PAD

2187

5

3

IN1

IN2

OU

T1O

UT2

PAD

FBG

ND

SD_N

+IN

–IN O

UT

11064-021


Rev. A | of 32

Figure 34. Schematic, FPGA

AD

CO

K

AD

CO

K

BA

NK

_2

BA

NK

_3B

AN

K_1

MC

LK

POW

ER_F

PGA

BA

NK

_4

R103

R74

R89

R14

5

ACC

R1

R30R31

R59

321P2

1

1C

SB

1R

ESET

1PD

1B

USY

1DIG

1

98765

40

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

P3

321

P28

R73

R77R75

321

P19

R78

321

P29

R72

R76

321

P27

321

P17

321

P16

321

P9

R32

321

P18

21

P10

21

P11

R125

1M

CLK

1C

NV

1D

IN

1SC

K

1SD

O

C128

C130

C131

C127

C129

C109C110

R126

C125

C126

C122

C124

C118

C120

C115

C116

C113

C111

C108

R132

R130R128

C10

7

C11

2C

114

21 R13

6

21 R15

0

21 R13

7

21 R15

1

R14

4

R14

3

R14

2

R14

1

R14

0

R13

9

R13

8

21 R13

4

21 R12

2

21 R12

1

21 R13

5

ACC

R2

98765432 101P2

8

73

1

4

62

5

U5

43

2

1

Y3

T15T2P10P7M10M7R16K14G14B16E10E7C10C7A15A2R1K3G3B1J7H10H7G9

C8B15B2

A16A1J8H9K9J9

T16T1

R15R2P9H8P8M9M8J14J3

H14H3E9E8C9G8

U6

L6

G1

G2

H5

F2J5G5

D3

E4E3E5D5

C2

M4L4C1P3P2P1L3N2

N1

M3

M2J4L2F4L1M1K5

K4

K1K2

E2E1F3D4

C3

N5L

5

H4

F1J1J2H1

H2

U6

E12

F6E6B3A3A4B4A5B5C4C5C6D6G7G6A6B6D8F8F7B7A7A8B9A9D10D11F9F10A10B10G11G10C11A11A12B12B11A13B13C12C13A14B14

E11

U6

F11

M13

K12J13

G13

G12

H11

J11

F16

F15

G15

G16

J12

H12

K15

K16

L16

L15

L14

M14

M16

M15

N16

N15

P16

P15

P14

N14

N13

M12

N12

D14

E14

D13

C14

E16

D16

D15

H13

D12

F12

L13

J16

J15

H15

H16

U6

M5

L11M11R14T14R13T13L12R12T12P13P12N11K10K11T10R10L10L9

P11R11T11N10N9R9T9R8T8L8L7R7T7N8T6R5T5R4T4P4P5T3R3

M6

U6

VIO

_FPG

A

0.1µF

0.1µF

EP2C5F256C7N

OH_D15

OH_D13OH_D12

OH_D9OH_D8

OH_D5OH_D4OH_D3OH_D2OH_D1OH_D0

LA_C

LK1

LA_CLK2

OH_D14OH_D15

LA_CLK1

OH_D13OH_D12OH_D11OH_D10

LA_C

LK2

OH_D11

OH_D7

EP2C

5F25

6C7N

BU

SY_A

UX

BU

SY_A

UX

CO

NTR

OL

BR

ESET

DSP

CLK

10kΩ

10kΩ

PS_C

ON

FIG

_N

RES

ET

DNI DNI

3M25

10-5

002U

B

VIO

TBD0603DNI

VIO

TBD0603DNI

DNI10kΩ

DNI

EN_3

.3V_

NEN

_5V_

N

MC

LK

10kΩ

DIN

EN_2

P5V_

N

10kΩ

VIO

DNI10kΩ

VIO

_FPG

AA

DC

OK

604Ω

PLLO

K604Ω

BR

ESET

BW

R_N

BD

<11>

SCK

OH_D7OH_D6

PS_C

DO

NE_

N10kΩ

VIO

_FPG

A

OH_D6

VPLL

OH_D10

OH_D14

CN

V

0Ω

VIO

DNI15kΩ

SDO

15kΩDNI

10kΩ

TBD0603VI

O

0Ω0Ω

0Ω0Ω

GN

DA

SDO

N_C

SOD

ATA

PS_S

TATU

S_N

GN

DPS

_DC

LK

VIO

_FPG

A

10kΩ

BLU

CN

V_I

CSB

RES

ET

PD

BLU

SDO

BLU

BLU

DIN

SCK

BLU

BLU

3M25

40-6

002U

B

RES

ET_I

DNI

DNI

BD

<15>

10kΩ

BC

S_N

VIO

_FPG

A

BW

R_N

BR

D_N

BB

USY

VIO

_FPG

AVI

O_F

PGA

MSE

L0M

SEL1

10kΩ

10kΩ

10kΩ

10kΩ

10kΩ

VIO

_FPG

A10

0MH

ZYE

L

ASD

OPS

_DC

LKD

ATA

N_C

SO

VIO

_FPG

A

10kΩ10kΩ10kΩ

PS_C

DO

NE_

N

VPLL

VPLL

VIO

ASD

O

DA

TA

VFPGA

VCCIO1

MSE

L1

10kΩ

VFPG

A

PS_D

CLK

VIO_FPGA

MC

LK

VIO

_FPG

A

EP2C5F256C7N

EP2C

5F25

6C7N

VCC

IO1

VPLL

BD

<4>

BD

<3>

BD

<0>

BD

<1>

BD

<2>

BD

<5>

BD

<6>

BD

<7>

BD

<9>

BD

<10>

BD

<12>

BD

<13>

BD

<8>

AD

<2>

AD

<3>

AD

<0>

AD

<1>

AD

<4>

BR

D_N

CO

NTR

OL

BB

USY

BC

S_N

BD

<14>

DSP

CLK

MSE

L0

CSBPD

BU

SY_I

PD_I

CSB

_I

VIO

_FPG

A

PS_S

TATU

S_N

PS_C

ON

FIG

_N

VIO

TBD0603

0Ω

0Ω

100p

F

CN

VB

LU

OH_D5OH_D4

OH_D1OH_D2OH_D3

BLU

DIG

1

SDO

_I

DIN

_I

N_C

SO

AD

CO

KPL

LOK

CLAMP_EN

OH_D0

RESET_IBUSY_ICNV_IDIN_ISDO_ISCK_I

CSB_IPD_I

OH_D9OH_D8

0.1µF 0.1µF

0.1µF

0.1µ

F0.

1µF

0.1µ

F0.

1µF

0.1µ

F0.

1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

1000pF 1000pF

EP2C

5F25

6C7N

0.1µF

0.1µF

EPC

S4SI

8N

SCK

_I

VCC

IO4

VCC

IO3

VCC

IO2

VCC

IO1

VCC

INT

GN

D

VCC

D_P

LL1

TDO

TMS

TDI

TCK

NC

ON

FIG

NC

E

DC

LKD

ATA

0C

LK3

CLK

2C

LK1

CLK

0

GN

D_P

LL1

IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VCCA_PLL2

GNDA_PLL2IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

GN

D

ASD

ID

CLKVC

C DA

TAnC

S

GN

D

GN

D

GN

D

V+

GN

DOU

TEN

GN

D

GN

D

GN

DGN

D

VCC

D_P

LL2

MSE

L1M

SEL0

CLK

7C

LK6

CLK

5C

LK4 G

ND

_PLL

2N

STA

TUSIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

CO

NF_

DO

NE

VCCA_PLL1

GNDA_PLL1 IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

C12

3C

121

C11

9C

117

11064-022


Rev. A | of 32

Figure 35. Schematic, 96-Pin Interface

Figure 36. Silkscreen, Top

1

BBUSY

1

BCS_N

1

BWR_N

1

CONTROL

1

BRESET

1

BRD_N

21P2

5

21P3

0

21P2

6

21P2

4

21P2

3

21P2

2A9A8A7A6A5A4

A32A31A30

A3

A29A28A27A26A25A24A23A22A21A20

A2

A19A18A17A16A15A14A13A12A11A10

A1P4

B9B8B7B6B5B4

B32B31B30

B3

B29B28B27B26B25B24B23B22B21B20

B2

B19B18B17B16B15B14B13B12B11B10

B1P4

C9C8C7C6C5C4

C32C31C30

C3

C29C28C27C26C25C24C23C22C21C20

C2

C19C18C17C16C15C14C13C12C11C10

C1P4

+15V_CED

AD<1>

BRD_NVDIG

–15V-5VA+5VA

+15V

ERNI533402

+5VA_CED–5VA_CED

+5VA_CED–5VA_CED

BD<6>BD<7>

BD<5>VDIG

BD<11>BD<13>

BD<10>BD<9>BD<8>

BD<4>BD<3>

BD<1>BD<0>

ERNI533402

AD<3>

BD<12>DSPCLK

+5VA_CED–5VA_CED

ERNI533402

AD<4>AD<2>AD<0>

BD<14>BD<15>

VDIG

CONTROL

BWR_NBCS_N

BBUSY

+5VD

BD<2>

DSPCLK_CED

BRESET

GNDGNDGND

1106

4-02

3

1106

4-03

0


Rev. A | of 32

Figure 37. Silkscreen, Bottom

Figure 38. Top Layer 1

1106

4-03

111

064-

024


Rev. A | of 32

Figure 39. GND Layer 2

Figure 40. Signal Layer 3

1106

4-02

511

064-

026


Rev. A | of 32

Figure 41. Signal Layer 4

Figure 42. Power Layer 5

1106

4-02

711

064-

028


Rev. A | of 32

Figure 43. Bottom Layer 6

1106

4-02

9


Rev. A | of 32

PRODUCTS ON THIS EVALUATION BOARD BILL OF MATERIALS

Table 8.

Qty Reference Description Part Description Value Manufacturer Part Number Instructions 5 U1 to U3, U8, U12 IC-ADI LDO – Analog Devices ADP3334ACPZ

2 U10, U11 IC-ADI LDO – Analog Devices ADP1715ARMZ

1 U20 IC-ADI OPAMP – Analog Devices AD8032ARZ

1 U4 IC-ADI OPAMP – Analog Devices ADA4841-2YRZ

1 A1 IC-ADI REFERENCE – Analog Devices ADR434ARMZ

1 A2 IC-ADI REFERENCE – Analog Devices ADR381ARTZ

1 U6 IC-CYCLONE II – Altera Devices EP2C5F256C7N

1 U5 IC SERIAL CONFIG – Altera Devices EPCS4SI8N

1 Y3 IC CRYSTAL OSC 100 MHZ C-MAC SPXO009437-CFPS-73

22 C108, C111 to C131 CAP X7R 0402 0.1 µF Murata GRM155R71C104KA88D

2 C45, C89 CAP X7R 0508 0.1 µF TDK C1220X7R1E104K 1 C107 CAP NP0 0603 100 pF Phycomp 2238 867 15101 DNI

6 C17, C20, C24, C25, C36, C88

CAP X8R 0603 0.1 µF Murata GRM188R7E104KA01D

6 C66 to C68, C79 to C81 CAP X7R 0603 DNI

11 C38,C65, C70, C71, C72, C73, C75, C76, C77, C78, C92

CAP X7R 0805 0.1 µF Murata GRM21BR71H104KA01L

7 C8, C29 to C31, C86, C109, C110

CAP C0G 0805 1000 pF Murata GRM2165C2A102JA01D

11 C43,C44, C46, C47, C49, C50, C57, C59, C60, C62, C63

CAP NPO 0805 2700 pF Murata GRM2165C1H272JA01D

9 C1, C3, C4, C6, C10, C51, C53, C55, C56

CAP NPO 0805 2700 pF Murata GRM2165C1H272JA01D DNI

8 C2, C5, C48, C52, C54, C58, C61, C64

CAP NPO 0805 5600 pF Murata GRM2195C1H562JA01D DNI

15 C7, C9, C18, C19, C21, C22, C26 to C28, C32 to C34, C37, C85, C87

CAP X5R 0805 2.2 µF Murata GRM21BR71E225KA73L

10 C11 to C16, C23, C35, C69, C74

CAP X5R 0805 10 µF Murata GRM21BR61C106KE15L

2 C84, C90 CAP TANT 10 µF AVX TAJA106K010RNJ

7 C39 to C42, C91, C93, C94 CAP 0805 Murata – DNI

1 R94 RES 0402 0 Panasonic-ECG ERJ-2GE0R00X

4 R32, R72, R73, R103 RES 0603 – Panasonic-ECG – DNI

6 R2, R71, R125, R126, R136, R151

RES 0603 – Panasonic-ECG – DNI

6 R30, R31, R59, R137, R137, R151

RES 0603 0 Panasonic-ECG ERJ-3GEY0R00V

9 R60 to R68 RES 0603, 5% 50 Panasonic-ECG ERJ-3EKF49R9V

18 R74 to R78, R121, R122, R128, R130, R132, R134, R138 to R144

RES 0603, 5% 10 K Panasonic-ECG ERJ-3EKF1002V

2 R125, R126 RES 0603, 5% 15 K Yageo RC0603FR-0715KL DNI

2 R13, R55 RES 0603, 1% 140 K Panasonic-ECG


Rev. A | of 32

Qty Reference Description Part Description Value Manufacturer Part Number Instructions 14 R1, R24 to R26, R29, R80

to R82, R85, R86, R95, R97, R99, R100

RES 0805 – Panasonic-ECG – DNI

25 R7 to R9, R19 to R23, R41 to R49, R69, R70, R90 to R93, R96, R101

RES 0805 0 Panasonic-ECG ERJ-6GEY0R00V

2 R57, R58 RES 0805, 1% 22 Panasonic-ECG ERJ-6ENF22R0V

9 R34 to R40, R50, R55 RES 0805, 1% 90.9 Panasonic-ECG ERJ-6ENF90R9V

1 R27 RES 0805, 1% 365 Panasonic-ECG ERJ-6ENF3652V

9 R33, R52 to R54, R79, R83, R84, R87, R88

RES 0805, 1% 499 Panasonic-ECG ERJ-6ENF4990V

1 R28 RES 0805, 1% 590 Panasonic-ECG ERJ-6ENF5902V

2 R89, R145 RES 0805, 1% 604 Panasonic-ECG ERJ-6ENF6040V

2 R3, R5 RES 0805, 5% 1 K Panasonic-ECG ERJ-6ENF1001V

2 R4, R6 RES 0805, 5% 2 K Panasonic-ECG ERJ-6ENF2001V

6 R10 to R12, R98, R102, R135

RES 0805, 5% 10 K Panasonic-ECG ERJ-6ENF1002V

1 R16 RES 0805, 1% 64.9 K Panasonic-ECG ERJ-6ENF6492V

2 R14, R56 RES 0805, 1% 78.7 K Panasonic-ECG ERJ-6ENF7872V

1 R18 RES 0805, 1% 95.3 K Panasonic-ECG ERJ-6ENF6042V

1 R17 RES 0805, 1% 107 K Yageo RC0805FR-07300KL

1 R15 RES 0805, 1% 210 K Panasonic-ECG ERJ-6ENF2103V

2 CR1,CR2 LED Green Chicago MINI LAMP CMD28-21VGCTR8T1

3 P5, P7, P31 CONN-3 PIN MALE Breakaway Samtec TSW-103-08-G-S

1 P2 CONN-10 PIN MALE RA, shroud 3M 2510-5002UB

1 P1 CONN-26 PIN MALE Shroud 3M 30326-6002HB

1 P3 CONN-40 PIN MALE RA, Shroud 3M 2540-6002UB

1 P4 CONN-96 PIN MALE RA, DIN ERNI 533402

6 GND(S) Test point Black Components Corp TP-104-01-00

2 +15 V, MCLK Test point Yellow Components Corp TP-104-01-04

4 REF, +5 V A, +5 V D, REFIN Test point Red Components Corp TP-104-01-02

2 −15 V, −5 VA Test point White Components Corp TP-104-01-09

26 PD, CNV, CSB, DIN, Test point Blue Components Corp TP-104-01-06

SCK, SDO, VIO,

AVDD, BUSY, DVDD,

VDDH, VSSH,

AUX+I, AUX−I,

COM_I, IN0_I−IN7_I,

RESET, VDRV+,

VDRV−


Rev. A | of 32

RELATED LINKS Resource Description AD8032 Product Page, AD8031/AD8032, Low Power, Low Noise Amplifier ADR434 Product Page, ADR434, 4.096 Precision Reference ADP1715 Product Page, ADP1715, 500 mA Low Dropout CMOS Linear Regulator with Soft Start ADP3334 Product Page, ADP3334, High Accuracy Low IQ, 500 mA, ANYCAP®, Adjustable Low Dropout Regulator EVAL-CED1Z Product Page, Converter and Evaluation Development board AN-931 Application Note, Understanding PulSAR ADC Support Circuitry AN-932 Application Note, Power Supply Sequencing











http://www.analog.com/an-931?doc=UG-484.pdf

http://www.analog.com/an-932?doc=UG-484.pdf


Rev. A | of 32

NOTES


Rev. A | of 32

NOTES

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11064-0-2/14(A)



EVAL-ADAS3022EDZ User Guide - Analog Devices · configuration register allows the user to configure...

Documents

Transcript of EVAL-ADAS3022EDZ User Guide - Analog Devices · configuration register allows the user to configure...