EV76C771 2 Mpixels B&W and Color CMOS Image sensor
Transcript of EV76C771 2 Mpixels B&W and Color CMOS Image sensor
EV76C771 2 Mpixels B&W and Color CMOS Image sensor
e2vsemiconductors SAS 11/09/2014
FEATURES 2 million (1920 x 1080) pixels, 5.3 µm square pixels with shifted micro-lens
Optical format 2/3”
Aspect Ratio : 16/9 - Full HD
300 fps @ full resolution & 10 bits / 55fps@ full resolution&14 bits
Output format true 8 / 10 / 12 / 14 bits LVDS and synchronization
SPI controls
Control input pins: Trigger In, Reset
Light control output – Trigger out
3.3 V and 1.8 V power supplies
80 MHz input clock Embedded functions:
Image Statistics and Context output
Sub-sampling (Vertical)
Two PLL for LVDS and ADC frequencies generation
Wide Dynamic Range capabilities
Time to Read improvement (good first image, abort image) Timing modes:
Global shutter in Serial and Overlap modes
Rolling shutter and Global Reset modes
PERFORMANCE CHARACTERISTICS High sensitivity at low light level
Operating temperature [-30° to +65°C]
Peak QE>60%
AVAILABLESENSOR TYPES Monochrome
Color (Bayer arrangement)
APPLICATIONS Scientific imaging / Astronomy
Surveillance and security cameras
Industrial machine vision
Biometrics/Medical Imaging
Broadcast cameras
2D barcode scanners
INTRODUCTION The EV76C771 is a 2 million pixels CMOS image sensor, Full HD resolution, designed with e2v's proprietary CMOS imaging technology. It is ideal for many different types of application where superior performance is required. The innovative pixel design offers excellent performance in low-light conditions with an electronic global shutter (true snapshot), and offers a high-readout speed at 60 fps in full resolution and 14bits.
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1. TYPICAL PERFORMANCE DATA
Table 1: Typical electro-optical performances @ 25°C and 65°C, nominal pixel clock (80MHz)
Parameter(PRELIMINARY) Unit Typical Value
Sensor characteristics
Resolution pixels 1920 (H) x 1080 (V)
Image size mm inches
10.2 (H) x 5.7 (V) – 11.7 (diagonal) 2/3
Pixel size (square) µm² 5.3 x 5.3
Aspect ratio 16/9
Max frame rate fps 55 @ full resolution – 14 bits 300 @ full resolution – 10 bits
Pixel rate Mpixels / s 622 @10bits
Bit depth bits 8 – 10 – 12 - 14
Pixel performance
@ TA25°C @ TA65°C
Dynamic range dB >(1b)
> 76(1a)
“
Qsat / SNR max ke- / dB 18 / > 43 “
Readout Noise e- (ERS/GS/DDS) 3.5 / 18 / 7
MTF at Nyquist, =550 nm % 63
Dark signal(2)
LSB10 /s 5 e-/s 700 e-/s
DSNU(2)
LSB10 /s 15 e-/s 1500 e-/s
PRNU (3)
(RMS) % < 1
Responsivity (4)
LSB10 /(lux/s)
Electrical interface
Power supplies V 3.3 & 1.8
Power consumption : Functional
(5)
Standby
mW µW
<900 330
(1a): in electronic rolling shutter (ERS) mode (1b): in global shutter (GS) mode (2): min gain, 12 bits (3): measured @ Vsat/2, min gain (4): 3200K, window with AR coating, IR cutoff filter BG38 2 mm (5): @ 180 fps, 12bits, 2 ADCs & full format & with 10 pF on each output
Figure 1: EV76C771 Quantum efficiency
Quantum Efficiency - EV76C771
0.0%
10.0%
20.0%
30.0%
40.0%
50.0%
60.0%
70.0%
80.0%
400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100
Wavelength (nm)
Q.E
. (%
)
Monochrome
Red
Green
Blue
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2. SENSOR OVERVIEW
The EV76C771 image sensor is divided in 2 sections, arranged symmetrically around the horizontal axis. Each-sub-section has individual and independent inputs and outputs. The active area is 1936 x 1096 pixels and the useful pixel area is 1920 x 1080 pixels. Figure 2: Block diagram
SCK
MISO
SEQUENCER
+
POWER
MANAGEMENT
MOSI
P
L
L
CLK_N
LVD
S
CLK_P
8 x LVDS_N
<5 :0>
8 x LVDS_P
<5 :0>
SYNC_N
SYNC_P
RESET
N TRIG_IN
CLK
SEQUENCER
+
POWER
MANAGEMENT
SPI
P
L
L
CS_T
CLK_N
LVDS
CLK_P
8 x LVDS_N
<5 :0> 8 x LVDS_P
<5 :0> SYNC_N
SYNC_P
14
CS_B
RESET
N
TRIG_IN
CLK
TRIG_OUT
RESET
N TRIG_IN
CLK
TRIG_OUT
MISO
MISO
MOSI
MOSI
SCK
SCK
TEST TEST
THERMO
THERMO
TEST TEST
PIXEL ARRAY
1920 x 540
PIXEL ARRAY
1920 x 540
SYNCHRO
PATTERN GEN
CLAMP
CDS
HDR
GAIN
HISTOS
CONTEXT
MULTPLEXER
SERIALIZER
SDATA
14
SYNCHRO
PATTERN GEN
CLAMP
CDS
HDR
GAIN
HISTOS
CONTEXT
MULTPLEXER
SERIALIZER
SPI
SDATA
ANALOG GAIN
ADC 8…14 BITS
ANALOG GAIN
ADC 8…14 BITS
LINE
DECODER
LINE
DECODER
LINE
DECODER
LINE
DECODER
PLL
PLL
TRIG_OUT
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3. APPLICATION INFORMATION
This paragraph gives the top view pinout, the pin list and the power supplies decoupling. Figure 3:Pinout Top View
TOP VIEW
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Table 2 : Pinout Table
Pin Number
Pin Number
Name Type Top/
Bottom Electrical level
1 A1 CLK_EXT_T Input Clock Top VDDIO
2 A2 VDDIO_T IO Power Supply Top 1.8V – 3.3V
3 A3 VSS1833D_T Digital Ground Top Ground
4 A4 N_LVDS0_T Negative LVDS data 0 Top LVDS
5 A5 N_LVDS1_T Negative LVDS data 1 Top LVDS
6 A6 VSS1833D_T Digital Ground Top Ground
7 A7 N_LVDS2_T Negative LVDS data 2 Top LVDS
8 A8 N_LVDS3_T Negative LVDS data 3 Top LVDS
9 A9 N_LVDS_CLK_T Negative LVDS Clock Top LVDS
10 A10 P_LVDS_CTRL_T Positive LVDS Control Top LVDS
11 A11 P_LVDS4_T Positive LVDS data 4 Top LVDS
12 A12 P_LVDS5_T Positive LVDS data 5 Top LVDS
13 A13 VSS1833D_T Digital Ground Top Ground
14 A14 P_LVDS6_T Positive LVDS data 6 Top LVDS
15 A15 P_LVDS7_T Positive LVDS data 7 Top LVDS
16 A16 VSS1833D_T Digital Ground Top Ground
17 A17 VSS18A_PLL_T Analog Ground Top Ground
18 A18 MOSI_T SPI MOSI Top VDDIO
19 B1 RESET_N_T SPI Reset Top VDDIO
20 B2 TRIG_IN_T Trigger In Top VDDIO
21 B3 VDD33D_TL Digital power supply Top 3.3V
22 B4 P_LVDS0_T Positive LVDS data 0 Top LVDS
23 B5 P_LVDS1_T Positive LVDS data 1 Top LVDS
24 B6 VDD18D_TL Digital power supply Top 1.8V
25 B7 P_LVDS2_T Positive LVDS data 2 Top LVDS
26 B8 P_LVDS3_T Positive LVDS data 3 Top LVDS
27 B9 P_LVDS_CLK_T Positive LVDS Clock Top LVDS
28 B10 N_LVDS_CTRL_T Negative LVDS Control Top LVDS
29 B11 N_LVDS4_T Negative LVDS data 4 Top LVDS
30 B12 N_LVDS5_T Negative LVDS data 5 Top LVDS
31 B13 VDD18D_TR Digital power supply Top 1.8V
32 B14 N_LVDS6_T Negative LVDS data 6 Top LVDS
33 B15 N_LVDS7_T Negative LVDS data 7 Top LVDS
34 B16 VDD33D_TR Digital power supply Top 3.3V
35 B17 NC Top
36 B18 MISO_T SPI MISO Top VDDIO
37 C1 TRIG_OUT_T Trigger Out Top VDDIO
38 C2 SCAN_MODE_T Test Pin Top VDDIO
39 C17 CS_N_T Chip Select Top VDDIO
40 C18 SCK_T SPI Clock Top VDDIO
41 D1 NC Top
42 D2 VSS18A_ADC_T Analog Ground Top Ground
43 D17 DTEST0_T Digital Test Pin Top VDDIO
44 D18 DTEST1_T Digital Test Pin Top VDDIO
45 E1 VSS18A_RAM_TL Analog Ground Top Ground
46 E2 VDD18A_RAM_TL Analog power supply Top 1.8V
47 E17 VDD18A_RAM_TR Analog power supply Top 1.8V
48 E18 VSS18A_RAM_TR Analog Ground Top Ground
49 F1 VSS33A_ADC_TL Analog Ground Top Ground
50 F2 VDD33A_ADC_TL Analog power supply Top 3.3V
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Pin Number
Pin Number
Name Type Top/
Bottom Electrical level
51 F17 VDD33A_ADC_TR Analog power supply Top 3.3V
52 F18 VSS33A_ADC_TR Analog Ground Top Ground
53 G1 VDD_MAT_TL Analog power supply Top 3.3V
54 G2 VSS_MAT_TL Analog Ground Top Ground
55 G17 VSS_MAT_TR Analog Ground Top Ground
56 G18 VDD_MAT_TR Analog power supply Top 3.3V
57 H1 ATEST0_T Analog Test Pin Top 0 – 3.3V
58 H2 ATEST1_T Analog Test Pin Top 0 – 3.3V
59 H17 VDD33A_REG_T Analog power supply Top 3.3V
60 H18 VSS33A_REG Analog Ground Top Ground
61 J1 VLR_MEM_T (optional external
power supply) Top
62 J2 VLR_PH_T (optional external
power supply) Top
63 J17 VHR_MEM_T (optional external
power supply) Top
64 J18 VDD_DL_T Analog power supply Top 3.3V
65 K1 VLR_MEM_B (optional external
power supply) Bottom
66 K2 VLR_PH_B (optional external
power supply) Bottom
67 K17 VHR_MEM_B (optional external
power supply) Bottom
68 K18 VDD_DL_B Analog power supply Bottom 3.3V
69 L1 ATEST0_B Analog Test Pin Bottom
70 L2 ATEST1_B Analog Test Pin Bottom
71 L17 VDD33A_REG_B Analog power supply Bottom 3.3V
72 L18 VSS33A_REG Analog Ground Bottom Ground
73 M1 VDD_MAT_BL Analog power supply Bottom 3.3V
74 M2 VSS_MAT_BL Analog Ground Bottom Ground
75 M17 VSS_MAT_BR Analog Ground Bottom Ground
76 M18 VDD_MAT_BR Analog power supply Bottom 3.3V
77 N1 VSS33A_ADC_BL Analog Ground Bottom Ground
78 N2 VDD33A_ADC_BL Analog power supply Bottom 3.3V
79 N17 VDD33A_ADC_BR Analog power supply Bottom 3.3V
80 N18 VSS33A_ADC_BR Analog Ground Bottom Ground
81 P1 VSS18A_RAM_BL Analog Ground Bottom Ground
82 P2 VDD18A_RAM_BL Analog power supply Bottom 1.8V
83 P17 VDD18A_RAM_BR Analog power supply Bottom 1.8V
84 P18 VSS18A_RAM_BR Analog Ground Bottom Ground
85 R1 NC Bottom
86 R2 VSS18A_ADC_B Analog Ground Bottom Ground
87 R17 DTEST0_B Digital Test Pin Bottom VDDIO
88 R18 DTEST1_B Digital Test Pin Bottom VDDIO
89 T1 TRIG_OUT_B Trigger Out Bottom VDDIO
90 T2 SCAN_MODE_B Test Pin Bottom VDDIO
91 T17 CS_N_B Chip Select Bottom VDDIO
92 T18 SCK_B SPI Clock Bottom VDDIO
93 U1 RESET_N_B SPI Reset Bottom VDDIO
94 U2 TRIG_IN_B Trigger In Bottom VDDIO
95 U3 VDD33D_BL Digital power supply Bottom 3.3V
96 U4 P_LVDS0_B Positive LVDS data 0 Bottom LVDS
97 U5 P_LVDS1_B Positive LVDS data 1 Bottom LVDS
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Pin Number
Pin Number
Name Type Top/
Bottom Electrical level
98 U6 VDD18D_BL Digital power supply Bottom 1.8V
99 U7 P_LVDS2_B Positive LVDS data 2 Bottom LVDS
100 U8 P_LVDS3_B Positive LVDS data 3 Bottom LVDS
101 U9 P_LVDS_CLK_B Positive LVDS Clock Bottom LVDS
102 U10 N_LVDS_CTRL_B Negative LVDS Control Bottom LVDS
103 U11 N_LVDS4_B Negative LVDS data 4 Bottom LVDS
104 U12 N_LVDS5_B Negative LVDS data 5 Bottom LVDS
105 U13 VDD18D_BR Digital power supply Bottom 1.8V
106 U14 N_LVDS6_B Negative LVDS data 6 Bottom LVDS
107 U15 N_LVDS7_B Negative LVDS data 7 Bottom LVDS
108 U16 VDD33D_BR Digital power supply Bottom 3.3V
109 U17 NC Bottom
110 U18 MISO_B SPI MISO Bottom VDDIO
111 V1 CLK_EXT_B Input Clock Bottom VDDIO
112 V2 VDDIO_B IO Power Supply Bottom 1.8V – 3.3V
113 V3 VSS1833D_B Digital Ground Bottom Ground
114 V4 N_LVDS0_B Negative LVDS data 0 Bottom LVDS
115 V5 N_LVDS1_B Negative LVDS data 1 Bottom LVDS
116 V6 VSS1833D_B Digital Ground Bottom Ground
117 V7 N_LVDS2_B Negative LVDS data 2 Bottom LVDS
118 V8 N_LVDS3_B Negative LVDS data 3 Bottom LVDS
119 V9 N_LVDS_CLK_B Negative LVDS Clock Bottom LVDS
120 V10 P_LVDS_CTRL_B Positive LVDS Control Bottom LVDS
121 V11 P_LVDS4_B Positive LVDS data 4 Bottom LVDS
122 V12 P_LVDS5_B Positive LVDS data 5 Bottom LVDS
123 V13 VSS1833D_B Digital Ground Bottom Ground
124 V14 P_LVDS6_B Positive LVDS data 6 Bottom LVDS
125 V15 P_LVDS7_B Positive LVDS data 7 Bottom LVDS
126 V16 VSS1833D_B Digital Ground Bottom Ground
127 V17 VSS18A_PLL_B Analog Ground Bottom Ground
128 V18 MOSI_B SPI MOSI Bottom VDDIO
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Table 3 : Power Supply Decoupling
(1)Optional: VDD_DL and VDD_MAT are used if external power supply is needed.
Note 1:VDDIO is used for all SPI, TRIG IN/OUT, RESETN and CLK_EXT pins Note 2: It is recommended to use X7R for all the 100nF capacitors.
4. PACKAGE SPECIFICATION
This paragraph gives the package drawing and the window characteristics. Table 4 : Window Characteristics
Parameters Specification
Window material SCHOTT D263 EcoT
Window thickness 0.55 +/-0.05 mm
Window index ne = 1.5255
AR Coating Transmittance (400-900nm) > 97%
Pins NameDecoupling
(per pin )
Power
ConsumptionComments
J18, K18 VDD_DL (1) 20µF /
100nF (optional)
0
150mA peak
- Left floating by defaut (internal regulator)
- // 100nF if external regulator
G1, G18, M1, M18 VDD_MAT (1) 10µF /
100nF (optional)
12mA
250mA peak
- Left floating by defaut (internal regulator)
- // 100nF if external regulator
B17, D1, R1, U17 VDD18A 1µF // 100nF16mA
50mA peakAnalog 1,8 V ( PLL, ADC)
B6, B13, E2, E17, P2, P17,
U6, U13VDD18D 1µF // 100nF
300mA
800mA peakDigital 1,8V (RAM, ...)
F2, F17, H17, L17, N2, N17 VDD33A 1µF // 100nF300 mA
400mA PeakADC and Internal regulators
B3, B16, U3, U16 VDD33D 1µF // 100nF75mA
90mALVDS output
A2, V2 VDDIO 1µF // 100nF 1mA to be connected to FPGA outputs (1.8V to 3.3V)
J17, K17 VHR_MEM 100nF (optional)- Left floating by defaut
- // 100nF if external regulator
J1, K1 VLR_MEM 100nF (optional)- Left floating by defaut
- // 100nF if external regulator
J2, K2 VLR_PH 100nF (optional)- Left floating by defaut
- // 100nF if external regulator
A17, D2, F1, F18, G2, G17,
H18, L18, M2, M17, N1, N18,
R2, V17
VSS_18_33A Analog Ground
A3, A6, A13, A16, E1, E18,
P1, P18, V3, V6, V13, V16VSS_18_33D Digital Ground
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Figure 4 : µPGA 128 Pins Package Drawing
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5. SENSOR OPERATING STATES
The sensor has different operating states as described below.
5.1 Stand By state
The Stand By state is the lowest power consumption state. The SPI registers can be programmed during the Stand By state.
5.2 Idle state
The Idle state is equivalent to a “break” mode where the sensor is waiting for a trigger. The power consumption is low but the sensor is still active.
5.3 Free Run state
In the “Free Run” mode, the sensor output frames without any user’s action. The frame rate is controlled by the integration time, the waiting time, specific functions and/or the clocks supplied to the sensor.
5.4 Trigger state
The sensor can be triggered using an external signal and/or by SPI registers. A single pulse launches an acquisition composed by consecutive integration time + readout time + optional wait time. A continuous trigger signal is equivalent to the free run mode. The sensor also provides a “pipelined” trigger mode for frame rate improvement, and an Integration Time Control (exposure controlled by the trigger).
6. READOUT MODES DESCRIPTION
The sensor offers several readout modes: - Global Shutter - Electronic Rolling Shutter - Digital Double Sampling (in Global Shutter) - Serial / Overlap modes - Video mode
6.1 Electronic Rolling Shutter mode (ERS)
The Electronic Rolling Shutter mode allows integration and readout line by line. The ERS introduces readout distortion, but the readout noise is as low as possible. A True Rolling Shutter mode is possible, with the top semi-matrix readout followed by the bottom one.
6.2 Global Shutter mode (GS)
The Global Shutter mode allows true snapshot readout. The GS does not introduce any distortion during the integration and readout. The readout noise is higher compared to the ERS mode (except if DDS mode is used; see below).
6.3 Digital Double Sampling (DDS)
The Digital Double Sampling (DDS) is a function similar to the Correlated Double Sampling (CDS) but done in the digital domain (after the signal is converted by the ADC) rather than in the analog main (before the ADC). It allows a readout noise reduction especially when the Global Shutter mode is used.
The sensor outputs 2 consecutive images: a first image with the all the pixel reference levels followed by an image with all the pixel signal levels. Subtraction product of these two images will generate a low readout noise global shutter image. An off-chip image processing with external memory will be required to perform this subtraction. Figure 5 : Digital Double Sampling timing
Integration time Image 1 Image 2 Image 3 Reference Data Ref 1 Ref 2 Ref 3 Signal Data S1 S2
Image memory Mem. Ref 1 Mem. Ref 2 Mem. Ref 3 Processing image Image 1 = S1 – Mem Ref 1 Image 2 = S2 – Mem Ref 2
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6.4 Serial and Overlap mode
A sensor acquisition is composed of an integration time followed by a readout time. When the sensor is in free run mode or in video mode, there are 2 ways to output images: - The Serial mode outputs each acquisition one after the other. The frame rate in this case is dependent on the integration time and readout time (ROI size). - The Overlap mode allows the overlapping of readout time and integration time. In this mode, the highest frame rate can be achieved. Frame rate remains the same while the integration time is lower than the readout time. Figure 6 : Overlap and Serial modes
6.5 Video mode
In Video mode, the frame rate is fixed and programmed through dedicated registers. In this mode, the “wait time” between frames is calculated automatically, based on the integration and readout times (Int and Read in figures below). Figure 7 : Video mode in Serial
In serial mode, the really first frame is always in serial mode. Figure 8 : Video mode in Overlap
Serial mode
Overlap mode
Int 1 Read 1 Int 2 Read2 Int 3 Read 3 …
Int 1 Read 1
Int 2 Read2
Frameperiod 1 Frameperiod2 Frameperiod 3
Int 4 Read 4 …
Int 3 Read3
SameFrame period DifferentFrame period
Video mode
(Serial) Int 1 Read
Fixed Frame Period
Wait 1 Int 2 Read Wait2 Int 3 Read
Video mode
(Overlap) Int 1 Read
Fixed Frame Period
Wait 1
Int 2 Read Wait2
Int 3 Read Wait 3
Int 4 Read
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7. ON-CHIP FUNCTIONS DESCRIPTION
The EV76C771 sensor has several on-chip analog and digital features for user convenience or to achieve higher performances.
7.1 Flip
The readout can be flipped in vertical (row flip), through SPI register programming. The horizontal flip can be achieved during the external image reconstruction. This allows easy system integration, depending on lens and optics.
7.2 Region Of Interest
The Region Of Interest (ROI) feature controls the number of columns and rows in a given frame. This operation is performed after the image flip but before sub-sampling and defect correction. Reducing the number of lines of the ROI increases the frame rate.
7.3 Sub sampling
The sub sampling allows faster sensor readout by sampling, in horizontal and vertical, 1 pixel over 2, 4 or 8. The interest is that the field of view is fully preserved.
7.4 Trigger Out
The “Trig Out” pin outputs the exposure period used in the sensor. The top “Trig Out” can be routed on the bottom “Trig In” to achieve the True rolling Shutter mode.
7.5 Trigger In
The “Trig In” pin is used to trigger the sensor. When triggered, the sensor launches acquisition sequence.
7.6 Integration Time Control (ITC)
The ITC mode uses the Trig In to launch an acquisition with the integration time corresponding to active level of the input signal.
7.7 Output Patterns
Output patterns are digitally generated, to test the acquisition system. They can be also configured using the registers.
7.8 Analog To Digital Converter (ADC)
The Analog to Digital Converter can convert 2 rows at a time, in true 8bits, 10bits, 12bits or 14bits. Each semi-matrix has its own ADC: one Top ADC and one Bottom ADC.
7.9 Clock tree
The input clock is 80MHZ, by default. This clock will be directly used for internal propose and by the two internal PLLs, dedicated to LVDS and sequencer.
7.10 Wide Dynamic Range functions
The sensor offers 2 different Wide Dynamic Range modes: Logarithmic and Global Shutter Bi-exposure.
7.10.1 Logarithmic
This mode sets the sensor in logarithmic response. Depending on the logarithmic adjustment, the dynamic range can reach up to 120dB.
7.10.2 Bi-Exposure
The sensor can output two consecutive images, with two different exposures. Then, with external memories and image processing, a wide dynamic range image can be achieved. The ratio between the two exposures will define the wide dynamic range value.
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7.11 Context
The Context provides additional information on sensor state and some statistics. It is composed of a “Header”, output before the data, and a “Footer”, output after the data.
7.12 Temperature Sensor
The EV76C771 contains two embedded temperature sensors, one for each semi-sensor. The temperature reading is accessible through dedicated SPI registers or through analog outputs. The temperature range is [-40°c; +85°C] and a digital calibration will be needed.
8. INTERFACE DESCRIPTION
8.1 LVDS output
Each semi-sensor (Top and Bottom) has its own dedicated pixel clock and synchronization signals, and is divided in 8 blocks of 256 columns by 582 rows. A LVDS pair is dedicated to each block for Data output. The LVDS common voltage is 1.2V with 350mV differential level and sub-LVDS is 0.9V with 175mV differential level. One semi-sensor owns 10 LVDS pairs as described below:
- 8 LVDS pairs for pixel data - 1 LVDS pair for synchronization - 1 LVDS pair for pixel clock
Then, for the entire sensor, there are 20 LVDS pairs arrange as below:
- 2 x 8 LVDS pairs for pixel data - 2 x 1 LVDS pairs for synchronization - 2 x 1 LVDS pairs for pixel clock
Figure 9 : LVDS pairs organization
Top Sensor
Bottom Sensor
Block T0
Block T1
Block T2
Block T3
Block T4
Block T5
Block T6
Block T7
Block B0
Block B1
Block B2
Block B3
Block B4
Block B5
Block B6
Block B7
256 columns
LVDS B0
LVDS B1
LVDS B2
LVDS B3
LVDS B4
LVDS B5
LVDS B6
LVDS B7
LVDS T0
LVDS T1
LVDS T2
LVDS T3
LVDS T4
LVDS T5
LVDS T6
LVDS T7
582 rows
LVDS Synchro B
LVDS Pixel clk B
LVDS Synchro T
LVDS Pixel clk T
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The Data and Synchronization Channel are organized as described below. Figure 10 : LVDS Data organization
Data Filling HEADER Data Filling
Data Filling IMAGE Data Filling
Data Filling FOOTER Data Filling
Data Filling
Note: Data filling can be changed using the SPI registers. Figure 11 : LVDS Synchronization signal
HEADER IDLE
SOF EOL
IDLE SOL IDLE
BLANKING LINE
= IDLE
EOL EOF
FOOTER
BLANKING FRAME
= IDLE
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8.2 Serial Peripheral Interface
The EV76C771 contains internal registers used for the sensor operation. These registers can be programmed using the Serial Peripheral Interface (SPI). Each semi-sensor has its own registers, controlled by individual SPI (MOSI, MISO and SCK).
9. SENSOR OPTIONS
The EV76C771 sensor is available in two versions:
Monochrome
RGB Bayer filter
Others : contact e2v marketing
10. STANDARDS COMPLIANCE
The EV76C771 sensor conforms to the following standards:
RoHS compliant
Product qualification according to JEDEC JESD47
MSL 3 compliant
11. ORDERING CODES
11.1 Standard version with protective foil
EV76C771ABT-EQTR Monochrome product,
EV76C771ACT-EQTR Color Bayer product. For other packaging, please contact e2v. The sensors are delivered in Jedec trays of 44 units each.
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TABLE OF CONTENTS
1. TYPICAL PERFORMANCE DATA .................................................................................................................2
2. SENSOR OVERVIEW .....................................................................................................................................3
3. APPLICATION INFORMATION ......................................................................................................................4
4. PACKAGE SPECIFICATION ..........................................................................................................................8
5. SENSOR OPERATING STATES ................................................................................................................. 10
5.1 STAND BY STATE ..................................................................................................................................... 10 5.2 IDLE STATE .............................................................................................................................................. 10 5.3 FREE RUN STATE ..................................................................................................................................... 10 5.4 TRIGGER STATE ....................................................................................................................................... 10
6. READOUT MODES DESCRIPTION ............................................................................................................ 10
6.1 ELECTRONIC ROLLING SHUTTER MODE (ERS) .......................................................................................... 10 6.2 GLOBAL SHUTTER MODE (GS) ................................................................................................................. 10 6.3 DIGITAL DOUBLE SAMPLING (DDS) .......................................................................................................... 10 6.4 SERIAL AND OVERLAP MODE .................................................................................................................... 11 6.5 VIDEO MODE ............................................................................................................................................ 11
7. ON-CHIP FUNCTIONS DESCRIPTION ....................................................................................................... 12
7.1 FLIP ........................................................................................................................................................ 12 7.2 REGION OF INTEREST .............................................................................................................................. 12 7.3 SUB SAMPLING ........................................................................................................................................ 12 7.4 TRIGGER OUT ......................................................................................................................................... 12 7.5 TRIGGER IN ............................................................................................................................................. 12 7.6 INTEGRATION TIME CONTROL (ITC) .......................................................................................................... 12 7.7 OUTPUT PATTERNS ................................................................................................................................. 12 7.8 ANALOG TO DIGITAL CONVERTER (ADC) .................................................................................................. 12 7.9 CLOCK TREE............................................................................................................................................ 12 7.10 WIDE DYNAMIC RANGE FUNCTIONS .......................................................................................................... 12 7.11 CONTEXT ................................................................................................................................................ 13 7.12 TEMPERATURE SENSOR ........................................................................................................................... 13
8. INTERFACE DESCRIPTION ....................................................................................................................... 13
8.1 LVDS OUTPUT ........................................................................................................................................ 13 8.2 SERIAL PERIPHERAL INTERFACE ............................................................................................................... 15
9. SENSOR OPTIONS ..................................................................................................................................... 15
10. STANDARDS COMPLIANCE ...................................................................................................................... 15
11. ORDERING CODES .................................................................................................................................... 15
11.1 STANDARD VERSION WITH PROTECTIVE FOIL.............................................................................................. 15
EV76C771
17 e2v semiconductors SAS 11/09/2014
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