EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

Oxford Semiconductor, Inc.1900 McCarthy Boulevard, Suite 210Milpitas, CA 95035USA

http://www.oxsemi.com

UG-0030 Feb 07

EV-OXU210-PCI and EV-OXU210

Evaluation BoardUser Guide

ii External—Free Release UG-0030 Feb 07

EV-OXU210-PCI Evaluation Board User Guide Oxford Semiconductor, Inc.

© Oxford Semiconductor, Inc. 2006

The content of this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in this manual.

ON Semiconductor is a register trademark of Semiconductor Components Industries, LLC.All other trademarks are the property of their respective owners.

UG-0030 Feb 07 External—Free Release iii

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vRevision Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vTypographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vOrdering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viContacting Oxford Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Chapter 1 EV-OXU210-PCI .............................................................................. 1-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1PCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Serial EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

Chapter 2 EV-OXU210 Evaluation Board ...................................................... 2-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1Board Operation Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2OTG & Host Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2Default Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3Oscillator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4VBUS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5OXU210HP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5DP/DM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5VBUS Over-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6Mounting Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

Chapter 3 PCI104 Bridge Board ..................................................................... 3-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2Local Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3Local Bus Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3Mounting Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

Chapter 4 Schematics ..................................................................................... 4-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

Contents

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Contents EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

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This manual documents the EV‐OXU210‐PCI and EV‐OXU210 Evaluation Board hardware.

Revision Information

Table I documents the revisions of this manual

Table I Revision Information

Revision ModificationJul 2006 First publicationAug 2006 In the Overview section, added “, the PCI104” to the end of the

second bullet.In Table 1-3, corrected the default values for offsets 2Ch, 54h, 56h, and 68h.In Figure 2-1, changed “Charge Pump” to “Power Switch”.In the VBUS Source section, added “to select the TPS2044BD” at the end of the first bullet.In the VBUS Source section, corrected a few port numbers.In the Local Bus Configuration section, changed “256 Kb memory space size “ to “128 Kb memory space size” .In the Schematics chapter, replaced the Rev. 1.0 schematics with Rev. 2.1 schematics.Change the footer to read “External—Free Release”

Nov 2006 In the Preface, deleted “development kit” in the first sentence.Updated the schematics in Figure 4-1 through Figure 4-8 to Revision 2.2

Feb 2007 Changed the corporate address on the cover page.Added the Certified USB logo to the cover page.In the Test Points section, changed the AMP/Tyco Electronics part number from “2-767004-2” to “2-5767004-2”

Preface

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EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

Typographic Conventions

In this manual, the conventions listed in Table II apply.

Ordering Information

The following boards are available:

EV‐OXU210‐PCI Evaluation Board (EV‐OXU210‐PCI‐110)

EV‐OXU210 Evaluation Board (EV‐OXU210‐110)

PCI104 Bridge Board (TDPCI104‐1000‐01)

Contacting Oxford Semi-conductor

See the Oxford Semiconductor website (http://www.oxsemi.com) for further details about Oxford Semiconductor devices, or email [email protected].

Table II Typographic Conventions

Convention Meaning

Italic Letters With Initial Capital Letters A cross-reference to another publication

Courier Font Software code, or text typed in via a keyboard

1, 2, 3 A numbered list where the order of list items is significant

A list where the order of items is not significant

“Title” Cross-refers to another section within the document

Significant additional information

http://www.oxsemi.com

UG-0030 Feb 07 External—Free Release 1—1

EV-OXU210-PCI

Overview The EV‐OXU210‐PCI Evaluation Board is a system for OXU210HP customer evaluations and internal software development in the PC environment. The EV‐OXU210‐PCI Evaluation Board allows the user to install and use the EV‐OXU210 in any PCI‐based computer. Application software running on the system has access to the OXU210HP via the PCI memory space.

The EV‐OXU210‐PCI Evaluation Board is a two‐board combination of the following:

An EV‐OXU210 Evaluation Board

A 33 MHz, 32‐bit PCI Bridge Board, the PCI104

The EV‐OXU210 Evaluation Board contains the OXU210HP and all the USB‐specific hardware.

The PCI104 Bridge Board contains a PCI‐to‐local‐bus bridge chip that bridges the PCI bus to the OXU210HP. Power and control signals to the PCI bus are maintained by the PCI bridge chip set, while initialization and configuration of the PCI bridge chip is maintained by the on‐board serial EEPROM.

Figure 1‐1 illustrates the orientation of the two boards. The combined boards are approximately one inch thick and require space for two PCI devices, but only one PCI slot. The OXU210HP OTG and host USB connectors are easily accessible through the openings in the computer case.

Chapter 2 describes the EV‐OXU210 Evaluation Board. Chapter 3 describes the PCI104 Bridge Board. For complete information about the OXU210HP device, see the OXU210HP Hardware Reference Manual.

Chapter 1

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EV-OXU210-PCI EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

Figure 1-1 EV-OXU210-PCI System Board Orientation

PCI Operation

Every PCI implementation has a PCI configuration space, where the PCI configuration registers are found. PCI configuration registers are accessed with read/write to configuration space, which is separate from memory and I/O space. Table 1‐1 lists the standard PCI configuration register space for all PCI functions on the PCI bus.

EV-OXU210

PC104 Connectors

PCI Slot

PCI Connector PCI104

CPU Motherboard

Table 1-1 Standard PCI Configuration Register Space

Byte 3 Byte 2 Byte 1 Byte 0 OffsetDevice ID Vendor ID 00hStatus Register Command Register 04hClass Code Revision ID 08hBIST Header Type Latency Timer Cache Line Size 0ChBase Address Register 0 (BAR 0) 10hBase Address Register 1 (BAR 1) 14hBase Address Register 2 (BAR 2) 18hBase Address Register 3 (BAR 3) 1ChBase Address Register 4 (BAR 4) 20hBase Address Register 5 (BAR 5) 24hCardBus CIS Pointer 28hSubsystem ID Subsystem Vendor ID 2ChExpansion ROM Base Address 30hReserved Capabilities

Pointer34h


EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide EV-OXU210-PCI

The PCI104 can be identified on the PCI bus during enumeration by the following PCI configuration registers:

Most operating systems provide functions for finding devices on the PCI bus. These functions typically key off the Vendor and Device IDs, or the Class Code. Because the Class Code for the PCI104 appears as a PCI Bridge with sub class code “other”, the search should be keyeed to the Vendor and Device IDs.

Configuration The EV‐OXU210‐PCI has two memory mapped register spaces and one I/O mapped register space. The address locations of the various spaces are determined by the Base Address Registers of the bridge controller registers. Base Address Register 0 (BAR0) of the PCI bridge controller registers contains the address of the memory mapped PCI bridge controller registers. BAR1 contains the I/O address for the same PCI bridge controller registers. The PCI bridge controller registers are mapped into both memory and I/O space, so that these registers can be accessed via memory accesses or I/O addressing. BAR3 contains the address of the memory mapped OXU210HP registers. Figure 1‐2 illustrates the register mappings within a PCI system.

Reserved 38hMax Latency Min Grant Interrupt Pin Interrupt Line 3Ch

Table 1-2 PCI Configuration Registers

Register Power-On ValueVendor ID 192EhDevice ID 032BhRevision 0001hClass Code 0680hSubsystem ID 032BhSubsystem Vendor ID 192Eh

Table 1-1 Standard PCI Configuration Register Space

Byte 3 Byte 2 Byte 1 Byte 0 Offset



Figure 1-2 PCI104 Register Mappings

The Base Address Registers are typically initialized by the system BIOS or by the operating system. Software generally does not have to manually set the addresses of the mapped locations, however, this is system dependent. If these registers are not initialized, the three spaces should be manually mapped into system memory and I/O space accordingly. Care must be taken to ensure no conflicts exist between the mapped regions and other devices on the PCI bus.

Serial EEPROM Registers

The PCI9030 PCI bridge controller provides an interface to program the attached serial EEPROM. The serial EEPROM should be pre‐programmed with the default values in Table 1‐3. The table is for informational purposes only. If the default values are modified, the behavior of the PCI104 will change.

CPU

PCI9030 Offset 0x10 0x14 0x18 0x1C 0x20 0x24

Local Addr Space 0

Local Addr Space 1

Local Addr Space 2

Local Addr Space 3

Configuration Registers

Register BAR0 (mem) BAR1 (I/O) BAR2 (mem) BAR3 (mem) BAR4 (mem) BAR5 (mem)

Table 1-3 Serial EEPROM Registers

Serial EEPROM Offset Description Default00h PCI Device ID 032Bh02h PCI Vendor ID 192Eh04h PCI Status Register 0290h06h PCI Command Register Reserved08h PCI Class Code 0680h0Ah PCI Class Code / Revision Number 0001h0Ch PCI Subsystem ID 032Bh0Eh PCI Subsystem Vendor ID 192Eh10h MSB New Capability Pointer Reserved12h LSB New Capability Pointer 0040h


EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide EV-OXU210-PCI

14h (Maximum Latency and Minimum Grant are not loadable) Reserved16h Interrupt Pin (Interrupt Line Routing is not loadable) 0100h18h MSW of Power Management Capabilities 4801h1Ah LSW of Power Management Next Capability Pointer /

Power Management Capability ID4801h

1Ch MSW of Power Management Data /PMCSR Bridge Support Extension Reserved1Eh LSW of Power Management Control/Status 0000h20h MSW of Hot Swap Control/Status Reserved22h LSW of Hot Swap Next Capability Pointer / Hot Swap Control 4C06h24h PCI Vital Product Data Address Reserved26h PCI Vital Product Data Next Capability Pointer /

PCI Vital Protocol Data Control0003h

28h MSW of Local Address Space 0 Range 0000h2Ah LSW of Local Address Space 0 Range 0000h2Ch MSW of Local Address Space 1 Range FFFEh2Eh LSW of Local Address Space 1 Range 0000h30h MSW of Local Address Space 2 Range 0000h32h LSW of Local Address Space 2 Range 0000h34h MSW of Local Address Space 3 Range 0000h36h LSW of Local Address Space 3 Range 0000h38h MSW of Expansion ROM Range 0000h3Ah LSW of Expansion ROM Range 0000h3Ch MSW of Local Address Space 0 Local Base Address (Remap) 0000h3Eh LSW of Local Address Space 0 Local Base Address (Remap) 0000h40h MSW of Local Address Space 1 Local Base Address (Remap) 0000h42h LSW of Local Address Space 1 Local Base Address (Remap) 0001h44h MSW of Local Address Space 2 Local Base Address (Remap) 0000h46h LSW of Local Address Space 2 Local Base Address (Remap) 0000h48h MSW of Local Address Space 3 Local Base Address (Remap) 0000h4Ah LSW of Local Address Space 3 Local Base Address (Remap) 0000h4Ch MSW of Expansion ROM Local Base Address (Remap) 0010h4Eh LSW of Expansion ROM Local Base Address (Remap) 0000h50h MSW of Local Address Space 0 Bus Region Descriptor 0080h52h LSW of Local Address Space 0 Bus Region Descriptor 0000h54h MSW of Local Address Space 1 Bus Region Descriptor 4080h56h LSW of Local Address Space 1 Bus Region Descriptor A040h58h MSW of Local Address Space 2 Bus Region Descriptor 0000h5Ah LSW of Local Address Space 2 Bus Region Descriptor 0000h5Ch MSW of Local Address Space 3 Bus Region Descriptor 0080h5Eh LSW of Local Address Space 3 Bus Region Descriptor 0000h


Serial EEPROM Offset Description Default



60h MSW of Expansion ROM Bus Region Descriptor 0000h62h LSW of Expansion ROM Bus Region Descriptor 0000h64h MSW of Chip Select 0 Base Address 0BFFh66h LSW of Chip Select 0 Base Address FFC1h68h MSW of Chip Select 1 Base Address 0001h6Ah LSW of Chip Select 1 Base Address 0001h6Ch MSW of Chip Select 2 Base Address 0000h6Eh LSW of Chip Select 2 Base Address 0000h70h MSW of Chip Select 3 Base Address 0000h72h LSW of Chip Select 3 Base Address 0000h74h Serial EEPROM Write-Protected Address Boundary 0030h76h LSW of Interrupt Control/Status 0041h78h MSW of Target Response, Serial EEPROM, and initialization Control 0870h7Ah LSW of Target Response, Serial EEPROM, and initialization Control 0000h7Ch MSW of General Purpose I/O Control 0024h7Eh LSW of General Purpose I/O Control 9864h80h MSW of Hidden 1 Power Management Data Select 0000h82h LSW of Hidden 1 Power Management Data Select 0000h84h MSW of Hidden 2 Power Management Data Select 0000h86h LSW of Hidden 2 Power Management Data Select 0000h


Serial EEPROM Offset Description Default


EV-OXU210 Evaluation Board

Overview This chapter describes the hardware operation and configuration options available for the EV‐OXU210 in stand‐alone mode. These options allow customers to directly connect the OXU210HP to their embedded processor or CPU without going through a PCI bus. The use of this board without the PCI bridge card increases performance and allows driver development in real‐world applications of the product. Figure 2‐1 shows the EV‐OXU210 block diagram.

Chapter 2


EV-OXU210 Evaluation Board EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

Figure 2-1 EV-OXU210 Block Diagram

Board Operation Requirement

The EV‐OXU210 requires a DC power source capable of supplying 5 V ±10% at 1.0 A through a power switch.

OTG & Host Port Configu-rations

The EV‐OXU210 supports both OXU210HP port configurations. Port 1 of the OXU210HP can function as either a host port, a peripheral port, or a full OTG port.

To select between the high‐speed OTG or host‐only modes, select one of these configurations:

Install jumper on JP4 pin 1‐2 (host‐only mode).

Install jumper on JP4 pin 2‐3 (OTG mode).

High‐speed USB host (Port 2) is fixed as a standard host mode. Refer to “VBUS Source” on page 2‐5 for further configuration details.

5.0 V to 3.3 V

Converter

1.8 V Core

3.3 V

3.3 V,

2.5 V , or

1.8 V I/O

P

C

1

0

4

C

O

N

N

E

C

T

O

R

5 V

Mictor Test

Headers

(Optional)

5.0 V to 2.5 V

Converter

Resistors

Port 2

Mini AB

Port 1

Type A

Processor

Bus

OXU210HP

BGA84 or LQFP128

12 MHz

Crystal or

Oscillator

TPS2044BDPower Switch

5.0V to 1.8V

Converter


EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide EV-OXU210 Evaluation Board

Default Configura-tions

Zero‐Ohm resistors are used to set the following factory default configurations:

R10, R11 (0 Ω) populated to route 5 V from the PCI104 connectors

R15, R16 (0 Ω) populated, R14 removed to use on‐board 12 MHz crystal

R18‐R21 (0 Ω) populated for DP/DM signals

R62 and R64 (0 Ω) populated for analog and digital 3.3 V

R66 (0 Ω) populated, R67 and R68 removed to set VIO to 3.3 V. Note that the VIO wide range I/O power supply is named MVCC on the schematics

R65 (0 Ω) populated to use 1.8 V voltage regulator for the 1.8 V core

R42‐R45 (0 Ω) populated to route DMA signals from PC104 connector to OXU210HP

R46‐R47, R53‐R54 (0 Ω) populated to route INTL, WRL, RDL, and CS1L from PC104 connectors to OXU210HP

R6 (0 Ω) populated, R5 removed to use the TPS2044BD 500 mA power switch (U1) as the source of VBUS in OTG or host mode

Power Distribution

In the default mode, the EV‐OXU210 receives all its power from the 5 V pins of the PC104 connector. The 5 V supply drives the 3.3 V, 2.5 V, and 1.8 V voltage regulators. Alternative power‐supply options are described below. Note that the VIO wide range I/O power supply is named MVCC on the schematics.

5 V Power Supply

The EV‐OXU210 5 V power is supplied by one of two sources:

1. The PC104 connector 5 V pins: J6.D16, J7.B3, J7.B29 (default setting).

2. An external power supply connected to JP8.3. To enable this mode, remove R10 (0 Ω) and R11 (0 Ω). Protection circuitry is not provided.

3.3 V Power Supply

The EV‐OXU210 3.3 V power is supplied by one of two sources:

1. 5 V‐to‐3.3 V DC regulator (U11). R62 (0 Ω) and L2 are installed to limit analog 3.3 V and allow current flow in the digital 3.3 V (default setting).



2. An external power supply connected to JP6.3. To enable this mode, remove R64 (0 Ω). Protection circuitry is not provided.

1.8 V Core Power Supply

The EV‐OXU210 1.8 V power is supplied by one of two sources:

1. An on‐board 5.0 V‐to‐1.8 V DC voltage regulator (U13). This is the default setting with R65 (0 Ω) installed.

2. An external power supply connected to JP7.3. To enable this mode, remove R65 (0 Ω). Protection circuitry is not provided.

3.3/2.5/1.8 V VIO Wide Range I/O Power Supply

The EV‐OXU210 provides either 1.8 V or 3.3 V for VIO, the wide range power. The voltage is selected through the intallation or removal of resistors as described below. The EV‐OXU210 gives the option of 3.3 V, 2.5 V, or 1.8 V through resistor settings. Any other value within this range is customer specific and is not directly supported by this evaluation board. The EV‐OXU210 VIO power is supplied by one of three sources:

1. From the 3.3 V power rail (default setting). Install R66 (0 Ω) and remove R67 (0 Ω) and R68 (0 Ω).

2. From the 2.5 V power rail. Install R68 (0 Ω) and remove R66 (0 Ω) and R67 (0 Ω).

3. 5.0 V‐to‐1.8 V DC regulator (U13). Install R67 (0 Ω) and remove R66 (0 Ω) and R68 (0 Ω).

Oscillator Input

The EV‐OXU210 uses a 12 MHz crystal at Y1 for the OXU210HP XSCI/XSCO clock source. The external 22 pF capacitors are used to control the stability of the frequency and startup time.

A 12 MHz oscillator can be soldered at the U3/U4 dual‐footprint by the customer and used as the OXU210HP clock source. To enable this mode, install R14 (33 W) and remove R15 (0 Ω). Also, remove R16 (0 Ω) because the XSCO pin must be floating in this configuration. Below are the part numbers that Oxford Semiconductor has used for internal design and testing. Other components meeting the OXU210HP requirements may be used (see the OXU210HP, OXU140CM, OXU121HP, and OXU200 External Crystal Selection application note).

12 MHz Crystal: Citizen America, HCM49‐12.000MABJT, 18 pF internal load (or RoHS compliant HCM49‐12.000MABJUT)

12 MHz Oscillator: Ecliptek, EH1345HSTS‐12.000M, 50 ppm, 8‐pin DIP (RoHS compliant)


EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide EV-OXU210 Evaluation Board

VBUS Source VBUS in Host Port Configuration

When the OXU210HP is in host configuration under OTG Port 1 (J4), the EV‐OXU210 drives VBUS via the TPS2044BD 500 mA Power Switch (U1), using the OXU210HP PO_N signal. Since Port 2 (J5) is a fixed host port, it is always driven by the TPS2044BD. To configure Port 1 (J4) for host port configuration, follow these steps:

R6 (0 Ω) is installed and R5 is removed to select the TPS2044BD (default setting, charge pump not used).

Install jumper on JP4 pin 1‐2 (host‐only mode).

VBUS in OTG Port Configuration

When the OXU210HP is in OTG configuration, the EV‐OXU210 can drive VBUS for the OTG Port 1 (J4) with one of two sources:

1. The TPS2044BD 500 mA Power Switch (U1) using the OXU210HP EXT_VBO signal (default setting)

Install R6 (0 Ω) and remove R5Install jumper on JP4 pin 2‐3 (OTG mode)

2. The OXU210HP internal 100 mA charge pumpInstall R5 (0 Ω) and remove R6Install jumper on JP4 pin 2‐3 (OTG mode)

OXU210HP Reset

The /RESET of the OXU210HP is brought out to the PC104 connector to allow control of the /RESET through a CPU GPIO. Push button S2 can also be used to assert /RESET manually.

DP/DM Signals

R18‐R21 (0 Ω) are installed

Each of the DP/DM pairs has an external ESD protection device (U14, U15). The ID pin may also be protected by this device. Refer to the Oxford Semiconductor OXU210HP External ESD Protection application note for more detail

Refer to the Oxford Semiconductor OXU210HP Layout Requirements application note for more detail



VBUS Over-Voltage Protection

Besides the ESD transient protection provided by the external ESD devices, the OXU210HP VBUS pin is also protected against steady‐state voltages above 5.1 V (typical) by the voltage divider resistor (R23 = 390 Ω) and the Zener diode D4. When the OXU210HP is configured as a B‐device in OTG mode and is connected to a host driving VBUS greater than 5.1 V, the Zener diode protects the OXU210HP from damage.

Zener diode: ON Semiconductor® BZX84C5V1LT1, 225mW, 5.1 V breakdown

LEDs The EV‐OXU210 has the following LEDs to enable monitoring of the normal operation of the board:

D9: 5.0 V Power Rail indicator



D1: VBUS Power indicator for OTG port

D2: VBUS Power indicator for host port

Mounting Holes

The EV‐OXU210 board has four un‐plated standoff holes, one near each corner of the board. Each hole is 0.146 inch in diameter. The placement matches the PCI104 PCI board which together make the EV‐OXU210‐PCI.

Test Points The following test points are furnished on the EV‐OXU210:

Ground test points JP2, JP5, JP9 and JP10. 3P3VCC_CONN from PC104 connectors (TP11)

USB_5V_P1 (TP2), USB_5V_P2 (TP5), DPHOST/DMHOST (JP3), DPOTG/DMOTG (JP4), ID (TP1)

Internal charge pump components ‐ L1: TP3 and TP4, C9 (TP6 and TP7), VOUT (TP7)

Byte enable (BE0‐BE3) has test points TP10, TP12‐TP14

Power supplies 5 V (JP8.3), 3.3 V (JP6.3), and 1.8 V (JP7.3)

All the microprocessor signals are routed to Mictor connectors, J1 and J2. The Mictor connectors are not installed but can be obtained from AMP/Tyco Electronics. Part Number: 2‐5767004‐2. Description: Receptacle, 38 positions, .025 vertical.


PCI104 Bridge Board

Overview The PCI104 Bridge Board (measuring 5.55 in. (140.9 mm) by 3.00 in. (76.2 mm) can be employed to:

Evaluate the Oxford Semiconductor OXU210HP USB OTG and host controller

Run OXU210HP demonstrations

Develop user software for OXU210HP based applications

Serve as a subassembly in an OEM product to provide USB OTG and host controller functionality

While the EV‐OXU210‐PCI can be used to evaluate the OXU210HP, it will not result in optimal performance due to the long access times of the PCI bus and bridge. For optimal performance evaluation, the OXU210HP should be placed directly on the system bus using the EV‐OXU210 board as described in Chapter 2.

The PCI104 board bridges between the PCI bus and the PCI9030 local bus. The local bus is routed out to the standard PC104 connectors (J6 and J7). Another proprietary, non‐PC104 connector (J8) is added to support a 32‐bit interface and additional signals not included in the PC104 signal definition. The EV‐OXU210 interfaces to the PCI104 Bridge Card via these three female connectors. Figure 3‐1 shows the PCI104 block diagram.

Chapter 3


PCI104 Bridge Board EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

Figure 3-1 PCI104 Bridge Board

The PCI104 board uses the PCI9030 bridge device. The PCI configuration registers are stored in an on‐board EEPROM.

The PCI edge connector supplies both 5 V and 3.3 V power. The PCI104 board can also receive its 3.3 V from a 5 V to 3.3 V regulator. This option is jumper selectable.

Power Distribution

The PCI104 board receives its 5 V power from the standard PCI bus edge connector (U2 – eight 5 V pins). The 5 V supply is routed directly to the EV‐OXU210 via the PC104 connectors (J1.D16, J2.B3, J2.B29).

The PCI104 board 3.3 V power is supplied by one of two sources:

1. 5.0 V-to-3.3 V DC regulator (U1). Install jumper on JP2 pin 1-2, 3-4 (default setting) and remove 5-6 and 7-8.

2. The standard PCI bus edge connector (U2 – twelve 3.3 V pins). Install jumper on JP2 pin 5-6, 7-8 and remove 1-2 and 3-4.

P

C

I

E

D

G

E

C

O

N

N

E

C

T

O

R

5.0 V to 3.3 V

DC

Converter

PCI9030

PQFP176

PCI_3.3 V

EEPROM

PCI Bus

Local Bus

5 V

3.3 V

P

C

O

N

N

E

C

T

O

R

1

0

4

C


EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide PCI104 Bridge Board

Local Bus Configuration

The PCI9030 local bus is connected directly to the EV‐OXU210 board via the PC104 connectors. Refer to the PCI9030 Data Book for a detailed explanation of its operation.

The PCI9030 CS1L chip select is routed to the EV‐OXU210. Register Space 1 of the PCI9030 controls CS1L. The number values programmed into Space 1 registers of the EEPROM are shown below. Changing values in the EEPROM requires an application from the bridge chip operating across the PCI bus. Space 1 has 32‐bit local and PCI space and contains 128 Kb memory space size. There is no pre‐fetch on space 1.

Space 1 Range 0x0FFE_0000

Space 1 Remap 0x0000_0001

Space 1 Descriptor 0x4080_A040

Space 1 Base Address 0x0001_0001

Space 1 Initialization GPIO Control 0x0024_9864

The local timing is one WAIT state for READs (address‐to‐data) and one for WRITEs (address‐to‐data) to make the PCI104 backwards compatible with previous Oxford Semiconductor chips. The other WAIT states are: zero RD (data‐to‐data), one RD/WR (data‐to‐address), zero WR (data‐to‐data), and one WR cycle hold. An optimum bus access will not create a significant increase in performance in the EV‐OXU210‐PCI system. For better performance evaluation, the OXU210HP should be embedded directly on the system bus using the EV‐OXU210 board.

Local Bus Speed

LCLK, the local bus clock, operates at frequencies up to 60 MHz and is asynchronous to the PCI bus clock, BCLK. BCLK is routed back into LCLK, setting the default local bus speed at 33 MHz.

An oscillator up to 60 MHz can be soldered at the U4/U5 dual‐footprint by the customer to increase the local bus speed. R10 (33 ohms) must be installed and R11 removed in this configuration. More WAIT states may have to be added to meet the OXU210HP interface timing when increasing the local bus frequency. See “Local Bus Configuration”.

LEDs The PCI104 has two LEDs to enable verification of the normal operation of the board.

D1: 3.3V Power Rail Indicator

D2: 5.0V Power Rail Indicator

Mounting Holes

The PCI104 board has four un‐plated standoff holes, one near each corner of the board. Each hole is 0.146” in diameter. The placement matches the EV‐OXU210 evaluation board which together make the EV‐OXU210‐PCI.


PCI104 Bridge Board EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

This page is intentionally blank


Schematics

Overview This chapter provides the EV‐OXU210 and PCI104 schematics. The EV‐OXU210 uses a dual‐footprint so either the LQFP128 (U5) or the BGA84 (U6) package can be installed, but not both.

Chapter 4


Schematics EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

Figure 4-1 EV-OXU210 Top-Level Schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EV-OXU210 CARD TOP LEVEL

Rev 2.0:

Deleted test pins on diff pairs

Rev 2.1:

If the EVB210 is re-spun, U2 and Q2 can be deleted.

Rev 2.2:

Changed internal charge pump capability from 50mA

to 100mA.

SC

-OX

210-

A3-

001

2.2

EV

-OX

U21

0 C

ard

: TO

P L

EV

EL

18

Tues

day,

Dec

embe

r 05,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

PC

104_

Con

nect

or

PC

104_

Con

nect

or

SA

[19:

1]

SD

[31:

0]

CS

1L

RD

L

WR

L

RE

SE

TL

INTL

AC

K0

AC

K1

DR

Q0

DR

Q1

GP

IO1

CS

2LC

S3L

GP

IO_P

LD1

GP

IO_P

LD2

RE

AD

YL

GP

IO2

GP

IO0

GP

IO3

BE

[3:0

]

SD

CK

E0

SD

CLK

0

Pow

er_D

istri

butio

n

Pow

er_D

istri

butio

n

OTG

_CLO

CK

S

OTG

_CLO

CK

S

OTG

_XS

CI

OTG

_XS

CO

US

B_C

onne

ctor

US

B_C

onne

ctor

DP

OTG

DM

OTG

ID PO

_NO

C_N

EXT

_VBO

_N

DP

HO

ST

DM

HO

ST

VOU

TE

XT

PD

_PM

OS

VB

US

Sys

tem

_PLD

Sys

tem

_PLD

CS

1L

CS

2LC

S3L

RD

LW

RL

GP

IO_P

LD1

GP

IO_P

LD2

RE

AD

YL

RE

SE

TL

SD

CK

E0

SD

CLK

0

A[5

:1]

D[7

:0]

GP

IO0

GP

IO1

GP

IO2

GP

IO3

OTG

_CS

1L

OTG

_RD

LO

TG_W

RL

OTG

_IN

TL

BE

[3:0

]

INTL

A[1

9:17

]

OTG

_DR

Q0

OTG

_DR

Q1

OTG

_AC

K0

OTG

_AC

K1

DR

Q0

DR

Q1

AC

K0

AC

K1

DE

BU

G[7

:0]

OX

U21

0HP

OTG

_IN

TL

OTG

_RES

ETL

OTG

_CS

1L

OTG

_WR

L

OTG

_RD

L

OTG

_D[3

1:0]

OTG

_A[1

6:1]

OTG

_DP

OTG

OTG

_DM

OTG

OTG

_ID

OTG

_PO

LO

TG_O

CL

OTG

_EX

VB

OL

OTG

_XSC

OO

TG_X

SCI

OTG

_GP

IO1

OTG

_DR

Q0

OTG

_DR

Q1

OTG

_AC

K0

OTG

_AC

K1

OTG

_DM

HO

ST

OTG

_DP

HO

ST

OTG

_VO

UT

OTG

_EX

TO

TG_P

D_P

MO

S

OTG

_VB

US

OTG

_GP

IO0

OTG

_GP

IO2

OTG

_GP

IO3

OTG

_BE

[3:0

]

DE

BU

G[7

:0]

OTG

_XSC

IO

TG_X

SCO

DM

OTG

DP

HO

ST

PO

_N

PD

_PM

OS

VO

UT

ID

D[3

1:0]

EX

T

VB

US

DM

HO

ST

DP

OTG

EXT

_VBO

_N

GP

IO0

GP

IO1

GP

IO2

GP

IO3

OTG

_CS

1L

OTG

_RD

LO

TG_W

RL

BE

[3:0

]

OTG

_IN

TL

CS

1L

A11

OTG

_A11

A2

OTG

_A2

INTL

A2

A3

A14

OTG

_A14

GP

IO1

OTG

_A[1

6:1]

A4

OTG

_A4

D2

D5

BE

[3:0

]

D6

A10

OTG

_A10

A5

OTG

_A5

A1

OTG

_A1

WR

L

RD

L

D7

A3

OTG

_A3

D4

D[7

:0]

GP

IO3

A[5

:1]

WR

L

D0

A12

OTG

_A12

SD

CK

E0

A4

A[1

9:1]

INTL

RE

SE

TL

A9

OTG

_A9

A15

OTG

_A15

D3

A16

OTG

_A16

RE

SE

TL

GP

IO2

A8

OTG

_A8

A13

OTG

_A13

RD

L

GP

IO0

CS

1LA5

A7

OTG

_A7

A1

D1

A6

OTG

_A6

SD

CLK

0

RE

AD

YL

A17

A18

A19

A[1

9:17

]

OTG

_DR

Q0

OTG

_AC

K0

OTG

_DR

Q1

OTG

_AC

K1

DR

Q0

AC

K0

DR

Q1

AC

K1

CS

2LC

S3L

GP

IO_P

LD2

GP

IO_P

LD1

OC

_N

DE

BU

G[7

:0]

DR

Q0

AC

K0

A[1

9:1]

GP

IO1

WR

L

GP

IO0

DR

Q1

SD

CLK

0R

EA

DY

L

INTL

GP

IO3

GP

IO2

RD

L

AC

K1

CS

1LD

[31:

0]C

S1L

SD

CLK

0

A[1

9:1]

DR

Q1

AC

K0

INTL

GP

IO0

RD

L

RE

AD

YL

WR

L

DR

Q0

AC

K1

D[3

1:0]

GP

IO2

GP

IO1

GP

IO3


EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide Schematics

Figure 4-2 EV-OXU210 Test Headers

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Female Mictor Connector

AMP 2-5767004-2 gold-plated

AMP 767054-1

GROUND TEST POINTS

Distribute the TestPoints on top side

TEST HEADERS

MH's are to be .146"

non-plated thru

holes.

TEST HEADERS

Mictor Test Headers

Mictor headers have

internal 50K

pull-ups.

Mictor headers have

internal 50K

pull-ups.

Female Mictor Connector

AMP 2-5767004-2 gold-plated

AMP 767054-1

SC

-OX

210-

A3-

002

2.2

EV

-OX

U21

0 C

ard

: Mic

tor T

est H

eade

rs

28

Tues

day,

Dec

embe

r 05,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

D20

D19

D26

D21

D22

D31

D25

D29

D18

D16

D24

D27

D17

D23

D30

D28

RE

AD

YL

A18

A17

A3

A9

A7

A14

A4

A11

A6

A10

A13

A8

A15

A12

A1

A16

A5

A[1

9:1]

A2

D10

D1

D15

D7

D8

D9

D3

D11

D5

D0

D2

D14

D12

D13

D4

D6

D[3

1:0]

WR

L

CS

1LIN

TL

DR

Q0

AC

K0

RD

L

AC

K1

DR

Q1

A19

DR

Q0

GP

IO1

GP

IO3

RD

L

DR

Q1

CS

1L

AC

K0

WR

L

RE

AD

YL

GP

IO2

AC

K1

GP

IO0

INTL

D[3

1:0]

A[1

9:1]

SD

CLK

0

SD

CLK

0

GP

IO1

GP

IO0

GP

IO2

GP

IO3

AC

K0

AC

K1

GP

IO1

CS

1L

DR

Q0

RE

AD

YL

GP

IO2

DR

Q1

GP

IO3

WR

LR

DL

INTL

GP

IO0

D[3

1:0]

A[1

9:1]

SD

CLK

0

J1 Mic

tor3

8

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

39

4041

4243

JP5

1X2

2 1

V5

1

J2 Mic

tor3

8

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

39

4041

4243

JP10

1X2

2 1

JP9

1X2

2 1

JP2

1X2

2 1

MH

2

V18

1V

171

MH

3

MH

4

MH

1



Figure 4-3 EV-OXU210 PC104 Connectors

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Bypass caps for

PC104 connector

TPS3801K33DCKR

TPS3801J25DCKR

TPS3801E18DCKR

200ms delay

Male headers placed on

bottom side of board.

Extra Connector, Non-PC104 Standard

Male headers placed on

bottom side of board.

PC104 Connector

No internal

pull-ups/downs.

Place test points near

PC104 connector.

Remove to use external

5V power supply.

SC

-OX

210-

A3-

003

2.2

EV

-OX

U21

0 C

ard

: PC

104

Con

nect

or

38

Thur

sday

, Nov

embe

r 30,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

SA

7

SA

16

GP

IO_D

5P0V

CC

_CO

NN

CS

2L

SD

11

SD

1

SA

3

SD

4

SD

15

SD

0

GP

IO_E

WR

L

SA

0

SA

14

SD

2D

MA

_DR

Q1

SA

2

LIN

T2

SA

13

nPW

E_R

SD

13S

D12

SA

6

SA

11S

A12

SD

8

RE

SE

T_R

SA

5

SA

9

SD

5

SD

CK

E0

INTL

SA

4

SA

8

SD

7

SD

CLK

0

SD

14

SA

15

RD

L

SA

10

SD

6

CS

1LC

S3L

DM

A_D

RQ

0

SA

1

SD

3

SD

10S

D9

SA

10

SA

7S

A8

DM

A_E

OT1

DM

A_E

OT0

SA

1

SA

5

SA

12

SA

14

SD

19

SD

28

SD

18

SD

27

SD

17

SD

23

SD

25

SD

21S

D22

SD

26

SD

16

SD

20

SD

24

SD

31S

D30

SD

29

SA

2S

A3

SA

4

SA

6

SA

9

SA

11

SA

13

SA

15S

A16

SD

23

SD

5

SD

27

SD

19

SD

25

SD

31

SD

2

SD

7

SD

4

SD

6

SD

12S

D28

SD

17S

D16

SD

3

SD

30

SD

0

GP

IO_A

GP

IO_F

GP

IO2

DM

A_A

CK

0

SD

1

SD

8S

D9

SD

10S

D11

SD

13S

D14

SD

15

SD

18

SD

20S

D21

SD

22

SD

24

SD

26

SD

29

RE

SE

T_C

ON

N

GP

IO1

BE

3B

E2

BE

1B

E0

SA

17S

A18

SA

19

SA

17S

A18

SA

19

BE

0

BE

3B

E2

BE

1

DM

A_A

CK

1

3P3V

CC

_CO

NN

MV

CC

MV

CC

MV

CC

MV

CC

MV

CC

MV

CC

MV

CC

MV

CC

MV

CC

MV

CC

5P0V

CC

5P0V

CC

_CO

NN

3P3V

CC

_CO

NN

R11

0_12

06R

_120

6

R22

DN

I_10

K

TP13

R56

10K

U10

TPS3

801

4 12

53

VDD GND1GND2

MR

RE

SE

T

S2

SW

_KT1

1P3J

M

2 1

R39

DN

I_10

K

R10

0_12

06R

_120

6

TP12

V13

1

V4

1

C27 0.1u

F

R41

DN

I_10

K

TP10

V16

1

R48

10K

V10

1

R40

DN

I_10

K

TP11

R52

DN

I_10

K

R58

20J7

PC

104_

2X32

_Hea

der

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

V7

1+

C10

4.7u

F

V8

1

C33

0.1u

F

+C

224.

7uF

V12

1

V9

1

R57

130

R61

10K

R51

DN

I_10

K

V11

1

J8

PC

104_

2X20

_Hea

der

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

J6

PC

104_

2X20

_Hea

der

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

R34

DN

I_10

K

TP14

V6

1

C21

0.1u

FC

18 0.1u

F

R37

DN

I_10

K

C29

22pF

C13 0.1u

F

C28 22

00pF

RE

SE

TL

GP

IO_P

LD2

AC

K1

AC

K0

RD

L

DR

Q1

GP

IO_P

LD1

RE

AD

YL

DR

Q0

CS

2L

INTL

WR

L

CS

1LC

S3L

GP

IO2

SA

[19:

1]

SD

[31:

0]

GP

IO0

GP

IO3

GP

IO1

SD

CK

E0

SD

CLK

0

BE

[3:0

]



Figure 4-4 OXU210HP Schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

OXU210HP

Deco

up

lin

g C

ap

acit

ors

Place decoupling

capacitors near

OXU210.

Place components as

close to the OXU210

as possible.

SC

-OX

210-

A3-

004

2.2

EV

-OX

U21

0 C

ard

: OX

U21

0HP

48

Tues

day,

Dec

embe

r 05,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

OTG

_XSC

O

OTG

_DM

OTG

_SB

OTG

_DP

OTG

_SB

OTG

_DP

HO

ST_

SB

OTG

_DM

HO

ST_S

B

OTG

_DR

Q0

OTG

_RES

ETL

OTG

_IN

TL

OTG

_DR

Q1

OTG

_AC

K0

OTG

_GP

IO3

OTG

_GP

IO2

OTG

_GP

IO1

OTG

_AC

K1

OTG

_GP

IO0

OTG

_DM

HO

ST

OTG

_DM

OTG

OTG

_DPO

TG

OTG

_VB

US

OTG

_EXT

OTG

_VO

UT

OTG

_PO

L

OTG

_DP

HO

ST

OTG

_EXV

BOL

OTG

_ID

OTG

_BE0

OTG

_D4

OTG

_D11

OTG

_D23

OTG

_A14

OTG

_D12

OTG

_D15

OTG

_A7

OTG

_A8

OTG

_GP

IO3

OTG

_D20

OTG

_AC

K0

OTG

_A1

OTG

_A9

OTG

_DM

HO

ST

OTG

_D5

OTG

_D10

OTG

_D15

OTG

_D14

DE

BU

G1

OTG

_A1

OTG

_PO

L

OTG

_IN

TL

OTG

_A16

OTG

_D27

OTG

_GP

IO0

OTG

_A12

OTG

_D5

OTG

_D9

OTG

_XSC

O

DE

BU

G3

OTG

_RE

FHO

ST

OTG

_BE0

OTG

_D26

OTG

_D21

OTG

_DR

Q1

OTG

_D0

OTG

_D4

OTG

_D12

OTG

_D30

OTG

_D12

OTG

_DR

Q0

OTG

_A11

OTG

_D11

OTG

_D14

OTG

_CS

1L

OTG

_A13

OTG

_D6

OTG

_RD

L

OTG

_D15

OTG

_OC

L

OTG

_TES

T

OTG

_D7

OTG

_A3

OTG

_D31

OTG

_D16

OTG

_AC

K1

OTG

_DM

OTG

OTG

_D7

OTG

_CS

1L

OTG

_XSC

I

OTG

_D1

OTG

_D22

OTG

_A15

OTG

_D6

OTG

_A11

OTG

_CS

1L

DE

BU

G5

DE

BU

G1

OTG

_D25

OTG

_D8

OTG

_A2

OTG

_RES

ETL

OTG

_D25

OTG

_D31

DE

BU

G5

OTG

_D10

OTG

_A1

OTG

_DP

HO

ST_

SB

OTG

_RD

L

OTG

_RES

ETL

DE

BU

G2

OTG

_A7

OTG

_RD

L

OTG

_PD

_PM

OS

OTG

_D13

OTG

_BE2

OTG

_PD

_PM

OS

OTG

_A10

OTG

_D10

OTG

_A6

OTG

_D30

OTG

_D22

OTG

_DR

Q0

OTG

_VB

US

OTG

_TES

T

OTG

_A4

OTG

_A5

OTG

_BE3

DE

BU

G3

OTG

_D26

OTG

_D20

OTG

_DM

HO

ST_S

B

DE

BU

G6

OTG

_D28

OTG

_D9

OTG

_A13

OTG

_EXV

BOL

OTG

_D13

DE

BU

G7

OTG

_BE3

OTG

_D19

OTG

_A12

OTG

_PO

L

OTG

_D1

OTG

_D13

OTG

_A3

OTG

_A2

OTG

_D27

OTG

_A7

OTG

_RE

FHO

ST

OTG

_A13

OTG

_A4

OTG

_WR

L

OTG

_GP

IO0

OTG

_A10

OTG

_ID

OTG

_A8

OTG

_D8

OTG

_A5

OTG

_A6

DE

BU

G2

OTG

_D2

OTG

_D0

OTG

_D21

DE

BU

G0

OTG

_A8

OTG

_RE

FOTG

OTG

_D29

OTG

_D23

OTG

_VO

UT

OTG

_IN

TL

OTG

_D19

OTG

_D17

OTG

_BE1

DE

BU

G7

OTG

_A16

OTG

_A15

OTG

_VO

UT

OTG

_A9

OTG

_VB

US

OTG

_DP

OTG

_SB

OTG

_D3

OTG

_D4

OTG

_D6

OTG

_GP

IO2

DE

BU

G4

OTG

_BE2

OTG

_D17

OTG

_OC

L

OTG

_D2

OTG

_D11

OTG

_XSC

O

OTG

_WR

L

OTG

_D16

OTG

_A10

DE

BU

G6

OTG

_D29

OTG

_RE

FOTG

OTG

_RE

FOTG

OTG

_D2

OTG

_GP

IO1

OTG

_A14

OTG

_DP

HO

ST

OTG

_EXV

BOL

OTG

_DPO

TG

OTG

_WR

L

OTG

_D18

OTG

_A16

OTG

_D5

OTG

_D24

OTG

_BE1

OTG

_A14

OTG

_EXT

OTG

_ID

OTG

_DM

OTG

_SB

OTG

_D8

OTG

_A15

OTG

_D28

OTG

_PD

_PM

OS

OTG

_EXT

OTG

_A6

OTG

_D7

DE

BU

G4

OTG

_D1

OTG

_A2

OTG

_XSC

I

DE

BU

G0

OTG

_A11

OTG

_D9

OTG

_D14

OTG

_D3

OTG

_A4

OTG

_A3

OTG

_A12

OTG

_A9

OTG

_RE

FHO

ST

OTG

_BE0

OTG

_AC

K0

OTG

_D0

OTG

_A5

OTG

_BE1

OTG

_D24

OTG

_D18

OTG

_D3

OTG

_OC

L

OTG

_TES

T

OTG

_GP

IO1

OTG

_GP

IO2

OTG

_GP

IO0

OTG

_GP

IO3

3P3V

CC

A

MV

CC

1P8V

DD

3P3V

CC 1P

8VD

D

MV

CC

3P3V

CC

A

MV

CC

1P8V

DD

3P3V

CC

A

3P3V

CC

3P3V

CC

MV

CC

MV

CC

MV

CC

MV

CC

3P3V

CC

A C80

DN

I_0.

001u

F

R26

DN

I_10

K

C58

0.1u

F

C65

0.1u

F

U6

OX

U21

0_B

GA8

4

D10K

6K

7

A1

B1

B2

D9B6

A6

A7

B7

A8

B8

A9

K1

K2 J1 J2 H1

H2

G2

G1 F3 F1 F2 E2

E1

D2

D1

C1

C10

K8

K9

E9

F9K3

K4

F10

E10

E8

D3

C7

C4

H4

G9

H5

F8 H3B5

A5

A4

B4

C9A3

G3

H6

H9

D8

B10

A10

G10

J10

H10

B3

C3

C6

G8

J4

K5

C8

E3

K10

H7

H8

J8J5 J9B9

A2

C2

C5

J6 J7

J3

RE

SE

T

XS

CI

XS

CO

CS

RD

WR

INT

A8

A7

A6

A5

A4

A3

A2

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

TES

T

DM

_OTG

DP

_OTG ID

EX

VB

O

DM

_HO

ST

DP

_HO

ST

OC

PO

VS

S_E

8V

SS

_D3

VS

S_C

7

VIO

_C4

VD

D33

A_H

4

VB

US

VD

D33

A_H

5

VS

SA

_F8

VS

SA

_H3

A9

A10

A11

A12

A1

A13

VS

S_G

3

VD

D33

A_H

6

VP

WM

3

VIO

_D8

DR

Q0

AC

K0

VO

UT

EX

TP

D_P

MO

S

A14

VS

S_C

3V

DD

18_C

6

VD

D33

A_G

8

BE

0

RE

F_H

OS

T

VD

D18

_C8

VD

D18

_E3

RE

F_O

TG

VS

SA

_H7

VS

SA

_H8

VD

D33

A_J

8V

SS

A_J

5V

SS

A_J

9

GP

IO0

A15

A16

VS

S_C

5

VD

D3I

O

VIO

_J7

BE

1

SB

41

2

R28

82

C66

0.1u

F

R17

12K

_1%

R13

12K

_1%

C52

0.1u

F

C59

0.1u

F

R30

DN

I_10

K

C51

0.1u

F

C55

0.1u

F

C25

100p

F

C64

0.1u

F

R27

DN

I_10

K

C57

0.1u

F

SB

11

2

R24

100

SB

31

2

C62

0.1u

F

R36

DN

I_10

K

C23

100p

F

C61

0.1u

F

C60

0.1u

F

C81

DN

I_0.

001u

F

C69

0.1u

F

C24

100p

F

R33

DN

I_10

K

C56

0.1u

F

C84

DN

I_0.

001u

F

C20

DN

I_22

pF

C67

0.1u

F

R32

DN

I_10

K

R35

DN

I_10

K

C63

0.1u

F

C82

DN

I_0.

001u

F

R25

82

R29

82

C68

0.1u

F

SB

21

2

C54

0.1u

F

C19

DN

I_22

pF

R31

DN

I_10

K

C53

0.1u

F

U5

OX

U21

0_LQ

FP12

8

845758

126 1

127 83113

112

111

110

109

108

107 33 32 31 30 26 25 24 23 22 21 20 19 17 16 15 14

8962 63 77 7549 48 7678

552928

6 4771 5246 51116

117

118

119

106

120 56

59 6412

91 93 90 92

70 66 69

123 734353637383940412345891011

18 27

42434445

50 53 5461

60 65

67

6872

7379

8081

82

85868788100

101

102

103

9495

96979899 104

105

114

115

121

122

124

125

12813

74

RE

SE

T

XS

CI

XS

CO

CS

RD

WR

INT

A8

A7

A6

A5

A4

A3

A2

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

TES

T

DM

_OTG

DP

_OTG ID

EX

VB

O

DM

_HO

ST

DP

_HO

ST

OC

PO

VS

S55

VS

S29

VS

S28

VIO

_6

VD

D33

A_4

7

VB

US

VD

D33

A_5

2V

SS

A46

VS

SA

51

A9

A10

A11

A12

A1

A13

VS

S56

VD

D33

A_5

9V

DD

33A

_64

VIO

_12

DR

Q0

AC

K0

DR

Q1

AC

K1

VO

UT

EX

TP

D_P

MO

S

A14

VS

S7

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

VD

D18

_18

VIO

_27

BE

0B

E1

BE

2B

E3

RE

F_H

OS

T

VD

D18

_53

VD

D18

_54

RE

F_O

TG

VS

SA

60V

SS

A65

VP

WM

3

VS

SA

68V

DD

33A

_72

VS

SA

73

VS

S79

VIO

_80

VD

D18

_81

VS

S82

DE

BU

G0

DE

BU

G1

DE

BU

G2

DE

BU

G3

DE

BU

G4

DE

BU

G5

DE

BU

G6

DE

BU

G7

VIO

_94

VS

S95

GP

IO0

GP

IO1

GP

IO2

GP

IO3

VIO

_104

VS

S10

5

VD

D18

_114

VS

S11

5V

IO_1

21V

SS

122

A15

A16

VS

S12

8

VS

S13

VD

D3I

O

C83

DN

I_0.

001u

F

OTG

_XSC

I

OTG

_XSC

O

OTG

_RD

LO

TG_W

RL

OTG

_CS

1L

OTG

_D[3

1:0]

OTG

_A[1

6:1]

DE

BU

G[7

:0]

OTG

_BE

[3:0

]

OTG

_IN

TL

OTG

_GP

IO1

OTG

_GP

IO3

OTG

_DR

Q0

OTG

_AC

K0

OTG

_RES

ETL

OTG

_GP

IO2

OTG

_DR

Q1

OTG

_AC

K1

OTG

_GP

IO0

OTG

_VB

US

OTG

_DM

OTG

OTG

_DP

HO

STO

TG_D

MH

OST

OTG

_ID

OTG

_EXT

OTG

_VO

UT

OTG

_EXV

BOL

OTG

_PO

LO

TG_D

POTG

OTG

_PD

_PM

OS

OTG

_OC

L



Figure 4-5 EV-OXU210 Clocks

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ECLIPTEK EH26 SERIES

OR EQUIVALENT

3.3V 12MHz

Oscillator

12 MHz

Crystal

ECLIPTEK EH1345HSTS-xx.xxxM

OR EQUIVALENT. Use a DIP

socket for this location.

OTG Clocks

Citizen Corporation P/N:

HCM49-12.000MABJ-UT.

Place resistors

close to crystal

or oscillators.

SC

-OX

210-

A3-0

052.

2

EV

-OX

U21

0 C

ard

: OTG

Clo

cks

58

Thur

sday

, Nov

embe

r 30,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

XS

CI

XS

CO

_CR

YS

TAL

XS

CI_

CR

YS

TAL

3P3V

CC

R16

0

C15

0.1u

F

C17

22pF

U4

DN

I_H

alf_

size

_DIP

1

4

5

8

EN

GND

OU

T

VCCR

810

K

R14

DN

I_33

R15

0

U3

DN

I_5x

7mm

_sm

_cer

amic

1

2

3

4

EN

GND

OU

T

VCC

R12

DN

I_50

0KY

1C

ryst

al_1

2MH

z

1 2

C16

22pF

OTG

_XSC

OO

TG_X

SCI



Figure 4-6 EV-OXU210 Power Distribution

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

5.0V to 3.3V Voltage Conversion

3.3V I/O

Power Headers

Power Indicators

Power Distribution



1.8V, 2.5V, or 3.3V I/O

1.8V CoreB

LM18

PG

600S

N1D

Current flow in

digital and limiting

analog voltages,

controlling jitter

and noise.

If MVCC = 1.8V,

power LED will not

light up.

Install resistor

for 3.3V I/O.

Install resistor

for 2.5V I/O.

Install resistor to

use the 5V-to-1.8V

Regulator for the

1.8V I/O.

Install resistor to

use the 5V-to-1.8V

Regulator for the

1.8V Core.

SC

-OX

210-

A3-0

062.

2

EV

-OX

U21

0 C

ard

: Pow

er D

istri

butio

n

68

Thur

sday

, Nov

embe

r 30,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

5P0V

CC

5P0V

CC

5P0V

CC

3P3V

CC

3P3V

CC

1P8V

DD

5P0V

CC

3P3V

CC

1P8V

DD

5P0V

CC

MV

CC

3P3V

CC

A

3P3V

CC

2P5V

DD

1P8V

DD

2P5V

DD

3P3V

CC

R65

0_12

06R

_120

6

C31

0.00

1uF

C35 0.1u

F

R59

150

C36

0.00

1uF

Q4

BC

R10

8

1

23

U12

LT19

63A

ES

T-2.

5#P

BF

1

2

3

4

VIN

GND

VO

UT

TAB

U11

LMS

1587

IS3.

3NO

PB

3

1

2 4V

IN

GND

VO

UT

TAB

+C

474.

7uF

+C

344.

7uF

D9

GR

EE

N_L

ED

+C

444.

7uF

R63

330

R66

0_12

06R

_120

6

D7

GR

EE

N_L

ED

C37

0.00

1uF

JP7

1X3

3 2 1

C41

0.1u

F

C30 0.1u

F

C40 0.1u

F

R62

0_12

06R

_120

6

+C

4333

uF

R68

DN

I_0_

1206

R_1

206

R67

DN

I_0_

1206

R_1

206

C38

0.00

1uF

+C

324.

7uF

JP6

1X3

3 2 1

C39

0.1u

F

+C

4633

uF

BL2

12

C45

0.1u

F+

C48

33uF

R64

0_12

06R

_120

6

C42 0.1u

F

R60

150

JP8

1X3

3 2 1

U13

LT19

63A

ES

T-1.

8#P

BF

1

2

3

4

VIN

GND

VO

UT

TAB

D8

GR

EE

N_L

ED



Figure 4-7 EV-OXU210 System CPLD (Not Populated)

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CPLD will set all I/O to

inputs when not programmed

with a 90K pull-up. I/O

signals are programmable

to 1.8V, 2.5V, or 3.3V.

System_CPLD

ISP PROGRAMMING

CABLE CONNECTOR

Bypass capacitors placed

near CPLD.

Default setting is to

bypass directly to OXU210

with 0 ohms resistor.

Uninstall the resistors to

use CPLD.

3.3V 12MHz

Oscillator

ECLIPTEK EH1345HSTS-xx.xxxM

OR EQUIVALENT. Use a DIP

socket for this location.

ECLIPTEK EH26 SERIES

OR EQUIVALENT

SC

-OX

210-

A3-

007

2.2

EV

-OX

U21

0 C

ard

: Sys

tem

PLD

78

Thur

sday

, Nov

embe

r 30,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

GP

IO_P

LD2

SP

AR

E_L

ED

2S

PA

RE

_LE

D2_

R

CS

2LC

S3L

SP

AR

E_L

ED

1_R

SP

AR

E_L

ED

1

CLK

_SP

AR

E0

CLK

_SP

AR

E1

CLK

_SP

AR

E2

CLK

_SP

AR

E3

ISP

_TD

I

ISP

_TC

K

ISP

_TD

O

ISP_

TMS

GP

IO_P

LD1

RE

SE

TL

A4

A5

A3

A2

A1

D4

D5

D6

D7

D1

D3

D2

D0

GP

IO3

GP

IO0

GP

IO2

GP

IO1

RE

AD

YL

BE

3B

E2

BE

1

BE

0

OTG

_CS

1LO

TG_R

DL

RD

L

OTG

_IN

TL

AC

K1

CP

LD_I

27C

PLD

_I62

CP

LD_I

73C

PLD

_I77

A18

A19

A17

SD

CK

E0

WR

L

OTG

_DR

Q0

OTG

_DR

Q1

OTG

_AC

K1

DR

Q0

DR

Q1

AC

K0

INTL

OTG

_AC

K0

OTG

_WR

L

CS

1L

DE

BU

G7

DE

BU

G5

DE

BU

G6

DE

BU

G3

DE

BU

G4

DE

BU

G2

DE

BU

G0

DE

BU

G1

CLK

_SP

AR

E0

3P3V

CC

3P3V

CC

MV

CC

3P3V

CC

MV

CC

MV

CC

3P3V

CC

R43

0

V15

1

C72

0.1u

FC

750.

1uF

R53

0

C26

0.1u

F

S1

DN

I_S

WD

IP_4

1234

8765

R42

0

U8

DN

I_H

alf_

size

_DIP

1

4

5

8

EN

GND

OU

T

VCC

R50

DN

I_30

0

R49

10K

R47

0

C73

0.1u

FC

770.

1uF

R45

0

V14

1

R38 D

NI_

56K

x4

1234 5

678

C76

0.1u

F

U7

DN

I_5x

7mm

_sm

_cer

amic

1

2

3

4

EN

GND

OU

T

VCC

C70

0.1u

F

U9 D

NI_

LC40

64V

_75T

N10

0C

3 54 6 8 9 10 14 15 16 17 19 20 21 22 28 34 4729 30 31 35 36 37 41 42 43 44

25

45

71826

1

245227489 38

13

33

3246515768768296

11

637583

95

48 49 50

53 54 55 56 58 59 60 61 64 65 66 67 69 70 71 72 78 79 80 81 84 85 86 87 91 92 93 94 97 98 99 100

12232739 88

40

627377

90

I/O_3

I/O_5

I/O_4

I/O_6

I/O_8

I/O_9

I/O_1

0

I/O_1

4I/O

_15

I/O_1

6I/O

_17

I/O_1

9I/O

_20

I/O_2

1I/O

_22

I/O_2

8

I/O_3

4

I/O_4

7

I/O_2

9I/O

_30

I/O_3

1

I/O_3

5I/O

_36

I/O_3

7

I/O_4

1I/O

_42

I/O_4

3I/O

_44

VCC_25

VCCO_45

GND_7GND_18GND_26

GND_1

TCK

TMS

TDI

TDO

CLK

0/In

0C

LK1/

In1

VCCO_13

VCCO_33

GND_32GND_46GND_51GND_57GND_68GND_76GND_82GND_96

I/O_1

1

VCCO_63VCC_75

VCCO_83

VCCO_95

I/O_4

8I/O

_49

I/O_5

0

I/O_5

3I/O

_54

I/O_5

5I/O

_56

I/O_5

8I/O

_59

I/O_6

0I/O

_61

I/O_6

4I/O

_65

I/O_6

6I/O

_67

I/O_6

9I/O

_70

I/O_7

1I/O

_72

I/O_7

8I/O

_79

I/O_8

0I/O

_81

I/O_8

4I/O

_85

I/O_8

6I/O

_87_

GO

E1

I/O_9

1_G

OE

0I/O

_92

I/O_9

3I/O

_94

I/O_9

7I/O

_98

I/O_9

9I/O

_100

I_12

I_23

I_27

CLK

2/In

2C

LK3/

In3

VCC_40

I_62

I_73

I_77

VCC_90

VCC

SDO/TDO

SDI/TDI

ispEN#

NC/TRST

MODE/TMS

GND

SCLK/TCK0.01uF

J3 DN

I_1X

8

1 2 3 4 5 6 7 8

C74

0.1u

F

TP16

R44

0

C71

0.1u

F

R55

DN

I_30

0

C79

0.1u

F

TP17

D6

DN

I_G

RE

EN

_LE

D

TP15

D5

DN

I_G

RE

EN

_LE

D

R54

0R

460

C78

0.1u

F

CS

2LC

S3L

GP

IO_P

LD2

GP

IO_P

LD1

RE

SE

TL

SD

CLK

0

A[5

:1]

D[7

:0]

GP

IO3

GP

IO2

GP

IO1

GP

IO0RE

AD

YL

BE

[3:0

]

A[1

9:17

]

SD

CK

E0

RD

LW

RL

INTL

DR

Q0

DR

Q1

AC

K0

AC

K1

OTG

_RD

LO

TG_W

RL

OTG

_IN

TL

CS

1L

OTG

_DR

Q0O

TG_D

RQ

1 OTG

_AC

K0

OTG

_AC

K1

OTG

_CS

1L

DE

BU

G[7

:0]



Figure 4-8 EV-OXU210 USB Ports

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Place resistors at

OXU210 chip and as

close together as

possible

USB Connectors

By default, R6 is

installed to use the

TPS2044B, 500mA external

charge pump. Or, install

R5 to use the 100mA

internal charge pump.

Only install one resistor

at a time.

Jumper 1-2: Host only mode.

Jumper 2-3: OTG mode.

CDR105NP-270MC

Install 180pF and 100-ohm

when using 2SD1119 NPN

Transistor instead of the

N-MOSFET.

Place 0.3" apart

in parallel to

ind footprint.

U2 and Q2 are not needed

for OXU210 designs and

can be deleted.

SC

-OX

210-

A3-

008

2.2

EV

-OX

U21

0 C

ard

: US

B C

onne

ctor

s

88

Tues

day,

Dec

embe

r 05,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

DP

HO

ST

P4_

OU

T

EX

T_V

BO_N

_LS

EXT

_VBO

_N

EN

3_N

P4_

1

P4_2

DM

HO

ST_

R

VB

US

IDID

VD

VB

US

2

VD

VB

US

1

P1_

OU

T

P4_

1

DM

OTG

DP

OTG

DM

HO

ST

DP

HO

ST_

R

DP

OTG

_RD

MO

TG_R

US

B_5

V_P

1

OTG

_VB

US

2O

TG_V

BU

S3

OTG

_EXT

_R

US

B_5

V_P

2

5P0V

CC

3P3V

CC

5P0V

CC

5P0V

CC

3P3V

CC

5P0V

CC

5P0V

CC

+C

810

uF/1

6V

TP4

C50

0.1u

F

R9

0

B L5

12

U15

MAX

3207

EAU

T

1 4

2 3 65IO

_A

IO_B

GN

DN

C3

NC

6

VC

C

JP4

1X3

32

1

R1

330

US

B_T

YP

E-A

J5

321 4 5

D+

D-

+5V

GN

DS

HD

R6

0

C6

0.1u

F

C14

DN

I_18

0pF

U1

TPS

2044

BD

3 4 7 816 13 12 9

10111415

2 6 51

EN

1

EN

2

EN

3

EN

4

OC

1

OC

2

OC

3

OC

4

OUT4OUT3OUT2OUT1

IN1

IN2

GN

D5

GN

D1

D2

GR

EE

N_L

ED

TP1

R4

10K

C49

0.1u

F

R21

0

U14

MAX

3207

EAU

T

1 4

2 3 65IO

_A

IO_B

GN

DN

C3

NC

6

VC

C

TP5

Q3

BS

S13

8/S

OT

3

1 2

Q2

PM

OS

1

2 3

R7

82K

R5

DN

I_0

C1

0.01

uF

C11

0.1u

F

L127

uH

+C

9

4.7u

F/25

V

B

L6

12

U2

AN

D_G

ate

41 2

5 3

TP2

+C

124.

7uF

Q1

PMO

S

1

23

R20

0

R18

0

BL41

2

C4

220u

F

TP3

R2

330

R23

390

C7

220u

F

R3

DN

I_10

K

J4 US

B_M

ini-A

B

321 54 6

D+

D-

+5V

GN

DID S

HLD

D3

MA

2Q73

800L

C3

0.01

uF

+C

533

uF

D1

GR

EE

N_L

ED

R19

0

C2

0.01

uF

B L3

12

D4

BZX

84C

5V1L

T1G

1 23

A NC

C

DM

OTG

DP

OTG

ID DM

HO

ST

DP

HO

ST

EXT

_VBO

_N

OC

_NP

O_N

VB

US

EX

T

PD

_PM

OS

VO

UT



Figure 4-9 PCI104 Top-Level Schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PCI104 BRIDGE CARD TOP LEVEL

PCLK must be 2.5"

in length

GROUND TEST POINTS

Distribute the TestPoints

near top side and corners

MH's are to be .146" non-plated thru holes.

MH's are to be .177" plated thru holes.

These holes are for the PCI front plate mounting.

SC

-PC

I104

-A1-

001

2.0

PC

I104

Car

d: T

op L

evel

15

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

PC

104_

CO

NN

PC

104_

CO

NN

WR

LR

DL

LIN

TI2

LRE

SE

TOL

CS

2L

CS

1L

LA[1

9:2]

RE

AD

YL

AD

SL

LD[3

1:0]

GP

IO[8

:4]

CS

3L

LIN

TI1

LBE

0LLB

E1L

P1_

PC

I_E

dge_

Con

nect

or

PC

I_E

dge_

Con

nect

or

PC

LK

AD

[31:

0]

C/B

E3L

C/B

E2L

IRD

YL

DE

VS

ELL

LOC

KL

PE

RR

L

SE

RR

L

C/B

E1L

VIO

PC

I

C/B

E0L

PA

R

STO

PL

FRA

ME

L

TRD

YL

IDS

EL

RS

TL

INTA

L

PM

EL

P2_

PLX9

030

PLX9

030

LD[3

1:0]

VIO

PC

I

PC

LK

RS

TL

IDS

EL

C/B

E0L

AD

[31:

0]

C/B

E1L

C/B

E2L

C/B

E3L

FRA

ME

L

IRD

YL

TRD

YL

STO

PL

DE

VS

ELL

PE

RR

L

SE

RR

L

LOC

KL

PA

R

INTA

L

PM

EL

AD

SL

RD

LW

RL

RE

AD

YL

LRE

SE

TOL

CS

0L

CS

1L

CS

2L

LIN

TI1

LA[1

9:2]

CS

3L

GP

IO[8

:4]

LBE

0LLB

E1L

LIN

TI2

P6_

Exp

ansi

on_R

OM

Exp

ansi

on_R

OM

XR

OM

_A[1

9:2]

XR

OM

_D[7

:0]

XR

OM

_CEL

XRO

M_O

EL

XR

OM

_WEL

XR

OM

_RES

ETL

LBE

1LLB

E0L

C/B

E2L

VIO

PC

I

AD

[31:

0]

IRD

YL

LOC

KL

PM

EL

C/B

E0L

C/B

E3L

INTA

L

RE

AD

YL

RS

TL

DE

VS

ELL

LRE

SE

TOL

CS

1L

IDS

EL

PA

R

PC

LK

TRD

YL

PE

RR

L

SE

RR

L

AD

SL

CS

2LC

/BE

1L

FRA

ME

L

STO

PL

LIN

TI1

CS

3L

GP

OI[8

:4]

LBE

0L

LA[1

9:2]

LIN

TI2

WR

L

LD4

RD

L

LD3

LD6

LA[1

9:2]

RD

L

LD[7

:0]

LD1

LD5

LD0

WR

L

LD2

LBE

1L

LD7

LD[3

1:0]

CS

0LC

S0L

LRE

SE

TOL

MH

6

MH

4

JP3

1X2

2 1M

H2

MH

1

JP1

1X2

2 1

JP5

1X2

2 1

JP6

1X2

2 1

MH

3

MH

5



Figure 4-10 PCI104 PCI Connector

A A

B B

C C

D D

E E

44

33

22

11

5V to 3.3V VoltageConversion

Deco

up

lin

g C

ap

acit

ors

PRSNT1#

PRSNT2#

Function

GND

OPEN

OPEN

GND

GND

OPEN

OPEN

GND

no adapter board

15W on all rails

25W on all rails

7.5W on all rails

Power Indicators

NEAR VIO_A10

NEAR VIO_A16

NEAR VIO_A59

NEAR VIO_B19

PLACE NEAR CARD EDGE CONNECTOR PINS

PLX9030 VIO PIN

Power Headers

7-8

5-6

3-4

1-2

3.3V Board Power

Taken from PCI Bus

3.3V Board Power

Taken from Regulator

JP

Function

NOTE:

The mating daughtercard must have a

backside keep-out area for

sufficient clearance of the Jumper.

LT1587CM-3.3

2A

max.

PCI Edge Connector

SC

-PC

I104

-A1-

002

2.0

PC

I104

Car

d : P

CI C

ard

Edg

e C

onne

ctor

25

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

VIO

PC

I

3.3V

AU

X

VIO

PC

I

VIO

PC

I

PC

I_P

ME

L

VIO

PC

I

VIO

PC

I

3.3V

AU

X

VD

5

VD

3

PC

I_TD

D

5P0V

CC

AD

25

AD

16

AD

8

AD

12A

D13

AD

30A

D29

AD

6

AD

18

AD

23

AD

1

AD

22

AD

31

AD

26

AD

14

AD

10

AD

0

AD

19A

D21

AD

17

AD

4

AD

7

AD

9

AD

28

AD

24

AD

2

AD

15

AD

11

AD

27

AD

3A

D5

AD

20

3P3V

_CO

NN

3P3V

_S

5P0V

CC

5P0V

CC

3P3V

CC

5P0V

CC

3P3V

PC

I

3P3V

PC

I

3P3V

PC

I

3P3V

PC

I

3P3V

PC

I

5P0V

CC

5P0V

CC

3P3V

CC

5P0V

CC

3P3V

CC

3P3V

CC

3P3V

CC

C56

0.01

uF

TP2

C24

0.01

uF

C19

0.01

uF

C57

0.01

uF

C59

0.04

7uF

C3

0.1u

F

+C

433

uF

C25

0.01

uF

R7

DN

I_24

0K

C22

0.01

uF

C58

0.04

7uF

+C

233

uFC

10.

1uF

3.3V KEY

5.0V KEY

U2

PC

I_32

BIT

_ED

GE

_UN

V

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

B10

A11

B11

A14

B14

A15

B15

A16

B16

A17

B17

A18

B18

A19

B19

A20

B20

A21

B21

A22

B22

A23

B23

A24

B24

A25

B25

A26

B26

A27

B27

A28

B28

A29

B29

A30

B30

A31

B31

A32

B32

A33

B33

A34

B34

A35

B35

A36

B36

A37

B37

A38

B38

A39

B39

A40

B40

A41

B41

A42

B42

A43

B43

A44

B44

A45

B45

A46

B46

A47

B47

A48

B48

A49

B49

A52

B52

A53

B53

A54

B54

A55

B55

A56

B56

A57

B57

A58

B58

A59

B59

A60

B60

A61

B61

A62

B62

TRS

T#-1

2V+1

2VTC

KTM

SG

ND

_B3

TDI

TDO

+5V

_A5

+5V

_B5

INTA

#+5

V_B

6IN

TC#

INTB

#+5

V_A

8IN

TD#

RE

SE

RV

ED

_A9

PR

SN

T1#

VIO

_A10

RE

SE

RV

ED

_B10

RE

SE

RV

ED

_A11

PR

SN

T2#

3.3V

AU

XR

ES

ER

VE

D_B

14R

ST#

GN

D_B

15V

IO_A

16C

LKG

NT#

GN

D_B

17G

ND

_A18

RE

Q#

PM

E#

VIO

_B19

AD

[30]

AD

[31]

+3.3

V_A

21A

D[2

9]A

D[2

8]G

ND

_B22

AD

[26]

AD

[27]

GN

D_A

24A

D[2

5]A

D[2

4]+3

.3V

_B25

IDS

EL

C/B

E[3

]#+3

.3V

_A27

AD

[23]

AD

[22]

GN

D_B

28A

D[2

0]A

D[2

1]G

ND

_A30

AD

[19]

AD

[18]

+3.3

V_B

31A

D[1

6]A

D[1

7]+3

.3V

_A33

C/B

E[2

]#FR

AM

E#

GN

D_B

34G

ND

_A35

IRD

Y#

TRD

Y#

+3.3

V_B

36G

ND

_A37

DE

VS

EL#

STO

P#

GN

D_B

38+3

.3V

_A39

LOC

K#

RE

SE

RV

ED

_A40

PE

RR

#R

ES

ER

VE

D_A

41+3

.3V

_B41

GN

D_A

42S

ER

R#

PA

R+3

.3V

_B43

AD

[15]

C/B

E[1

]#+3

.3V

_A45

AD

[14]

AD

[13]

GN

D_B

46A

D[1

1]A

D[1

2]G

ND

_A48

AD

[10]

AD

[09]

M66

EN

C/B

E[0

]#A

D[0

8]+3

.3V

_A53

AD

[07]

AD

[06]

+3.3

V_B

54A

D[0

4]A

D[0

5]G

ND

_A56

AD

[03]

AD

[02]

GN

D_B

57A

D[0

0]A

D[0

1]V

IO_A

59V

IO_B

59R

EQ

64#

AC

K64

#+5

V_A

61+5

V_B

61+5

V_A

62+5

V_B

62JP

73 2 1

U1

LMS

1587

IS-3

.3

31

2 4V

INGND

VO

UT

TAB

R9

DN

I_24

0K

JP4

3 2 1

TP3

R5

300

C32

0.01

uF

C36

0.01

uF

C11

0.01

uF

+C

56.

8uF

C41

0.01

uF

C23

0.04

7uF

C7

220

uF

R4

150

C42

0.01

uF

R8 10K

C13

DN

I_0.

1uF

C35

0.01

uF

D1

GR

EE

N2

1

U6

DN

I_FD

N33

5N

3

1 2D

rain

Gat

e

Sou

rce

C10

0.01

uF

TP1

D2

GR

EE

N2

1

C43

0.01

uF

C62

0.01

uF

CF1

0.02

2uF

C61

0.04

7uF

C63

0.01

uF

C48

0.01

uF

C18

0.01

uF

R6

0

C50

0.01

uF

C21

0.01

uF

C60

0.01

uF

JP2

2X4

21

4357

8 6

PC

LK3 A

D[3

1:0]

3

C/B

E3L

3

C/B

E2L

3

IRD

YL

3

DE

VS

ELL

3

LOC

KL

3P

ER

RL

3

SE

RR

L3

C/B

E1L

3

C/B

E0L

3

PA

R3

STO

PL3

FRA

ME

L3

TRD

YL

3

IDS

EL

3

RS

TL3

INTA

L3

PM

EL3

VIO

PC

I3



Figure 4-11 PCI9030 Bridge Chip

A A

B B

C C

D D

E E

44

33

22

11

JTAG Port

- PIN 76 (MODE) GROUNDED = non-multiplexed bus mode

- PIN 112 (BD_SEL_TEST) pulled low = outputs remain in

normal operation and PCI Hot Swap precharge resistors

are not active.

De

co

up

lin

g C

ap

ac

ito

rs

+ XROM CHIP SELECT = CS0L

+ OTG243 CHIP SELECT = CS1L

+ ispLSI CHIP SELECT = CS2L

+ spare = CS3L

LOCAL DATA BUS

LOCAL ADDRESS BUS

SYSTEM DATA BUS

BCLK0 must be 2X

the length CS1L

NOTE:

All other signals going to the PC104

connector must be pulled-up on

the daughtercard.

ECLIPTEK EC28 SERIES

OR EQUIVALENT

Place near PLX9030.

Remove when using

external oscillator.

Place near BCLKO_R

resistor and near OSC

Option to run local bus

up to max of 60MHz

DIP8 Socket

for 93CS66

1

PLX9030

SC

-PC

I104

-A1-

003

2.0

PC

I104

Car

d : P

LX90

30 P

CI I

nter

face

and

EE

PR

OM 3

5Tu

esda

y, O

ctob

er 1

7, 2

006

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

PR

E

BTE

RM

LR

EA

DY

LLW

/RL

PE

TMS

LA21

GP

IO6

AD

11

LRE

QAD

0

AD

14

AD

18

LBE

0L

MO

DE

GP

IO0/

WA

ITO

L

TDI

LA22

AD

8

AD

16

AD

28

AD

31

LA23

AD

13

AD

22

EN

UM

L

BC

LKO

EE

SKA

D29

LPM

ESET

AD

9

AD

26

AD

30

LBE

3L

EE

CSA

D24

EE

DOA

D1

ALE

GP

IO7

AD

23

AD

4

AD

17

LBE

2L

TEST

TRS T

L

AD

10

AD

12

TDO

AD

3

GP

IO1/

LLO

CK

OL

GP

IO4

AD

25

AD

27

BLA

STL

AD

19A

D20

GP

IO5

AD

7

AD

21

AD

6

LA20

AD

2

AD

5

AD

15

TCK

LW/R

L

BTE

RM

L

EE

DI

LED

ON

L

LD1

LD27

LA9

LD12

LD16

LD14

LD15

LA5

LA8

LD19

LD23

LD4

LD28

LA6

LA18

LD25

LD6

LD0

LD24

LA16

LD2

LD9

LD13

LD29

LA4

LD8

LA12

LD7

LA10

LA14

LD10

LA3

LD20

LD17

LD22

LD21

LA17

LD3

LA7

LA15

LD26

LD30

LA19

LD18

LA13

LD31

LA11

LD11

LA2

LD5

CP

CIS

W

LGN

T

GP

IO8

BC

LKO

_R

BLA

STL

GP

IO0/

WA

ITO

L

ALE

GP

IO1/

LLO

CK

OL

LGN

TLR

EQ

GP

IO5

GP

IO4

GP

IO6

GP

IO7

LA21

LA23

LA22

LA20

GP

IO8

LBE

1L

LIN

TI2

LIN

TI1

CS

0LC

S1L

CS

2LC

S3L

BC

LKO

LBE

2LLB

E1L

LBE

0L

LBE

3L

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

C28

0.1u

F

R31

150

R17

10K

R1

10K

C34

0.01

uF

R18

10K

C31

0.01

uF

PC

I S

ign

als

PC

I S

ign

als

PC

I S

ign

als

PC

I S

ign

als

PC

I S

ign

als

PC

I90

30

U7

PLX9

030-

176P

QFP

152

144

143

151

139

154

150

153

138

142

158

172

140

160

161

171 8

112

145 76

149

60 59 58 55

51169

10 155

56

52173

174

175

23416171830333435363738394142434647484950 5

4532

85

101100

70

13

117133

31

162

170

57

111215 9 28

66

44

6

78

257

88

2019

113

22

122

21

132

29

146

2440 23

128

26 27

137

136

135

13484 131

130

12995 127

125

124

12393 12192 120

119

118

11691 115

114

11190 110

109

108

10789 106

10587 86 83 81104 80102 7999 98 7797 96 74 73 72 69 68 6782 65 64 63 62 61

114

163176

159

165

166

168

164

167

53

75 141

94

147

148

157

156

54 71

103

126

LIN

Ti1

BTE

RM

#

RE

AD

Y#

LRE

Q

BLA

ST#

GP

IO0/

WA

ITo#

LGN

T

LIN

Ti2

AD

S#

LW/R

#

EE

CS

PC

LK

WR

#

EE

SK

EE

DI

RS

T#ID

SE

L

BD

_SE

L_TE

ST

LCLK

MO

DE

LRE

SE

To#

LBE

0#LB

E1#

LBE

2#LB

E3#

EN

UM

#P

ME

#

AD

22

GP

IO1/

LLO

CK

o#

VDD

LED

on#

AD

31A

D30

AD

29A

D28

AD

27A

D26

AD

18A

D17

AD

16A

D15

AD

14A

D13

AD

12A

D11

AD

10A

D9

AD

8A

D7

AD

6A

D5

AD

4A

D3

AD

2A

D1

AD

0

AD

25

VDDVDD

VDD

VSSVDD

VDD

VSS

VDDVDD

VSS

VDD

INTA

#

VSS

AD

21A

D20

AD

19

AD

23

PA

R

VSS

VSS

AD

24

VSS

LOC

K#

C/B

E3#

VSS

FRA

ME

#

C/B

E2#

VSS

TRD

Y#

VSS

IRD

Y#

VSS

C/B

E1#

VSS

STO

P#

C/B

E0#

DE

VS

EL#

LA20

PE

RR

#S

ER

R#

LA27

/GP

IO4

LA26

/GP

IO5

LA25

/GP

IO6

LA24

/GP

IO7

LD14

/LA

D14

LA23

LA22

LA21

LD6/

LAD

6

LA19

LA18

LA17

LA16

LD7/

LAD

7

LA15

LD8/

LAD

8

LA14

LA13

LA12

LA11

LD9/

LAD

9

LA10

LA9

LA8

LD10

/LA

D10

LA7

LA6

LA5

LA4

LD11

/LA

D11

LA3

LA2

LD12

/LA

D12

LD13

/LA

D13

LD15

/LA

D15

LD17

/LA

D17

LD0/

LAD

0

LD18

/LA

D18

LD1/

LAD

1

LD19

/LA

D19

LD2/

LAD

2LD

3/LA

D3

LD20

/LA

D20

LD4/

LAD

4LD

5/LA

D5

LD21

/LA

D21

LD22

/LA

D22

LD23

/LA

D23

LD24

/LA

D24

LD25

/LA

D25

LD26

/LA

D26

LD16

/LA

D16

LD27

/LA

D27

LD28

/LA

D28

LD29

/LA

D29

LD30

/LA

D30

LD31

/LA

D31

VDDVDD

VSSVSS

EE

DO

TCK

TMS

TDI

TRS

T#TD

O

VI/O

ALE

RD

#G

PIO

8

CS

0#C

S1#

GP

IO3/

CS

3#G

PIO

2/C

S2#

CP

CIS

W

BC

LKo

LPM

ES

ET

LPM

INT#

C33

0.1u

F

J4 1X6

1 2 3 4 5 6

1 2 3 4 5 6

R28

10K

R11

0

C40

0.01

uF

C54

0.1u

F

C53

0.01

uF

R23

10K

R12

1K

C15

0.1u

F

D3G

RE

EN

21

R29

DN

I_10

K

R14

10K

C39

0.1u

F

C47

0.01

uF

C9

0.1u

F

C44

0.1u

F

RN

4 4x10

K

12345 6 7 8

R19

10K

U5

DN

I_5x

7mm

_sm

_cer

amic

1

2

3

4

EN

GND

OU

T

VCC

R13

10K

U3

93C

S66

1 2 3 4

8 7 6 5

CS

SK

DI

DO

VC

CP

RE

PE

GN

D

R26

10K

RN

2 4x10

K

12345 6 7 8

TP4

R22

10K

C37

0.1u

FC

270.

1uF

RN

3 4x10

K

12345 6 7 8

RN

1 4x10

K

12345 6 7 8

C29

0.01

uF

C26

0.1u

F

R3

10K

R21

10K

R15

10K

R27

10K

C52

0.1u

F

R2

DN

I_10

K

R10

DN

I_33

C30

0.01

uF

R24

10K

RN

5 4x10

K

12345 6 7 8

C49

0.1u

FC

460.

1uF

R20

DN

I_10

K

C45

0.01

uF

U4

DN

I_H

alf_

size

_DIP

1

4

5

8

EN

GND

OU

T

VCC

R25

DN

I_10

K

C55

0.01

uFC

510.

01uF

R16

10K

R30

10K

C38

0.01

uF

LD[3

1:0]

4,5

PC

LK2

RS

TL2

IDS

EL

2

C/B

E0L

2

AD

[31:

0]2

C/B

E1L

2C

/BE

2L2

C/B

E3L

2

FRA

ME

L2

IRD

YL

2TR

DY

L2

STO

PL2

DE

VS

ELL

2

LOC

KL

2P

AR

2IN

TAL

2PM

EL2

AD

SL

4

RD

L4,

5W

RL

4,5

RE

AD

YL

4

LRE

SE

TOL

4,5

CS

0L5

CS

1L4

CS

2L4

LIN

TI1

4

LA[1

9:2]

4,5

SE

RR

L2

PE

RR

L2

VIO

PC

I2

CS

3L4

GP

IO[8

:4]

4

LBE

0L4,

5LB

E1L

4,5

LIN

TI2

4



Figure 4-12 PC104 Connectors

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Place at connector pins

Place at connector pins

3M Female Conn: 929975-01-20

3M Female Conn: 929975-01-32

3M Female Conn: 929975-01-20

Extra Connector, Non-PC104 Standard

IRQ9 - GPIO7

IRQ10 - LINT1

IRQ11 - GPIO8

IRQ12 - CS3L

IRQ15 - CS1L

IRQ14 - CS2L

PCI104 Connector

SC

-PC

I104

-A1-

004

2.0

PC

I104

Car

d: P

C10

4 C

onne

ctor

s

45

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

IOC

HC

HK

_N

IRQ

4

EN

DX

FR_N

IOW

IOR

UC

LK

OS

C

KE

Y2

ME

MC

S16

_NIO

CS

16_N

IRQ

7IR

Q6

IRQ

5

IRQ

3

LD6

LD12

LD13

LD15

LD11

LD10

LD9

LD7

LD8

LD14

LD4

LD5

LD3

LD2

LD16

LD21

LD17

LD22

LD23

LD18

LD19

LD20

LD28

LD24

LD29

LD30

LD25

LD26

LD27

LD31

LA8

LA19

LA15

LA2

LA18

LA11

LA9

LA12

LA7

LA14

LA17

LA4

LA5

LA13

LA3

LA6

LA10

LA16

GP

IO8

GP

IO6

GP

IO4

GP

IO5

GP

IO7

LD1

LD0

MA

STE

R_N

AE

N

5P0V

CC

3P3V

CC

3P3V

CC

5P0V

CC

V19

1

J2P

C10

4-64

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

+C

86.

8uF

V7

1

V20

1

V18

1

C14

0.1u

F

V1

1

V6

1

V12

1

C17

0.1u

F

V16

1

+C

166.

8uF

V3

1

J3P

C10

4-40

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

V15

1

V5

1

V2

1

V11

1

C12

0.1u

FC

60.

1uF

V9

1

J1P

C10

4-40

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

V14

1

V4

1

V13

1

V17

1

V8

1

V10

1

WR

L3,

5R

DL

3,5

LRE

SE

TOL

3,5

CS

2L3

CS

1L3

AD

SL

3

LD[3

1:0]

3,5

LA[1

9:2]

3,5

RE

AD

YL

3

GP

IO[8

:4]

3

CS

3L3

LIN

TI1

3

LIN

TI2

3

LBE

1L3,

5LB

E0L

3,5



Figure 4-13 PC104 Expansion ROM

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

14

5 13

14

20

21

29

30

32

PLCC-32

SOCKET

LOCAL BUS CHIP SELECT 0

LOCAL BUS READ, WRITE AND RESET

Expansion ROM

SC

-PC

I104

-A1-

005

2.0

PC

I104

Car

d : P

CI E

xpan

sion

Boo

t FLA

SH

RO

M

55

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

XRO

M_D

0XR

OM

_D1

XRO

M_D

2XR

OM

_D3

XRO

M_D

4XR

OM

_D5

XRO

M_D

6XR

OM

_D7

XRO

M_A

2XR

OM

_A3

XRO

M_A

5XR

OM

_A4

XRO

M_A

6

XRO

M_A

8XR

OM

_A7

XRO

M_A

9

XRO

M_A

11XR

OM

_A10

XRO

M_A

12

XRO

M_A

14XR

OM

_A13

XRO

M_A

15

XRO

M_A

17XR

OM

_A16

5P0V

CC

5P0V

CC C

200.

1uF

U8

DN

I_A

T49F

002N

-55J

C

12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30

13 14 15 17 18 19 20 21

22 24 31

32 161

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

CE

OE

WE

VC

C

GN

DR

ES

ET

TP5

XR

OM

_D[7

:0]

3,4

XR

OM

_CEL

3

XRO

M_O

EL3,

4

XRO

M_W

EL3,

4 XR

OM

_RES

ETL

3,4

XR

OM

_A[1

9:2]

3,4

LBE

0L3,

4LB

E1L

3,4

EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide

Documents

Transcript of EV-OXU210-PCI and EV-OXU210 Evaluation Board User Guide