Public

EUV: Status and Challenges AheadInternational Workshop on EUVL, Maui 2010

Jos Benschop

PublicSlide 2 |

Agenda

• Roadmap• Status• Challenges• Summary & conclusion

PublicSlide 3 |

IC & Lithography roadmap towards <10nm

Year of production start

Res

olut

ion

(hal

f pitc

h) "

Shrin

k" [n

m]

8

20

30

405060

80

200

10

100

ArF

ArF

iEU

V

02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19

KrF

DPT

Notes: 1. R&D solution required 1.5~ 2 yrs ahead of Production2. EUV resolution requires 7nm diffusion length resist3. DPT = Double Patterning

Source: Customers, ASML, 05/10

DRAM

NAND

LOGICXT:1900i

XT:1400XT:1700i

AT:1200

NXT:1950i

DPT

DPT²NXE:3350

EUV-ADT

DPT

NXE:3100 NXE:3300

Logic / SRAM

6 Transistor SRAM Cell

k1 0.40 ~ 0.44DRAM

k1 0.30 ~ 0.35

NAND Flash

k1 0.27 ~ 0.30

PublicSlide 4 |

Likely lithographic optionsk1 = (half-pitch) * numerical aperture / wavelength

NAλ (nm)

Most likelyOpportunityChallenge

201520132011200920072005Year 2017

7111522324565Half pitch (nm)

0.45

0.32

0.2513.5

1.35

1.20

0.93193

0.370.50

0.360.52

0.41

0.150.220.310.280.40

0.31

Double (Double) patterning, DP: CoO challenge

Low k1 > 0.25challenge

0.10

DP, k1 > 0.125 DP², k1 > 0.0625

0.70 0.36

2019

5

0.26

6.8nm?

Infrastructure challenge

0.31

PublicSlide 5 |

Litho costs back to normal with EUV >100 W/hrLi

tho

cost

per

waf

er [a

.u.]

Source Samsung, Litho Forum, New York, May 2010

3.5

3

2.5

2

1.5

1

0KrF set 1400 set 1900i set 1900i DPT 1900i DPT EUV

100W/hrEUV

180W/hr

0.5

DPT case, Litho costincreases 2 ~ 3 times

EUV case, Litho costtrend returns

1st Gen.DTP

2st Gen.DTP

PublicSlide 6 |

Source TSMC, Prague 2009

EUV is the only feasible litho technology for foundriesEnabling cost effective shrink to 2x node without design restriction

Single layer pattering cost target

2009 2010 2011 2012 2013

2.5

2.0

1.5

1.0

0.5

Rel

ativ

e 2x

nm

nod

e lit

ho c

ost

per w

afer

DP

DDL

SP

EUVDDL, Double Dipole Lithography, Extreme low k1 imaging at relaxed half pitch using double exposure and extreme SMO. Best cost but major design restrictions and not the most aggressive shrink

DP, Double Patterning, good shrink, cost too high and design restrictions.

EUV: the best balance between cost, shrink and absence of design restrictions, however major technology adoption hurdle

Year

PublicSlide 7 |

EUV can increase the fab capacityLarger footprint required to support Multi Patterning schemes

1200 m2 clean room130k Wafers / Month

Spacerdouble

patterningEUV

627 m2 clean room OR250k Wafers / Month

StripCVD

TrackEtchNXT EUV

PublicSlide 8 |

EUV has come a long way in last 25 years

'85 '86 '87 '88 '89 '90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04 '05 '06 '07 '08 '09 '10

NL:

5 μm

USA:

40 nm hp

70nmL&S

1st papers soft X-ray for lithography(LLNL, Bell Labs)

ASML start EUVL research program

•ASML has active program since 1997. •Currently ~1000 people work on pre-production system to be shipped 2010.

Japan:

80nm

160nm

ASML pre-production tools plannedshipment

ASML ships 2 alpha tools to IMEC (Belgium) and CNSE (USA)

NL:

40 nm hp28 nm Lines and spaces

PublicSlide 9 |

… and much more to come in the next few years

* Requires <7 nm resist diffusion length

2006 2010 2012 2013Proto System NXE:3100 NXE:3300B NXE:3300C

Resolution 32 nm 27 nm 22 nm 16* nm

NA / σ 0.25 / 0.5 0.25 / 0.8 0.32 / 0.2-0.9 0.32 / OAI

Overlay (SMO) < 7 nm < 4.5 nm < 3.5 nm < 3 nm

Throughput W/hr 4 W/hr 60 W/hr 125 W/hr 150 W/hr

Dose, Source 5 mJ/cm2, ~8 W 10 mJ/cm2, >100 W 15 mJ/cm2, >250 W 15 mJ/cm2, >350 W

Main improvements1) New EUV platform: NXE 2) Improved low flare optics 3) New high sigma illuminator4) New high power source5) Dual stages

Main improvements1) New high NA 6 mirror lens2) New high efficiency illuminator3) Off-axis illumination optional4) Source power increase5) Reduced footprint

Platform enhancements1) Off-Axis illumination2) Source power increase

PublicSlide 10 |

NXE:3100/ANXE:3300/BNXE:3300/CNXE:3300/D

Source Power, Resist Sensitivity, Transmission, StagesAll need to increase over time to meet user cost targets

22nm dense lines12.8mJ/cm2, 4.3nm LWR MET, Intel Younkin et al, EUVS, Prague 2009

020

4060

80100

120140

160180

200

0 5 10 15 20 25 30 35 40Dose [mJ/cm2]

Thro

ughp

ut [w

ph]

3100A

33x0

B

> 100 W

> 350 W

> 500 W

Expected practical productivity roadmap from A→D

Proto status5wph/5mJ/cm2

> 250 W

C

D

>50% transmission increase

PublicSlide 11 |

Agenda

• Roadmap• Status

• Alpha Demo tool• NXE:3100

• Challenges• Summary & conclusion

PublicSlide 12 |

2 Alpha-demo tools used by multiple customers since 2006

λ 13.5 nm NA 0.25Field size 26 x 33 mm2

Magnification 4x reductionSigma 0.5

• 300mm Single stage• linked to track• Single reticle load• Uses TWINSCAN technology• Sn discharge source

PublicSlide 13 |

0.25NA Systems producing >3000 R&D wafersand number of wafers per month continues to improve

~50 wafers/month

100 wafers/month

250 wafers/month

Device feasibilityResist workMask work

Resolution testingResist work

0

500

1000

1500

2000

2500

3000

3500

4000

Jan-

08

Jul-0

8

Jan-

09

Jul-0

9

Jan-

10

Cum

ulat

ive

# w

afer

s ex

pose

d

PublicSlide 14 |

Overlay performance supports device integration

On-product Overlay ResidualsX = 8.0 nm, Y = 7.8 nm

Single Machine OverlayX = 2.2 nm, Y = 2.8 nm

Freq

uenc

y

300

200

100

0

6543210-1-2-3-4-5-6

Freq

uenc

y

300

200

100

0

source: Global Foundries

Error X Error Y

PublicSlide 15 |

EUV has demonstrated superior imaging compared to 193

PublicSlide 16 |

NAND word line connectivity area down to 26 nmStaggered and slot contacts

30 nm L/S 28 nm L/S 27 nm L/S 26 nm L/S

in cooperation with IMECMask funded by EU EXEPT program

PublicSlide 17 |

NXE:3100 is the 1st generation of the NXE platform

• NA=0.25• Sigma=0.8 • Resolution 27 nm• SMO=4.5 nm• MMO=7.0 nm• Productivity

60wph at 10mJ/cm2 resist

PublicSlide 18 |

Status Integration Oct. 2009

PublicSlide 19 |

3 NXE:3100 systems: Integration, Early Access and 1st Output

System completedSource being installed

System completedArF source used for integration andqualifyingoverlay, S/W, TPT

Wafer Stage installedOptics installedReticle Stage JuneSource June1st ship H2 2010

NXE:3100 #1 NXE:3100 #2 NXE:3100 #3

PublicSlide 20 |

3 more NXE:3100 in build-up, 2 additional cabins

NXE:3100 #4 NXE:3100 #5 NXE:3100 #6

PublicSlide 21 |

Reliability Testing Progressing

0

100

200

300

400

500

600

700

800

90010

00

1001

1002

1003

1004

1005

1006

1007

1008

1009

1010

1011

1012

1013

1014

1015

1016

1017

1018

1019

1020

1021

Num

ber o

f Cyc

les

0

500

1000

1500

2000

2500

3000

3500

4000

Num

ber o

f Chu

ck S

wap

s

Wafer Exchange RetEx in Air RetEx in vacuumWafermap Wafers Chuck Swaps

• 300 wafers cycled• Bottom module MTBI=5hrs• Chuck swap MTBI = 185 swaps• RetEx testing now in vacuum

PublicSlide 22 |

Wafer Stage Integration in vacuumFocus Control and Leveling verified

Reproducibility 99.7 %5.5 nm

0 1 2 3 4 5 6Standard dev. per point [nm]

Dis

tribu

tion

[au]

PublicSlide 23 |

Wafer Stage Integration in vacuumAlignment and Overlay readout verified

-1

-0.5

0

0.5

1

0 25 50 75 100 125 150 175 200# of measurement

alig

nmen

t rep

ro [n

m]

repro Xrepro Y Overlay Readout

2nd to 1st

x= 12 nm y= 9 nm

PublicSlide 24 |

Agenda

• Roadmap• Status• Challenges

• Critical issues• Extension of Shrink roadmap

• Summary & conclusion

PublicSlide 25 |

Critical issues EUV 2005-2009

2005 / 32hp 2006 / 32hp 2007 / 22hp 2008 / 22hp 2009 / 22hp1. Resist resolution,

sensitivity & LER met simultaneously

1. Reliable high power source & collector module

1. Reliable high power source & collector module

1. Long-term source operation with 100 W at IF and 5MJ/day

1. MASK

2. Collector lifetime 2. Resist resolution, sensitivity & LER met simultaneously

2. Resist resolution, sensitivity & LER met simultaneously

2. Defect free masks through lifecycle & inspection/review infrastructure

2. SOURCE

3. Availability of defect free mask

3. Availability of defect free mask

3. Availability of defect free mask

3. Resist resolution, sensitivity & LER met simultaneously

3. RESIST

4. Source power 4. Reticle protection during storage, handling and use

4. Reticle protection during storage, handling and use

• Reticle protection during storage, handling and use

• EUVL manufacturing integration

Reticle protection during storage, handling and use

5. Projection and illuminator optics quality & lifetime

5. Projection and illuminator optics quality & lifetime

• Projection / illuminator optics and mask lifetime

Projection and illuminator optics quality & lifetime

PublicSlide 26 |

Mask critical issues

• Make a defect free mask• Maintain a defect free mask

• Avoid contamination• Inspection• Cleaning

PublicSlide 27 |

Protection during shipping-handling• MIRAI Selete and Sematech showed (SPIE 2008) that

dual-pod handling system is very effective in preventing contamination during handling/shipping: ~0.1 particles/reticle average for lifetime use.

• However potential risk of contamination during exposure

Lifetime use defined as a round-trip shipment, vacuum, pump-vent, and accelerated storage test, at 53nm PSL equivalent inspection capability.

PublicSlide 28 |

PublicSlide 29 |Slide 29 |

1 Source: Hoya, Samsung EUV conference april 20102 Source: KLA, EUV symposium Prague, October 2009

Optical inspection able to detect phase defects 3.4 nm x 45.4 nm in size²

Mask infrastructure improvements: blanks & inspectionMulti-layer Ultra Low Expansion blank defects approaching quartz performance¹

350

300

250

200

150

100

50

0Q2’08 Q4’08 Q2’09 Q1’10 ML/QZ

Def

ect c

ount

s

ML/ULE

50 nm@M736060 nm@M1350H

1/10

PublicSlide 30 |

PublicSlide 31 |

Reticle contamination: overview of the challange• Mask Substrate (ULE, 6mm)+ Multilayer mirror (Mo/Si-Ru

capped, ~200nm) + Absorber (e.g.,TaN/TaNO, 50-70nm)

• Particles organics, Al, Fe (steel), Zn, Sn, Ni, Ti, Cu, oxides of previous metals, ceramics, ML, absorber, … (?)

• Any shape, any size > 25nm (@22nm node)

• Topography Ridges, trenches, contact holes, periodic/non-periodic patterns

Substrate

ML

Absorber

organicinorganic

metallic

PublicSlide 32 |

Cleaning challenges/issues• Smaller particles are more difficult to

removeAdhesion force ~ RApplied cleaning force ~R2

• Challenge: remove particles without damage

• Standard off-line wet cleaning:• Can clean as far as it can be inspected

(~40nm) • Number of cleanings is limited (slight

damage from chemicals)• Not vacuum compatible difficult to

integrate into scanner

• Challenge: dry, local, vacuum-compatible cleaning technique for integration in EUV tool

• Laser Shockwave Cleaning

R

Force

Multi-stage wet (/dry) cleaning – megasonics / plasma

PublicSlide 33 |

Laser Shockwave Cleaning

• Dry, contact-free method of cleaning• Local cleaning possible very fast!• Vacuum operation theoretically possible• The shockwave produced by the Laser-

Induced Breakdown (LIB) from a high-energy pulse in air provides the necessary cleaning force

MIX 40-100nm PSL on Silicon wafer

Removal efficiency

>120nm 100%>60nm 98%>40nm 95%

Before cleaningAfter cleaning

Cleaning area

Cleaning from real EUV reticle

PublicSlide 34 |

Source critical issues

• Power• Burstlength (>400 msec), duty cycle (80%), uptime• Cleanliness• Cost (initial cost, operational cost)

PublicSlide 35 |

2 different source concepts pursued: LPP vs DPP

• Laser-Produced Plasma source

• CO2 laser• Sn droplet target• Debris mitigation using background

gas and/or magnetic fields• Near normal multilayer collector• Pursued by: Gigaphoton, Cymer

• Discharge Produced Plasma source

• Direct conversion electricity => plasma

• Sn liquid• Debris mitigation by set of foils • Grazing incident collector• Pursued by Ushio

Many kWlaser

Near normal Multilayer collector

GrazingRu coated collector

Foil trap

Sn coatedRotating disc

Sn droplets

plasma plasma

PublicSlide 36 |

3 suppliers demonstrated steady progress However further increase of power is required

C. Wagner et al SPIE 2010

0

50

100

150

200

250

300

SPIE09 Prague 09 SPIE10 end 2010 HVM

publ

ic e

xpos

e po

wer

s

Roadmaps shownat SPIE 2010enable 125wphat 15mJ/cm2

~2x power to go

PublicSlide 37 |

EUV increase by more power and/or increased CECE improvement is strongly preferred way

By “power knob” turning:

By CE gain (3x)

PublicSlide 38 |

Collector lifetime must be ensured also at higher power levels

Lifetime demonstration of 1000x is needed

Maintaining debris suppression with power scaling of up to 100x is necessary

PublicSlide 39 |

Resist critical issues

• Resolution• Line edge roughness• Sensitivity

PublicSlide 40 |Slide 40 |

Resist progress supports 16 nm resolution for NXE:3300Calibrating champion 0.25NA full field and 0.3NA small field data

0.00

0.50

1.00

1.50

2.00

2.50

15 20 25 30Lines and Spaces (half pitch) [nm]

Imag

e co

ntra

st (l

ogar

ithm

ic: b

lurr

ed N

ILS)

24nm dense lines NA=0.25, σ=0.5LER 4.4nmDose 19mJ/cm2February 2010

20nm dense lines NA=0.30Oct 2009

2010

2009

2008

MET 0.30NAADT 0.25NA/0.5σNXE:3100 0.25NA/0.8σNXE:3300 0.32NA/0.9σNXE:3300 0.32NA/dipole

Source: 20nm data, Intel, EUVS, Oct 2009

PublicSlide 41 |

Resolution and resist blur

• Resist blur degrades the projected image and limits resolution.• Current lowest blur values (6-10nm) need reduction to less than

5nm to approach tool’s optical limits.

assumption: 0.9/0.2 Quasar, 3% flare, 3nm MSDxy

Printing limit can be estimated using a blurred image NILS cutoff, e.g. NILS=0.6 or 6% max dose latitude.

PublicSlide 42 |

Shot noise limitations and resist

• Small features are imaged with relatively few photons; Statistical fluctuations create an effective dose variation.

• Resist can help by better absorbing the light.

20mJ/cm2

))*exp(1(****67.0# RTDillBfactorimagedoseareaholephotons −−=hole aspect ratio fixed at 2.5

PublicSlide 43 |

Agenda

• Roadmap• Status• Challenges

• Critical issues• Extension of Shrink roadmap

• Summary & conclusion

PublicSlide 44 |

Extendibility of EUV down to sub 5 nm possibleincreasing apertures up to 0.7, wavelength reduction down to 6.8 nm

using 13 nm compatible optics with depth of focus as the major challenge

Year

Res

olut

ion,

Dep

th o

f foc

us [n

m]

0

5

10

15

20

25

30

35

40

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

k-fa

ctor

, Ape

rture

k-factor@13 nm Aperture@13 nmk-factor@6.8 nmAperture@6.8 nm

ResolutionDOF@13 nmDOF@6.8 nm

PublicSlide 45 |

6.x nm wavelength would enable further shrinkand/or increase depth-of-focus• Shorter wavelengths have been investigated for lithography and other applications

(e.g. water window microscopy).• Criteria are

• coating bandwidth and reflectivity• In-band source power, • resist sensitivity

• Measured source and coating performance

44.3% reflectivity is achieved78% is theoretically possible

Achieved CE (in tool band) is 1.8%.Further improvement to 3-5% is feasible

PublicSlide 46 |

EUV extendibility possible beyond 10 nm resolutiontrough increase the apertures up to 0.7

•0.5•0.35

Unobscured Central obscuration

•0.7Apperture

•0.25

6 mirror 6 mirror 8 mirror 6 mirror 8 mirror

Reference: W.Kaiser et al, SPIE 2008 6924-4

PublicSlide 47 |

Summary and conclusions

• EUV considered as the only cost effective way to continue Moore’s Law.

• EUV has come a long way• 2 Alpha Demo tools used by customers since 2006• First tools on new production platform integrated and

planned to ship before end 2010

• No new critical issues have surfaced which is good.• Progress is steady however much more needs to be

done in area of mask, source and resist.

PublicSlide 48 |

Acknowledgements

The work presented today, is the result of hard work and dedication of teams at ASML and many technology partners worldwide including our customers

Special thanks to Vadim Banine, Steve Hansen and Luigi Scaccabarozzi for providing input to this presentation.