ESA’s approach to quality control of the supply … › mews › jp › 27th › data ›...

ESA’s approach to quality control of the supply chain for PCBs

Stan Heltzel European Space Agency

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Outline

A. ESA‘s approach to supply chain control for PCBs

B. Case study: contamination in PCBs 1. Problem description

2. Risk mitigations

27th MEWS Tsukuba, Japan 23, 24 Oct 2014

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PCB manufacturer ESA

Equipment manufacturer

Procurement: DR + MRR, Test, NCR

Qualification: Test, Audit, NCR

Projects: NRB, RFx,

reviews

ECSS: Standardisation

PCB/SMT WG: Harmonisation

R&D


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ECSS European Cooperation for Space Standardisation

ECSS-Q-ST-70-10C PCB qualifcation (revision ongoing) ECSS-Q-ST-70-11C PCB procurement (revision ongoing) ECSS-Q-ST-70-12C PCB design (first issued July 2014) In addition, Process Identification Documents (PID) describe qualified technology domain of each PCB manufatcurer.


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Harmonisation of electronic technologies

ECSS standardisation ecss.nl

PCB/SMT WG with industry in the Component Technology Board

technology roadmaps escies.org, spacecomponents.org


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Technology drivers

PCB are platform for placement and routing for complex components PCB ~2 keuro Area Array Device ~20 keuro PCBs need to be comparable to components in terms of reliability and complexity, but for a much lower cost. • High pint count causes complex routing • Miniaturization requires dense routing • Signal integrity requires short routing


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Reliability issues

PCB material selection driven by assembly and repair, not by space environment PCB build-up driven by capability and miniaturization, not by manufacturability ⇒ Material, build-up and metallisation processes affect

reliability of interconnections

⇒ Design and manufacturability are key


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Qualification

- Request for qualification: support, market, ESA projects

- Qualification ECSS-Q-ST-70-10

- Audit

- Qualified domain published in PID and on escies.org/pcb/

- Design & Procurement by OEMs

- Periodic audit and re-qualification


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PCB manufacturer ESA

Equipment manufacturer

Procurement: DR + MRR, Test, NCR

Qualification: Test, Audit, NCR

Projects: NRB, RFx,

reviews

ECSS: Standardisation

PCB/SMT WG: Harmonisation

R&D


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B. Case study: contamination - Outline

1. Problem description a. Latent short circuit failure b. Failure mechanism c. Contamination d. IR testing

2. Risk mitigations

a. Design b. Manufacture c. Base material supply


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1. Latent short circuit - Introduction

Short circuit failure occurred in PCBs for power distribution after prolonged functional testing in ambient lab environment or after thermal vacuum cycles.


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1. Latent short circuit - Failure Mechanism

Electromigration caused by: Pathway Electrolyte Bias voltage

Dendritic growth (SIR) Conductive Anodic Filament


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1. Latent short circuit - Pathway

Resin-glass interface Hollow glass fibers

Congolmerated flame retardant or fillers

Delamination Voids

Cracks [EA-2010-MAT-12B]

Contamination by foreign material


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1. Latent short circuit - Contamination

Sources: PCB manufacturing processes Base material supply

Types: Cl-bearing particles Metallic debris Organic residue Dust Fibers FR4 resin dust in polyimide etc


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1. Latent short circuit – IR test

fiber contaminated no contamination observed

http://www.ipcoutlook.org/pdf/insulation_resistance_dieelectric_materials_ipc.pdf

T0 after 200TC after 500TC T0 after 200TC after 500TC




• Fiber contamination provides pathway for electromigration

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1. Latent short circuit – IR test conclusions


IPC-2221 ECSS-Q-ST-70-12 “Space product assurance – PCB design“ Example: 4 mil laminate with 2 oz Cu can have a min projected peak-to-peak dielectric thickness of 68 µm. Take account of tolerances in dielectric thickness Take account of etching tolerances for in-plane clearances Margin for double insulation of critical signals Presence of non-functional pads 2 sheets of glass reinforcement between copper layers

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2. Risk mitigation – PCB design www.ecss.nl


a) Incoming sample inspection on base laminate

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2. Risk mitigation – PCB manufacturer


b) Inspection on etched inner layers: 100% visual inspection on light table

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b) Inspection on etched inner layers: AOI

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c) Cleanliness control plan QT/2013/730/SH

Recommendations: Cleanliness control between Cu oxidation and lay-up Restrictions on the use of materials that show static charging Class 100‘000 cleanroom in lay-up area Class 1‘000 cleanroom on flow bench De-ionisation equipment at lay-up

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www.escies.org/pcb/


http://www.escies.org/pcb/

d) Cleaning and inspection of ecthed inner layers and prepreg

Clean • ‘tacky‘ roller • vacuum hovering Inspect • UV fluorescence • bright light

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e) Inspection on external layers Note: these are laminates, not prepreg

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f) High resistance electrical testing

V drop during ramp up is a failure Direct resistive testing 1.27 mm adjacency

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IPC-9252 IPC6012 class 3/a QT/2013/681/SH 10 V 250 V 250 V

10 MΩ 100 MΩ 1 GΩ

www.escies.org/pcb/


http://www.escies.org/pcb/

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2. Risk mitigation – IPC-4101 base laminate

• Test frequency • Pass/fail criteria • Consequences of failure


Proposal for cleaner class of base materials [QT/2013/378/SH] Prepreg delivered as b-stage cured sheets Prepreg for manufacture of laminate ⇒ Increase inspection frequency to 100% Laminate ⇒ Reduce permittable fibre length from 13 mm to 0.5 mm ⇒ Increase sample frequency to 2% ⇒ Reject entire lot if test is non-compliant

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2. Risk mitigation – IPC-4101 base laminate


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Conclusions

Interactions in supply chain identified contamination problems. Risk mitigations specified in design, manufacture and base material supply. New procurement specification in use and proposed to IPC-4101.


Thank you for your attention!

ESA’s approach to quality control of the supply … › mews › jp › 27th › data ›...

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