By: Jonathan Reyes Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

2010

Jonathan Reyes Digital Electronics

12/3/2010

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Ning Zhu, Wang Ling Goh, Weija Zhang, Kiat Seng Yeo, and Zhi Hui Kong from the

Nanyang Technological University in Singapore proposed an alternative type of adder for

applications that required lower power consumption and better speed performance rather

than very accurate results. Although the power consumption and speed performance is

much better with this proposed adder, the accuracy tradeoff is actually negligible in

applications such as Digital Signal Processing (DSP). The proposed adder is called an Error-

Tolerant Adder (ETA). This adder was compared to other adders such as: Carry-Skip Adder

(CSK), Carry-Select adder (CSL), and the Carry-Look-Ahead adder. These are all very fast

adders but have a tradeoff of consuming large amounts of power. There are also other

alternatives that provide lower power consumption, but with a tradeoff of speed. The

proposed ETA adder consumes little power and is also very fast.

VLSI design often yields inaccurate results, but these results are acceptable because

our world is analog. Human senses for example do not require everything to be exact. A

human cannot perceive that an image is low quality if they view it from far away. A very

pixelated image looks very similar to a high resolution image if they are both viewed from

far away. The human eye only needs about 45 frames per second to see a moving image

smoothly, which is the real time frame rate. In PC gaming for example, video cards can

output frame rates as high as 150 frames per second (FPS). The difference between 150

FPS and 100 FPS is almost undetectable to a human eye, so in cases such as these, we

achieve a threshold of accuracy in the video or image that is needed in order for someone

to view it comfortably. An example I acquired 360x356 resolution image of the FIU panther

logo and a 180x178 logo (half the size of the first one). I expanded the second one to look

the same size of the second one. Even though the resolution was decreased by half, it is

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difficult to see that the image on the right is blurry compared to the one on the left.

Furthermore, if these images are observed from far away, one would think they were the

exact same images, when in fact they are not. This proves accuracy is not needed in certain

applications. The design of an ETA adder has been implemented for this purpose and to be

used in solutions that require less power consumption and higher speed rather than

accuracy. Large data sets require adders to be very fast, thus creating the need for ETA

adders.

There are factors that must be taken into consideration for the ETA adder to

be acceptably accurate. In order to meet constraints required by specific applications,

factors such as Overall error (OE), Accuracy (ACC), Minimum acceptable accuracy (MAA),

and Acceptable probability (AP), must be taken into consideration. Overall Error is

calculated as OE = |Rc-Re|, while Rc is the correct result of an adder and Re is the actual

result of the adder. Accuracy (ACC) is calculated by ACC = (1- (OE/Rc))x100%. In the

example used in this paper, they require the Minimum Acceptable Accuracy (MAA) to be

95% and the acceptance probability to be 98%.

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The proposed ETA requires a special type of Addition Arithmetic of binary numbers.

The image below shows the process used to add two numbers.

The addition Arithmetic consists of an accurate part (on the left) and an inaccurate part (on

the right). The addition of the accurate part is handled normally by a RCA (Ripple Carry

Adder). Each bit is added normally, generating and propagating a carry in a situation where

both input sum bits are 1. In contrast, the addition of the inaccurate part goes from left to

right, and no carry is generated or propagated. If the sum bits are not both 1, then the

addition is handled normally just like the accurate part. In the other hand, if the sum bits

ARE both 1’s, then all the bits to the right are also set to 1. This saves the power consumed

and speed lost by propagating and generating a carry. In the example above, OE = 72877 –

72863 = 14. According to that number, the accuracy is ACC = (1-(14/72877))x100% =

99.98% accurate. 99.98% accuracy is definitely good enough in applications such as digital

signal processing or in mobile phone applications where battery time is essential but

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quality is not needed as much. How does one determine what is the accurate part, and what

is the inaccurate part? The dividing strategy is determined based on a guess and verify

system that depends on requirements such as speed, power, and accuracy. If accuracy is

very important, then more bits will be in the accurate part of the string of bits. If speed and

power are needed, then more will be added to the inaccurate part of the string of bits. An

optimal time delay would be where the accurate part and the inaccurate part would be

calculated in close to equal time.

The hardware used to implement the ETA is also divided into calculating the

accurate and the inaccurate. The accurate part just requires a conventional adder. The

inaccurate part requires a control block and a carry-free addition block. The control block

is used to generate the control signals, that determine the working mode of the carry-free

addition block. The carry-free-addition block consists of 20 modified XOR gates that are

used to generate the sum bits. Below is an image and description of the modified XOR gate.

“In the modified XOR gate, three extra transistors,

M1, M2, and M3, are added to a conventional XOR

gate. CTL is the control signal coming from the

control block of Fig. 6 and is used to set the

operational mode of the circuit. When CTL=0, M1

and M2 are turned on, while M3 is turned off,

leaving the circuit to operate in the normal XOR

mode. When CTL=1, M1 and M2 are both turned off, while M3 is turned on, connecting the output node

to VDD, and hence setting the sum output to “1.” The function of the control block is to detect the first bit

position when both input bits are “1,” and to set the control signal on this position as well as those on its

right to high.”

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The ETA and the other conventional adders were simulated using HSPICE. The results

showed that the ETA successfully achieved lower power consumption and lower delay than all

the other adders. The transistor count on the ETA was almost as small as the RCA, and much

smaller than CSK, CSL, and CLA respectively. These results prove that the ETA adder is a very

feasible solution to increase performance and lower power consumption in applications in

which accuracy are not extremely important. The following images show that the ETA adder can

be very useful in Digital Signal Processing. The first image was processed using a regular adder

that required large power consumption, and the second image was processed using the fast

ETA adder. The reduction in quality is not very noticeable, and is definetelya good tradeoff for

better processing time and less power consumption.

(a) Processed without ETA (b) processed with ETA