Error-Correction &CrosstalkAvoidance in DSM Busses

Ketan Patel and Igor Markov University of Michigan

Electrical Engineering & Computer Science

2003 ACM 1-58113-627-7/03/0004

Outline

Motivation Memoryless Codes Codes with memory Boundary shift codes

Motivation

DSM busses increasingly susceptible to noise

Crosstalk Electromagnetic interference Power grid fluctuations

Goal: Avoid crosstalk & provide error-correction

Crosstalk Noise

The severity of interference is correlated with the particular switching patterns on the bus.

Bus value (t=0) ⇒ 0 1 1 0 0 0 1 1Bus value (t=1) ⇒ 1 1 0 1 1 0 1 0

We call this an invalid transition

A self-shielding code does not allow invalid transitions.

Memoryless Model

Vertices: Bus Values Edges: Valid TransitionsMax clique⇒Optimal

memoryless codedistance ≥ d ⇒ Detect d-1 errors

can correct [(d-1)/2] errors

Place edges if Valid transition Distance large enough

3-bit codes example

(a) (b)

Codes with Memory

Two graphs:G1 :crosstalk constraintsG2 :error-correction constraints

For rate log2M code Vertices connected to ≥ M vertices

in G1forming clique in G2

Dependent Boundaries

Dependent boundary: boundary with transition

0 1 1 0 1 0 0 0Positions {1, 3, 4, 5}

No overlappingdependent boundaries⇒No invalidtransition

Boundary Shift Codes

Start with error-correcting code Duplicate all bits (no odd dependent

boundaries) Possibly “puncture” last bit position ⇒

Code 1 1-bit circular right-shift ⇒Code 2

Code 1 has no odd dependent boundaries Code 2 has no even dependent boundaries

Boundary Shift Codes(example)

Time Input Encoded Output 0 1010 110011000

1 0111 100111111

Time Received 1 110111111 1-bit left-shift ⇒101111111Decode by majority vote ⇒ 0111

AdvantagesAdvantages Practical encoder/decoder Scalable construction Systematic (unencoded wires)

Drawbacks Encoding/decoding logic overhead Wire overhead

Code Rates