Errata for Analog IC Design with Low-Dropout Regulators

Prof. Gabriel A. Rincón-Mora, Ph.D.

Chapter 2 Page 69: "…the MOSFET enjoys the benefit of true symmetric performance…"

Chapter 3

Equation 3.4: M.LFGoutv =0

= outiinv! gsv mg

gsv + Rv= gsv mg

gsv +R vgsgm( )= mg1+Rgm

" mg

Equation 3.5: M.LFGoutv =0

= outiinv! gsv mg " Rv mbg

gsv + Rv= mg1+ mg + mbg( )R

# mg

Equation 3.6: gRg1g

11gvRv

gvvvgv

viG m

m

m

m

m

R

m

in

out0vLF.M

out≤

+≈

⎥⎦

⎤⎢⎣

⎡⎟⎠

⎞⎜⎝

⎛β

++

=+

≈=

ππ

π

π

π=

Equation on page 89: R || 1sC

!

"#

$

%&=

R1+ sRC

=R

1+ s2'p

Equation 3.20:

( )

( )( )⎥⎦

⎤⎢⎣

⎡

+++

+=

⎟⎟⎠

⎞⎜⎜⎝

⎛

++

=

⎟⎟⎠

⎞⎜⎜⎝

⎛+

≈

Rg1sRC1Rg1

sRC1g

sRC1Rg1

g

sC1||Rg1

gG

m

PARm

PARm

PARm

m

PARm

mM

=

GM.LF 1+s

2!zG

"

#$

%

&'

1+ s2!zG

GM.LF

gm

"

#$

%

&'

(

)*

+

,-

.

GM.LF 1+s

2!zG

"

#$

%

&'

1+ s2!pG

"

#$

%

&'

Figure 3.14:

I BiasV Bias

V > V CE CE(min) V > V DS DS(sat)

i O1

v O1

i O1

v ID

I Bias

-V ID(min) +V ID(max)

(0, 0.5I ) Bias

(b)

Small-SignalVariations

DDV

i o

v id

v O2

R O

1

V CC

R O

2I BiasV Bias

v O1 v O2

0.5v +v ID CM -0.5v +v ID CM

R O

1

R O

2

Assume IdealCurrent Sources (g = 0) m

i O2 i O2

(a)

i O1 i O20.5v +v ID CM -0.5v +v ID CM

SSV EEV

Figure 3.22:

C π

C µ

r v g

r

C π

C µ

r v g

r

(a)

i out

i in

2C π

1/g

(b)Q IN Q O

C µ r

i Loa

d

v in v out

R Si s

R Lo

ad C Lo

ad

Z IN Z OUT

Equation 3.78: Since QIN–QO mirrors igm.IN,

ib.CO =igm.IN1+!

and INR =1m.CINg

+1m.Mg

!

"#

$

%& || IN.COR '

2mg|| 2

mg1+(( )

)

*+

,

-. '

2mg

Equation 3.81:

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛=≡

out

Load

CO.gm

out

CO.e

CO.gm

M.gm

CO.e

M.b

M.gm

in

M.b

s

in

s

LoadLF.I v

iiv

vi

iv

vi

vv

iv

iiA

= RS || RIN( )

1gm.M

!

"#

$

%&

RIN

'

(

))))

*

+

,,,,

-gm.M( ) ro.CO +RLoad

1+gm.COro.CO|| r..CO +

1gm.M

+1

gm.CIN

!

"#

$

%&

'

()

*

+, gm.CO( ) ROUT || RLoad( ) 1

RLoad

!

"#

$

%&

( ) ( ) ( ) ⎟⎟

⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟

⎠

⎞⎜⎝

⎛≈Load

LoadOUTCO.m

CO.mM.mINS R

R||Rgg1g

21R||R

!

2gm.M

"

#$

%

&'12"

#$%

&' (gm.M( ) 1

gm.CO

"

#$

%

&' gm.CO( ) 1( ) ! (1

Chapter 4 Figure 4.10:

|v |A O V

i = O 0.5|v |g O m

v O

* Unused terminal at 0, V , or v (but not in the feedback path) Bias I

or

i = O 0.5|v |g O m i = O |v |g O m

i =

O

|v |

g

O

m

orv O

or

v O

orv O

orv O

orv O

Page 153, 2nd paragraph, line 14: “…to iO (i.e., approximately gm) and iO to vFB (i.e., roughly R), respectively.”

Equation 4.15: R1

Rg1g

A1A

viA

m

m

FBOL.G

OL.G

I

OCL.G ≈

+≈

β+=≡

Figure 4.20:

v 2A V

v 1

C M

iC.M

iA.V

R M

z , M

(a) Loop

Gai

n A

[dB

]β

OL

FB

Frequency [Hz]

p 2

p 1

0dB

f 0dB

p 1

p 2

f 0dB.M

f 0dB.A

(b)

f 0dB.S

f 0dB.MR

Miller-RM

Page 168, 2nd paragraph, line 6: “…where the output voltage is zero, which means io or vfb/(rπ||R) is vegm(rπ||R||ro)/(rπ||R) or approximately gm.” Page 168, 3rd paragraph, line 12: “…current gain AI.OL is io/ie, where io is MC’s gate voltage vgC (or approximately, iero1AV) into source-degenerated transconductance io/vgC:” Equation 4.47:

( )( )[ ] ( )3sddsAmA

1omC

mC3sddsAmA1o

e

gC

oV1oe

e

oOL.I r||rg

rg1gr||rgr

iviAri

iiA ≈⎟⎟

⎠

⎞⎜⎜⎝

⎛

+=

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

==

Page 169, 1st paragraph, line 3: “…or rdsCAV, where AV is gmA(rdsA||rsd3):” Page 185, Active LHP Zeros, line 5: “…equivalent pole-zero pair pz-p-zz-p results because…” Figure 4.24:

1

OL.ROL.V R

A =

(a)

v IN R z-p 1v O

A V

z-p

R 2

(b)

v /v

[d

B]

O

IN

Frequency [Hz] (log scale)

f GBW

p z-p

z z-p

2

1

2 z-p

1

V.OL

1

OL.ROL.V R

AA =

Page 186, paragraph 2, line 6: “…(i.e., 1/2πR1C1) until the gain reaches the amplifier’s maximum possible gain AV.OL, beyond which point the close-loop gain drops with AV.OL, as shown in Fig. 4.25b.”

Figure 4.25:

v IN R 2 1v O

A V

1

(a)

v /v

[d

B]

O

IN

Frequency [Hz] (log scale)

z ff

2 1

(b)

1

OL.ROL.V

sC1||R

A =

V.OL

f GBW

11

OL.ROL.V

sC1||R

AA =

Chapter 5: Equation 5.13:

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟

⎠

⎞

⎜⎜

⎝

⎛≈⎟

⎟⎠

⎞⎜⎜⎝

⎛

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛=

'CC

II

GBW1

z

pGBW

ff

(min)B

(max)O

(min)L

(max)L

(min)(min)ESR

(max)B(max)

PMOS(min).dB0

PMOS(max).dB0

Equation 5.14:

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛≈⎟

⎟⎠

⎞⎜⎜⎝

⎛

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛=

'CC

II

GBW1

z

pGBW

ff

(min)B

(max)O

(min)L

(max)L

(min)(min)ESR

(max)B(max)

PNP(min).dB0

PNP(max).dB0

Equation 5.18:

⎟⎟⎠

⎞⎜⎜⎝

⎛

++≤

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛

⎥⎥⎦

⎤

⎢⎢⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛=

CCCC10

z

pGBW

pGBW

GBW1

ff

(min)L(min)P(min)B

(max)O

(min)ESR

(max)BInt

(min)O

Int

Int(min)Int.dB0

(max)Int.dB0

Figure 5.10:

V Bias

MD1

v IN

v A

MD2

MM1 MM2

MTail

1/g

m

Eq.

v in2r + 1/g sdTail mD

i ~ acv in

v in

R D R D

R M

r dsM

R D

v ~ 0 aAC Eq. MD1

v in

v a

MD2

MM1 MM2

v in

2r d

sTai

l

2r d

sTai

l

V BiasD V BiasD

Chapter 6: Equation 6.8:

( )

( )

11

1LGgsC

1LGgG

11LGsCR1LG

RG

ZGLG

REGBUF.m

SW

REGBUF.m

FB

REG

SWBUF.O

REG

BUF.OFB

BUF.OFBFB <

⎥⎦

⎤⎢⎣

⎡+

+

+≈

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+

+≈≈

++

++

Equation 6.9:

⎟⎟⎠

⎞⎜⎜⎝

⎛+

≈>+

=β≈

+

<+

1g

sCgG

LGRRRAAAALG

BUF.m

SW

BUF.m

FB

1LGFB2FB1FB

1FBPOEAFBPOEAREG REG

Chapter 7:

Figure 7.2:

V IN

p EAI BIAS

V REF

v O

M ND1M ND2

M NM1 M NM2

M NO

M NB1 M NB2M NB3

R FB

1R

FB2

C Op FB

p O

z M

f 0dB

z C

Loop

Gai

n A

[dB]

β

O

L

FB

Freq. [Hz]0O

-90 O

-180 O Phas

e Sh

ift [

]O

0dB

p O

p EA

f o 180

p FBp M

z NO

z Mz C

(a)

(b)

p M

z NO

z ND2

z ND2 v EA

M Tail

M PB1M PB2

M PB

p 1

p 2

M PBC M PC1M PC2

C Cv FB

p 1,2

LG LF

Appendix A

Derivation: Time Linear Regulators Require to Respond to a Sudden Load-current Step A regulator, in essence, is a differential amplifier used in a non-inverting feedback configuration. As such, an equivalent gain block with a reference voltage as its non-inverting input can model its closed-loop response. Figure A.1 illustrates the circuit and its model. The output of the regulator is loaded with a capacitor having a finite ESR value and a current sink characterized by transient load-current steps. Capacitor CO, at first charged to VOUT, initially provides the current demanded by the transient load because the regulator requires some time to react. Voltage vOUT therefore instantaneously drops a voltage equal to the product of the load current and the ESR of CO. Consequently, voltage vX instantaneously drops an attenuated version of the same. This voltage change will be considered, for this derivation, the transient stimulus against which the circuit must react to maintain a regulated output voltage. For analysis, the stimulus is referred back to VREF by simply inverting the polarity of the instantaneous voltage change. This procedure allows the circuit to be modeled, as shown in the figure, by a block having the closed-loop transfer function displayed from VREF to vOUT with a transient voltage step as its stimulus. In this manner, the response time (system delay) to a load-current change may be approximated.

Vref

I Loa

d

Co

RES

R

Vout

R1

R2Vx

A1 + Aβ ~

1 /βτs + 1

Vin Vout

Figure A.1. Block-model development of a typical linear regulator for estimating the time delay through the system. For simplicity, the circuit is further assumed to exhibit a single-pole response. This assumption is reasonable if any secondary pole is sufficiently displaced from the system’s dominant pole. As a result, the output is expressed as a function of input vIN and time constant τ:

⎟⎠

⎞⎜⎝

⎛+τβ

≈⎟⎟⎠

⎞⎜⎜⎝

⎛

β+=

1s1v

A1A

vv ININOUT , (A.1)

where τ is 1/ωBW, ωBW the bandwidth in radians, A the forward open-loop gain of the regulator and β the feedback gain factor or R2 / (R1 + R2). Figure A.2 shows the time-dependent waveforms of the load current, the consequential input referred voltage, and the output. The input referred signal is further simplified to a single step response (vIN′). This approximation is done since only the delay associated with the instantaneous voltage change is pursued: approximate delay through the system for a single event. The peak-peak voltage of the step response, 1 / s in the s domain, is assumed to be 1 V; thus, vOUT is

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

τ+

−β

=⎥⎦

⎤⎢⎣

⎡⎟⎠

⎞⎜⎝

⎛+ττ

−β

=⎟⎠

⎞⎜⎝

⎛+τβ

= 1s

1s11

1ss11

1s1

s1

vOUT , (A.2)

in the s domain, or equivalently,

⎥⎦

⎤⎢⎣

⎡⎟⎠

⎞⎜⎝

⎛τ−

−β

=texp11vOUT (A.3)

in the time domain, where t refers to time. Consequently, time delay tdelay is the time span defined by the onset of the input transition to the time the output reaches 90% of its final value (i.e., 0.9 / β),

t

0

V9.0

0OUT

%90

texp11v ⎥⎦

⎤⎢⎣

⎡⎟⎠

⎞⎜⎝

⎛τ−

−β

=β (A.4)

or ω

=τ≈τ==BW

%90delay3.23.210lntt . (A.5)

Consequently, the approximate time delay through the regulator is 2.3 / ωBW, or equivalently, 0.37 / fBW.

ILoad

Vout1 /βτs + 1

Vin

Vin

Vin

VoutVΔβ

VΔ

Time Figure A.2. Time-domain description of the system under a stepped load-current change.