EPMC-PU-0114-1.0

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78K Primer Kit

78K0S & 78K0 (8-bit) & 78K0R (16-bit)

Microcontrollers for the Industrial MarketArchitecture, Peripherals and

Development Tools

2

Disclaimer

The information in this document is current as of January, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.

• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application."Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots."Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)."Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note)(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries.(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).

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Purpose of the 78K Primer Kit

This kit has been created to help and educate newcomers to get started quickly and easily with 78K Microcontrollers, both 78K0 8-bit and 78K0R 16-bit.

This is ideal for Engineers and Students new to NEC’s Microcontrollers

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Contents

1. Introduction

2. General Purpose & Industrial MCU Roadmap

3. Industrial Applications Focus

4. Industrial Application Examples

5. NEC Microcontroller Nick-Naming

6. 8/16-bit NEC Microcontroller Nomenclature

7. Quality Grades

8. Different NEC cores• 78K0 & 78K0R Microcontroller Series

− General Purpose Microcontroller− Motor Control Microcontroller− Microcontroller with LCD C/D

9. The 78K Architecture• Memory Organization• Processor Registers• Mirror Area• Pipeline Structure

10. The 78K On-Chip Peripherals• Clock generator, Ports, Power-On Clear,

Low-Voltage Indicator, Timers, Comparators/Operational Amplifiers, Real-Time Clock, Window Watchdog Timer, Option Byte, A/D Converter, D/A Converter, Multiplier/Divider, Serial Interfaces, Interrupt Functions, Key Interrupt Functions, LCD Controller/Driver, DMA Controller, External Bus Interface

11. Flash Technology• Parameters and security• On-board programming• Self-Programming• EEPROM Emulation

12. The Development Tools Environment• 78K0 & 78K0R Tools Environment

13. Support

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1. Introduction

All of our Multi Market Microcontrollers employ reliable Flash memory

All Flash continues to evolve, contributing to the success of customers

Answering ever more specific needs, contributing to cost cutting, delivering peace of mind that can be relied on.

This lineup comprises the V850E and V850ES 32-bit microcontrollers delivering high performance for system control, and the 78K0 and 78K0S 8-bit microcontrollers, which boast a small size and low power consumption making them ideal as subcontrollers.

A truly diversified lineup of 8-bit devices that offers a full range of products, which are available with 10 to 100 pins and ROM capacity of 1 KB to 128 KB; cuts total cost by allowing program changes, the incorporation of peripheral functions, and lower power consumption; as well as providing a full range of development tools that dramatically enhance ease of use.

NEC Electronics' All Flash lineup is completed by the 78K0R 16-bit microcontrollers, positioned between 8-bit and 32-bit microcontrollers. These microcontrollers achieve a low power consumption on a par with that of 8-bit microcontrollers while delivering the performance of 16-bit microcontrollers.

NEC Electronics' All Flash lineup supports from 30 to 144 pins and ROM capacities of 16 to 512 KB. The lineup also inherits the existing 78K0 and 78K0S 8-bit microcontrollers. Should 8-bit microcontrollers fall short in terms of performance and ROM capacity for the intended application, smooth migration to 16-bit microcontrollers is possible.

More than just providing its devices with sophisticated functions, NEC Electronics has also created an entire infrastructure that ranges from the development of flash microcontrollers to their delivery and that enables more effective and simple use of All Flash.

Our products and environment, which make the most of the merits of flash memory products, work for the success of our customers everywhere.

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2. General Purpose & Industrial MCU Roadmap

1024768640512384256128s

966448322416

8421

Flas

h:

K B

yte

32-bit

16-bitHigher performance & large memory

MultiPurpose

LCD drive / control

Industrial ASSP’s

Low power Low power & high integration& high integration

Low pin countLow pin countMCUMCU

10 16 20 30 44/48 52 64 80 100 128 144 pin

High performance, low power & High integration

8-bit

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3. Industrial Applications Focus

Industrial Markets & Applications

Healthcare

Diagnostic

Imaging

Therapy

Other Healthcare

Motor Control

Major Appliances

Small Appliances

Power Tools

Industrial Motor Control

Industrial Automation

Control Systems

Sensors

Operator Panels (HMI)

Instrumentation

Industrial Networking

Building Management

HVAC

Fire & Security

Lighting

Metering

Biometrics

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4. Industrial Application Examples

Fire Detectors

Electricity/Water/Gas Meters

Thermostats

Programmable Logic Controller (PLC) Patient Monitors Blood Glucose

Meter

Washing Machines

Electric Drills Electric shavers

Some IndustrialApplications…

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78K0/Kx2 - L

CPU core name (78K0, 78K0S CPU core name (78K0, 78K0S 88--bit; bit; 78K0R 78K0R 1616--bitbit))

Device family name (K, F, L Device family name (K, F, L , etc.), etc.)

Device package informationDevice package informationA: 20 pinsA: 20 pins G: 100 pinsG: 100 pins

Device generation (1st, 2nd, etc.)Device generation (1st, 2nd, etc.)

78K078K0//KKEE22 88--bit CPU, K Series (General Purpose) 2nd generation, 64 pin packabit CPU, K Series (General Purpose) 2nd generation, 64 pin packagege78K0R78K0R//KKGG33 1616--bit CPU, K Series (General Purpose) 100 pin packagebit CPU, K Series (General Purpose) 100 pin package

Extension L Extension L --> Low Power > Low Power

5. NEC Microcontroller Nick-Naming

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6. 8/16-Bit Microcontroller Nomenclature

µPD78F0547GK-8EU-APackage + Lead Frame + Lead free

Series & ROM size

Core (0: 78K0, 1: 78K0R, 9: 78K0S)

Memory (no: ROM, “F”: Flash)

Member of the 78K MCU family

Microcontroller CMOS

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7. Quality grades

= Ta : - 40°C … + 85°C NEC’s standard quality(A) = Ta : - 40°C … + 85°C NEC’s automotive quality(A2)= Ta : - 40°C … + 125°C

All “A” grades get an additional burn–in and are tested at high temperature.

µPD78F0547GK(A)-8EU-AµPD78F0547GK(A)-8EU-A

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Different Cores for each Application Requirement

8. Different NEC Cores

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

78K0R16-bit

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78K0S Core

8-bit CISC CPU core• 200ns min. instruct. exec. time

47 assembler instructions• 8 and 16-bit data transfers

1 register bank organized as • 8x8-bit or 4x16-bit registers

Free configurable software stack Vectorized interrupts for each source

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0R16-bit

78K0SLow-End

8-bit

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78K0 Core

8-bit CISC CPU core• 100ns min. instruct. exec. Time• Code banking for > 60k

63 assembler instructions• 8 and 16-bit data transfers• mul/div instruction (8x8, 16/8-bit)

4 register banks organized as• 8x8-bit or 4x16-bit registers• fast interrupt handling

Free configurable software stack Vectorized interrupts for each source• Selectable priority

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0RHigh-End

16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

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78K0R Core

16-bit CISC CPU core• 50ns min. instruct. exec. Time• Up to 512kB ROM

71 assembler instructions• 16-bit shift instructions

3-stage pipeline2 DMA channelsUltra low power consumption• 4mA @10MHz 3V

Free configurable software stack Vectorized interrupts for each source• 4 interrupt priority level

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

78K0R16-bit

16

8-bit Micro Series

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8-bit 78K0 – K Series

78K0 K Series

10 to 100 pins 8- and 16-bit Timers10-bit A/D Converter8-bit D/A ConverterSerial Interfaces• UART with LIN Functionality• 3-wire (SPI)• I2C

Internal OscillatorsSecure Watchdog POC / LVI CircuitWide Operating Voltage RangeWide Package VarietyRoHS Compliant

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0SLow-End

8-bit

78K0R16-bit

ASSP

Devices

78K0High - End

8-bit

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Low Pin Count Microcontrollers78K0S/Kx1+

78K0S/Kx1+

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

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78K0S/Kx1+ – Product Line-up

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78K0S/Kx1+ - Version Line-Up

x RAM sizew/o AD conv.

Flash (Byte)

8K

4K

2K

1K

128128

128128

128128

10-pinKU1+

128128

128128

128128

16-pinKY1+

256

128

20-pinKA1+

256

256

30-pinKB1+

x RAM sizewith AD conv.

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µPD78F950x – 10pin (78K0S/KU1+) (1/2)

Window Watchdog Timer

78K0S Core200 ns @ 10MHz

2 to 5.5V-40 to +85°C

Flash

Single Voltage FlashSecure Self-Programming

Power-On ResetLow-Voltage Indicator

10-Pin PackageMA (SSOP 0.65 mm pin pitch)

On-chip Oscillator8 MHz (±2%), 240kHz

Up to 8 I/O lines

Interrupt Controller2 external / 8 internal

1 KB Flash 128 B RAM 78F95002 KB Flash 128 B RAM 78F95014 KB Flash 128 B RAM 78F9502

8-bit Timer TMHx1-ch, 2 x Compare/1 x PWM

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µPD78F920x – 10pin (78K0S/KU1+) (2/2)

16-bit Timer TM01-ch, 2 x Capture/Compare



2 to 5.5V-40 to +85°C

Flash



10-Pin PackageMA (SSOP 0.65 mm pin pitch)

Cer. / Crystal OscillatorUp to 10 MHz


Up to 8 I/O lines




A/D Converter4 x 10-bit

23

µPD78F951x – 16pin (78K0S/KY1+) (1/2)




2 to 5.5V-40 to +125°C

Flash



16-Pin PackageGR (SSOP 0.65 mm pin pitch, 225 mil)

FH ( WCSP 2.2 x 1.9 mm2)CS (SDIP)



Up to 14 I/O lines




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µPD78F921x – 16pin (78K0S/KY1+) (2/2)




2 to 5.5V-40 to +125°C

Flash



16-Pin PackageGR (SSOP 0.65 mm pin pitch, 225 mil)

FH ( WCSP 2.2 x 1.9 mm2)CS (SDIP)



Up to 14 I/O lines





25

µPD78F952x – 20pin (78K0S/KA1+)




2 to 5.5V-40 to +125°C

Flash



20-Pin PackageMC ( SSOP 0.65 mm pin pitch, 300 mil)

FH ( WLBGA, 2.03 x 2.55 mm2)CS (SDIP)



Up to 17 I/O lines


2 KB Flash 128 B RAM 78F95214 KB Flash 256 B RAM 78F9522

Serial Interface1-ch, UART (1 x LIN capable)


26

µPD78F953x – 30pin (78K0S/KB1+)



8-bit Timer TM81-ch, 1 x Compare


2 to 5.5V-40 to +125°C

Flash



30-Pin SSOP PackageMC ( 0.65 mm pin pitch, 300 mil)



Up to 26 I/O lines



HW Multiplier(8x8)



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78K0S/Kx1+ - Peripherals

Note 1: external osc not on 78F950x devices

Flash [KB]

1 to 10 MHz externNote1 and 8 MHz (+/- 3%) on-chip

KU1+16 30

RAM [Bytes]Main ClockSubclockWatchdog

Timers

16-bit

RTC

SerialInterface

UART

InterruptsNote 3 4 ext./ 10 int.

10-bit A/D-Converter 4 channels Note2

PortsUp to 8 I/O

POC / LVI Power-On-Reset: 2.1V±0.1V, LVI: 2.35V to 4.30V

KY1+

Up to 14I/O

1 channelNote1

KB1+10

Memory

Pin count

ClockSources

1 / 2 / 4 4 / 81 / 2 / 4128 128 256

Up to 26 I/O

20

2 / 4128 / 256

240 kHz (+/- 50%) on-chip

8-bit 2 channels

Up to 17 I/O

2 ext./ 8 int.

KA1+

1 channels

Watchdog 1 channel

1channel (supporting LIN)

Operational AmplifierNote 2

Note 2: only 78F92xx

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16-pin WCSP is the smallest packaged MCU in the world!

WCSP1.9x2.2mm

0.5mm pitch

KY1+ 16pin

78K0S/Kx1+ – Space Saving Packages

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78K0/Kx2“General purpose peripherals

& scalability at it’s best”

30

78K0/Kx2

78K0/Kx2

V850ESLow-End

32-bit

V850EHigh-End

32-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

31

78K0/Kx2 – Product Line-up

32

Flash (Byte)

128K

96K

60K

48K

32K

24K

16K 768

1K

RAM size78K0/Kx2x

8K 512

768

1K

1K

2K

768

1K

1K

2K

3K

5K

2K

3K

5K

768

1K

512

78K0/Kx2 - Version Line-Up

30-pin 36-pinKB2

38-pin 44-pin 48-pinKC2

52-pinKD2

64-pinKE2

80-pinKF2

768

1K

768

1K

1K

2K

1K1K1K

7K7K

3K

5K

7K7K 7K 7K

1K 1K 1K

3K3K

RAM size78K0/Kx2 On Chip Debug version

x

768

1K

2K

3K

5K 5K

Portfolio Extension on A version

1K1K

7K 7K7K 7K

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Improvements on A version

Extended portfolio• Up to 128 KB Flash in 30-pin SSOP and 48-pin LQFP• 38-pin SSOP• Qualified for up to 140 °C

Improved Flash macro• Code: 1000 (instead of 100) W/E cycles,

15 years data retention• Data: 10000 (instead of 100) W/E cycles,

3 years data retention

Extended settings for A/D conversion time• Increased accuracy with noisy signals• Higher flexibility to adapt the conversion time

to the frequency

Improved self-programming firmware• Optimized for shorter interrupt response times

Wide operating range• 20 MHz at 2.7 - 5.5 V

Caution: Do not confuse “A” version and A/A2 grade

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Tool Changes for A Version

IECube

HardwareUpdate

MiniCube 2

Device File

PG-FP5-EE

SoftwareUpdate

Parameter File Update Required

No UpdateUse as it is






No Update(K Series:control code “F” or higher,F Series:control code "C" or higher)

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µPD78F050x – 30pin (78K0/KB2)



8-bit Timer TM5x2-ch, 1 x Compare/1 x PWM each

78K0 Core100 ns @ 20MHz

1.8 to 5.5V-40 to +125°C

Flash

Single Voltage FlashSecure Self-ProgrammingOn-Chip Debugging 78F0503D,78F0507D* Only 30 pin version


30/36-Pin PackageMC ( SSOP, 300 mil, 0.65 mm pin pitch)FC(LGA, 4 x 4 mm2, 0.5mm pin pitch)


On-chip Oscillator8 MHz (±5%), 240kHz (±10%)

Up to 23 I/O lines

Serial Interface1 x CSI (SPI)


8 KB Flash 512 B RAM 78F0500A16 KB Flash 768 B RAM 78F0501A24 KB Flash 1 KB RAM 78F0502A32 KB Flash 1 KB RAM 78F0503A48 KB Flash 2 KB RAM 78F0504A60 KB Flash* 3 KB RAM 78F0505A96 KB Flash* 5 KB RAM 78F0506A128 KB Flash* 7 KB RAM 78F0507A

Voltage Regulator


8-bit Timer TMHx2-ch, 2 x Compare/1 x PWM each


Serial Interface1-ch, I2C

Ext. Multiplier(from 48KB onwards)

36

µPD78F051x – 44/48pin (78K0/KC2)




Watch Timer


1.8 to 5.5V-40 to +125°C

Flash

Single Voltage FlashSecure Self-ProgrammingOn-Chip Debugging 78F0513D/5D/7D* Only 48 pin version

Key Return Inputs


38/44/48-Pin PackageMC ( SSOP, 300 mil, 0.65 mm pin pitch)

GB (QFP, 10 x 10 mm2, 0.8 mm pin pitch)GA (QFP, 7 x 7 mm2, 0.50 mm pin pitch)



Subclock Oscillator32.768 kHz

Up to 37/41 I/O lines


Interrupt Controller7/8 external / 16 internal

16 KB Flash 768 B RAM 78F0511A24 KB Flash 1 KB RAM 78F0512A32 KB Flash 1 KB RAM 78F0513A48 KB Flash* 2 KB RAM 78F0514A60 KB Flash* 3 KB RAM 78F0515A96 KB Flash* 5 KB RAM 78F0516A128 KB Flash* 7 KB RAM 78F0517A

Voltage Regulator



Clock / Buzzer Output A/D Converter8 x 10-bit



37

µPD78F052x – 52pin (78K0/KD2)




Watch Timer


1.8 to 5.5V-40 to +125°C

Flash

Single Voltage FlashSecure Self-ProgrammingOn-Chip Debugging 78F0527D

Key Return Inputs


52-Pin QFP PackageGB (10 x 10 mm2, 0.65 mm pin pitch)




Up to 45 I/O lines



16 KB Flash 768 B RAM 78F0521A24 KB Flash 1 KB RAM 78F0522A32 KB Flash 1 KB RAM 78F0523A48 KB Flash 2 KB RAM 78F0524A60 KB Flash 3 KB RAM 78F0525A96 KB Flash 5 KB RAM 78F0526A128 KB Flash 7 KB RAM 78F0527A

Voltage Regulator






38

µPD78F053x – 64pin (78K0/KE2)

16-bit Timer TM0Up to 2-ch, 2 x Capture/Compare



Watch Timer


1.8 to 5.5V-40 to +125°C

Flash


Key Return Inputs


64-Pin QFP PackageGC (14 x 14 mm2, 0.8 mm pin pitch)GK (12 x 12 mm2, 0.65 mm pin pitch)GB (10 x 10 mm2, 0.50 mm pin pitch)GA (7 x 7 mm2, 0.40 mm pin pitch)

FC (5 x 5 mm2, FLGA)




Up to 55 I/O lines

Serial InterfaceUp to 2 x CSI (SPI)

Interrupt Controller9 external / 16 (19) internal

16 KB Flash 768 B RAM 78F0531A24 KB Flash 1 KB RAM 78F0532A32 KB Flash 1 KB RAM 78F0533A48 KB Flash 2 KB RAM 78F0534A60 KB Flash 3 KB RAM 78F0535A96 KB Flash 5 KB RAM 78F0536A128 KB Flash 7 KB RAM 78F0537A

Voltage Regulator






39

µPD78F054x – 80pin (78K0/KF2)




Watch Timer


1.8 to 5.5V-40 to +125°C

Flash


Key Return Inputs


80-Pin QFP PackageGC (14 x 14 mm2, 0.65 mm pin pitch)GK (12 x 12 mm2, 0.50 mm pin pitch)




Up to 71 I/O lines

Serial Interface3-ch, 2 x CSI (SPI)

1 x Auto CSI


48 KB Flash 2 KB RAM 78F0544A60 KB Flash 3 KB RAM 78F0545A96 KB Flash 5 KB RAM 78F0546A128 KB Flash 7 KB RAM 78F0547A

Voltage Regulator





Ext. Multiplier

40

78K0/Kx2 - Peripherals

Note 1: only version >= 48K flash

Flash [KB]

1 to 20 MHz extern and 8 MHz (± 5%) on-chip

KB238 / 44 /48 64

RAM [KBytes]Main ClockSubclockWatchdog

Timers

16-bit

Watch timer

SerialInterface

UART/CSI/I2c

Interrupts6 ext. / 14 int. 7 ext. / 19 int.

10-bit A/D-Converter 8 channels

Ports23


KC2

32.768 kHz

2/1/1 channel

4 channels

31 / 37 / 41

1 channel

KE230 / 36

80

Memory

Pin count

ClockSources

16 to 128 16 to 128 48 to 1288 to 1280. 5 to 7 0.75 to 7 0.75 to 7 2 to 7

55 71

52

16 to 1280.75 to 7

240 kHz (±10 %) on-chip

8-bit 4 channels

45

7 ext. / 16 int.

KD2

1 channelWatchdog 1 channel

2/3/1 channel

HW-multiplier (16x16,32/16) 1 channel Note1

7 ext. / 20 int.

KF2

2 channel Note1

2/2 Note1 /1 ch.

41

Introducing78K0/Kx2-L

“Industry LeadingLow Power

8-bit MCU’s”

42

78K0/Kx2-L

78K0/Kx2-L

V850ESLow-End

32-bit

V850EHigh-End

32-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

43

78K0/Kx28-bit

30-80pin

78K0S/Kx1+8-bit

10-30pin

78K0R/Kx316-bit

64-144pin

78K0R/Next16-bit

78K0/Kx2-L16-48pin

78K0R/Kx3-L44-100pin

Wide operating voltage range

1.8V to 5.5VLow-powerInternal Oscillator

With ±2% accuracyAnalog function

Pin

count

Low Power 78K Series Overview

44

78K0/Kx2-L – Product Line-up

Family Concept:+ 16 to 48 pins+ 4 KB - 32 KB Flash+ 384 B - 1 KB RAM+ 8 and 16 bit timers+ UART, CSI,IIC+ AD conv. /comparator+ POC/LVI/on-chip oscillator

µPD78F055x

4 x 10-Bit A/D

4 - 16 KB Flash

Comparator

8/16-Bit Timer

78K0/KY2-L

384B - 768B RAM

16-pin SSOP

µPD78F056x

6 x 10-Bit A/D

4 - 16 KB Flash

Comparator

8/16-Bit Timer

78K0/KA2-L

384B - 768B RAM

20-pin SSOP

µPD78F057x

4/7 x 10-Bit A/D

8 - 32 KB Flash

Comparator

8/16-Bit Timer

78K/KB2-L

512B - 1KB RAM

30-pin SSOP

µPD78F058x

8/11 x 10-Bit A/D

8 - 32 KB Flash

Comparator

8/16-Bit Timer

78K0/KC2-L

512B – 1KB RAM

44/48-pin QFP

45

78K0/Kx2-L – Product Line-up

All devices support the On-Chip Debug function

xRAM sizew/o Op. Amp.

Flash (Byte)

32K

16K

8K

4K

768768

512512

384384

16-pinKY2-L

768768

512512

384384

20-pinKA2-L

1K 1K

768 768

512 512

30-pinKB2-L

1K 1K

768 768

512 512

44-pin / 48-pinKC2-L

xRAM sizew/ Op. Amp.

46



8-bit Timer TM5x1-ch, 1 x Compare/1 x PWM 78K0 Core

200 ns @ 10MHz1.8 to 5.5V

-40 to +85°C

Flash

Single Voltage FlashSecure Self-ProgrammingOn-Chip Debugging


16-Pin SSOP PackageMC (225 mil, 0.65 mm pin pitch)


On-chip Oscillator4 MHz (±2%)Note, 8 MHz (±5%),

30 kHz (±10%)

Up to 12 I/O lines


4 KB Flash 0.384 KB RAM 78F05558 KB Flash 0.512 KB RAM 78F0556

16 KB Flash 0.768 KB RAM 78F0557

Voltage Regulator

Serial Interface1-ch, UART (LIN capable)




Prg. Gain Amp./Op. Amp.1-ch / 1-ch for A/D-Converter each

Note: 4 MHz±2%@TA=-20 to +70 °C4 MHz±3%@TA=-40 to +85 °C

µPD78F055x – 16pin (78K0/KY2-L)(1/2)

47




200 ns @ 10MHz1.8 to 5.5V

-40 to +85°C

Flash





On-chip Oscillator4 MHz (±2%) Note, 8 MHz (±5%),

30 kHz (±10%)

Up to 12 I/O lines




Voltage Regulator






µPD78F055x – 16pin (78K0/KY2-L)(2/2)

48




200 ns @ 10MHz1.8 to 5.5V

-40 to +85°C

Flash






30 kHz (±10%)

Up to 16 I/O lines




Voltage Regulator







µPD78F056x – 20pin (78K0/KA2-L)(1/2)

49




200 ns @ 10MHz1.8 to 5.5V

-40 to +85°C

Flash






30 kHz (±10%)

Up to 16 I/O lines




Voltage Regulator






µPD78F056x – 20pin (78K0/KA2-L)(2/2)

50



8-bit Timer TM5x2-ch, 1 x Compare/1 x PWM each 78K0 Core

200 ns @ 10MHz1.8 to 5.5V

-40 to +85°C

Flash






30 kHz (±10%)

Up to 24 I/O lines


8 KB Flash 0.512 KB RAM 78F057616 KB Flash 0.768 KB RAM 78F057732 KB Flash 1.024 KB RAM 78F0578

Voltage Regulator







µPD78F057x – 30pin (78K0/KB2-L)(1/2)

51

µPD78F057x – 30pin (78K0/KB2-L)(2/2)



8-bit Timer TM5x2-ch, 1 x Compare/1 x PWM each 78K0 Core

200 ns @ 10MHz1.8 to 5.5V

-40 to +85°C

Flash






30 kHz (±10%)

Up to 24 I/O lines

Serial Interface1-ch, CSI (SPI)



Voltage Regulator






52




Real Time Clock Unit


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs




48-Pin QFP PackageGA (7 x 7 mm2, 0.50 mm pin pitch)



30 kHz (±10%)


Up to 38 I/O lines


Interrupt Controller10-12 external / 16 internal


Voltage Regulator






µPD78F058x – 44/48pin (78K0/KC2-L)(1/2)

53






1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






30 kHz (±10%)


Up to 42 I/O lines


Interrupt Controller10-12 external / 17 internal


Voltage Regulator






µPD78F058x – 44/48pin (78K0/KC2-L)(2/2)

54

78K0/Kx2-L - Peripherals

Note 1: CSI is not supported on 78K0/KB2-L with Op. Ampl.Only 1 CSI is supported on 78K0/KC2-L with Op. Ampl.

Note 2: Dependson product

Note 3: Higher number of internal interruptsfor products without Op. Ampl.

Flash [KB]

1 to 10 MHz extern and 4/8 MHz on-chip

KY2-L20 44


Timers

16-bit

RTC

SerialInterface

UART/CSI/I2c 1/1Note 1/1 channel

InterruptsNote 32 ext./10 int. 8 ext./12-13 int. 10 ext./16-17 int.

10-bit A/D-Converter 11 channels with Op. Amp.

8 channels without Op. Amp.

Ports10 I/O / 2 Inputs


KA2-L

32.768 kHz

1/-/1 channel

6 channels

14 I/O / 2 Inputs

1 channel

KC2-L16

48

Memory

Pin count

ClockSources

4 / 8 / 16 8 / 16 / 32 8 / 16 / 324 / 8 / 16384 / 512 / 768 384 / 512 / 768 512 / 768 / 1024 512 / 768 / 1024

33 I/O / 5 Inputs 37 I/O / 5 Inputs

30

8 / 16 / 32512 / 768 / 1024

30 kHz±10 % on-chip

8-bit 4 channels

7 channels 7 ch. with Op.Amp.4 ch. without Op.Amp.

21 I/O / 3 Inputs

4 ext./10 int.

KB2-L

3 channels


1/2Note 1/1 channel(s)

Operational AmplifierNote 2 0 channels / 2 channels0 channels / 1 channel

12 ext./16-17 int.

On-chip debug interface 1 channel

55

1MHz

260uA

Sub clockHALT mode

32.768KHz

<1uA

Internal low-speed Oscillator

+TMH1

STOP mode30KHz

0.8uA

Internal high-speed

oscillator

4MHz

650uA

Internal high-speed

oscillator

RTC Running

0.2uA

0

1

2

3

4

5

0.0.88uAuA

Standby current w/ int. LS Osc

K0Kx2-L

R M T

4uA

1.2uA0.9uA

78K0/Kx2-L – Current Consumption

56

78K0/Lx2 & Lx3“Scalable devices with

large-segment LCDController-Driver”

57

8-bit 78K0 – L Series

V850ESLow-End

32-bit

V850EHigh-End

32-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

78K0 L Series

48 to 100 pins 8- and 16-bit Timers10-bit A/D ConverterSerial Interfaces• UART with LIN Functionality• 3-wire (SPI)• I2C

LCD Controller / DriverUp to 288 segmentsInternal OscillatorsSecure Watchdog POC / LVI CircuitWide Operating Voltage RangeRoHS Compliant

58

Wide LCD application range• 78K0/Lx2: up to 40x4 seg., Booster, 128K Flash, 20MHz • 78K0/Lx3: up to 36x8 seg., ∆∑ A/D-Conv., 60K Flash, 20MHz• 78K0R/Lx3 up to 50x8 seg., 12-Bit A/D-Converter, 128K Flash, 20MHz

L Series - Roadmap

78K0 / LC3 (48pin)

78K0 / LD3 (52pin)

78K0 / LE3 (64pin)

78K0 / LF3 (80pin)

78K0 / LE2 (64pin)

78K0 / LF2 (80pin)

78K0 / LG2 (100pin)

78K0R / LG3 (100pin)

* under planning

78K0R / LH3 (80pin)

78K0R / LF3 (128pin)

59

78K0/Lx2

78K0/Lx2

V850ESLow-End

32-bit

V850EHigh-End

32-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

60

Flash (Byte)

128K

96K

60K

48K

80-pinLF2

32K

100-pinLG2

64-pinLE2

2K

3K 3K

5K

78K0/Lx2 – L Series Overview

24K

16K 768

1K

2K

1K

x RAM sizew/o AD conv. x RAM size

with AD conv.

1K1K

2K

3K

1K

1K

5K 5K

7K

1K1K

5K

7K

5K

x RAM sizew/o AD conv. and OCD interface

x RAM sizewith AD conv. and OCD interface

61

I²Cresistor ladder

capacitors

4 common lines,up to 40 segment lines

LCDcontroller/driver

mainclock

32.768kHz

78K0/Lx2 – 100% Compatibility with the K Series

I²CLCD

controller/driver

K_LINE

PINS

LCD

PINS

62

µPD78F036x – 64pin (78K0/LE2)

16-bit Timer TM02-ch , 2 x Capture/Compare



Watch Timer


1.8 to 5.5V-40 to +85°C

Flash



64-Pin QFP PackageGK (12 x 12 mm2, 0.65 mm pin pitch)GB (10 x 10 mm2, 0.50 mm pin pitch)




Up to 34 I/O lines



16 KB Flash 768 B RAM 78F036124 KB Flash 1 KB RAM 78F036232 KB Flash 1 KB RAM 78F0363

Voltage Regulator



Clock / Buzzer Output



LCD controller/driver20 seg x 4 com

Note 1: only 1 channel on 32K version

63

µPD78F037x – 80pin (78K0/LF2)(1/2)

16-bit Timer TM02-ch Note1, 2 x Capture/Compare



Watch Timer


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 34 I/O lines



24 KB Flash 1 KB RAM 78F037232 KB Flash 1 KB RAM 78F037348 KB Flash 2 KB RAM 78F037460 KB Flash 3 KB RAM 78F037596 KB Flash 5 KB RAM 78F0376

Voltage Regulator









64

µPD78F038x – 80pin (78K0/LF2)(2/2)




Watch Timer


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 26 I/O lines




Voltage Regulator








65

µPD78F039x – 100pin (78K0/LG2)




Watch Timer


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs


100-Pin QFP PackageGC (14 x 14 mm2, 0.5 mm pin pitch)GF (20 x 14 mm, 0.65 mm pin pitch)




Up to 40 I/O lines

Serial Interface2-ch Note1, CSI (SPI)



Voltage Regulator









66

78K0/Lx2 - Peripherals


Flash [KB]

1 to 20 MHz extern and 8 MHz (± 5%) on-chip

64 80


Timers

16-bit

Watch timer

SerialInterface

UART(LIN)/CSI

Interrupts


Ports


LE2

32.768 kHz

2/1 channel

24

2 channel Note1

LF2

80

Memory

Pin count

ClockSources

16/24/32 48/60/96/1280.75/1/1 2/3/5/7

34 40

24/32/48/60/961/1/2/3/5

240 kHz (±10 %) on-chip

8-bit 4 channels

26

7 ext. / 16 int.


HW-multiplier 1 channel Note1

7 ext. / 19 int.

LG2

1 channel

2/2 channel

5 channels

On- chip debug interface 1 channel

LCD controller/driver 26 x 4 40 x 436 x 420 x 4

Note 1: versions >=48K

7 ext. / 19 (16) int.

67

78K0/Lx3

78K0/Lx3

V850ESLow-End

32-bit

V850EHigh-End

32-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

68

78K0/Lx3 – L Series Overview

69

µPD78F040x – 48pin (78K0/LC3)(1/2)




8-bit Timer TM5x3-ch, 3 x Compare

Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 30 I/O lines


8 KB Flash 512 B RAM 78F040016 KB Flash 768 B RAM 78F040124 KB Flash 1 KB RAM 78F040232 KB Flash 1 KB RAM 78F0403

Voltage Regulator




LCD controller/driver18 seg x 8 com22 seg x 4 com

Manchester Code Gener.

70

µPD78F041x – 48pin (78K0/LC3)(2/2)




Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 30 I/O lines



Voltage Regulator








71

µPD78F042x – 52pin (78K0/LD3)(1/2)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 34 I/O lines

Serial Interface1-ch, 1x CSI(SPI)



Voltage Regulator






Remote Control Receiver

72

µPD78F043x – 52pin (78K0/LD3)(2/2)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 34 I/O lines




Voltage Regulator








73

µPD78F044x – 64pin (78K0/LE3)(1/3)




Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 46 I/O lines



16 KB Flash 768 B RAM 78F044124 KB Flash 1 KB RAM 78F044232 KB Flash 1 KB RAM 78F044348 KB Flash 2 KB RAM 78F044460 KB Flash 2 KB RAM 78F0445

Voltage Regulator








74

µPD78F045x – 64pin (78K0/LE3)(2/3)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 46 I/O lines




Voltage Regulator








75

µPD78F046x – 64pin (78K0/LE3)(3/3)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 46 I/O lines




Voltage Regulator






∆∑ A/D-Converter3 x 16-bit



76

µPD78F046x – 64pin (78K0/LE3)(3/3)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 62 I/O lines




Voltage Regulator









77

µPD78F047x – 80pin (78K0/LF3)(1/3)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 62 I/O lines

Serial Interface2-ch, 1x CSI(SPI), 1x AUTO CSI



Voltage Regulator







78

µPD78F048x – 80pin (78K0/LF3)(2/3)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 62 I/O lines




Voltage Regulator








79

µPD78F049x – 80pin (78K0/LF3)(3/3)





Real Time Clock


1.8 to 5.5V-40 to +85°C

Flash


Key Return Inputs






Up to 62 I/O lines




Voltage Regulator









80

78K0/Lx3 - Peripherals

Flash [KB]

1 to 10 MHz extern and 8 MHz (± 5%) trimmable on-chip

48 64


Timers

16-bit

Real Time Clock

SerialInterface

UART(LIN)/CSI

Interrupts

A/DConverter

Ports


LC3

32.768 kHz

2 channel

30

80

Memory

Pin count

ClockSources

8/16/24/32 16/32/48/600.5/0.75/1/1 0.75/1/1/2/2

46 62

16/24/32/48/600.75/1/1/2/2

240 kHz (±10 %) on-chip

8-bit 6 channels

34

5 ext. / 18 int.


7 ext. / 22int.

LF3

1 channel

2/2 channel

6 ch


LCD controller/driver 24 x 4 / 20 x 822 x 4 / 18 x 8

5 ext. / 20 int.

LD3 LF352

8/16/24/320.5/0.75/1/1

2/1 channel

24x4/20x832x4/28x8 32x4/28x840x4/36x810-bit SAR16-bit ∆∑

6 ch 8 ch 8 ch3 ch 3 ch

Manchester Code Gener. 1 channelRemote Control Receiver 1 channel

6 ext. / 20int.

81

8-bit 78K0 – I Series

V850ESLow-End

32-bit

V850EHigh-End

32-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

78K0 I Series

16 to 30 pins 8- and 16-bit Timers10-bit A/D ConverterSerial Interfaces• I2C Interface• UART/Manchester

CpmparatorsOp. Amps. / PGAInternal OscillatorsSecure Watchdog POC / LVI CircuitWide Operating Voltage RangeOn Chip Debug Interface

82

78K0/Ix2

78K0/Ix2

V850ESLow-End

32-bit

V850EHigh-End

32-bit

ASSP

Devices

78K0R16-bit

78K0SLow-End

8-bit

78K0High - End

8-bit

83

78K0/Ix2 – Product Line-up

µPD781201/3

5 x 10-Bit A/D

4 - 16 KB Flash

Comparator

8/16-Bit Timer

78K0/IY2

384B - 768B RAM

16-pin SSOP

µPD781211/3/4/5

6 x 10-Bit A/D

4 - 16 KB Flash

Comparator

8/16-Bit Timer

78K0/IA2

384B - 768B RAM

20-pin SSOP

µPD781223/4/5

9 x 10-Bit A/D

8 - 16 KB Flash

Comparator

8/16-Bit Timer

78K/IB2

512B - 1KB RAM

30-pin SSOP

Family Concept:+ 16 to 30 pins+ 4 KB - 16 KB Flash+ 384 B - 512 KB RAM+ up to 20MHz for core+ up to 40 MHz for timer X + 8 and 16 bit timers+ UART,IIC+ AD conv. /comparator+ POC/LVI/on-chip oscillator

84

78K0/Ix2 – I Series Overview


Flash (Byte)

16K

8K

4K

16-pinIY2

20-pinIA2

30-pinIB2

x RAM sizew/o Op. Amp. x RAM size

with Op. Amp.

768

512

384

768

512

384

768

512

768

512

768

512

384

768

512

384

85

µPD78F0750/1/2 – 16pin (78K0/IY2)(1/2)

16-bit Timer TM01-ch, 1xCapture/2xCompare




2.7V to 5.5V-40 to +85°C

Flash





On-chip Oscillator4 MHz (±2%), 30 kHz (±10%)

Up to 12 I/O lines



16 KB Flash 512 B RAM 78F0752

Voltage Regulator



Prg. Gain Amp. /OpAmp1-ch for AD converter /1-ch

2 x 16-bit Timer X1 x Capt./ AD trigger

4x Comp. eachTwo outputs each

Comparator3-chPLL

x10

86

µPD78F0740/1/2 – 16pin (78K0/IY2)(2/2)





2.7V to 5.5V-40 to +85°C

Flash






Up to 12 I/O lines



16 KB Flash 512 B RAM 78F0742

Voltage Regulator





Comparator3-chPLL

x10

87

µPD78F0753/4 – 20pin (78K0/IA2)(1/2)





2.7V to 5.5V-40 to +85°C

Flash






Up to 16 I/O lines



Voltage Regulator

Serial Interface1-ch, UART

(LIN and DALI capable)(Mancester)







Comparator3-chPLL

x10

88

µPD78F0743/4 – 20pin (78K0/IA2)(2/2)





2.7V to 5.5V-40 to +85°C

Flash






Up to 16 I/O lines



Voltage Regulator








Comparator3-chPLL

x10

89

µPD78F0755/6 – 30pin (78K0/IB2)(1/2)





2.7V to 5.5V-40 to +85°C

Flash






Up to 25 I/O lines



Voltage Regulator





Serial Interface1-ch I2C / 1-ch CSI




Comparator3-chPLL

x10

90

µPD78F0745/6 – 30pin (78K0/IB2)(2/2)





2.7V to 5.5V-40 to +85°C

Flash






Up to 25 I/O lines



Voltage Regulator





Serial Interface1-ch I2C / 1-ch CSI



Comparator3-chPLL

x10

91

78K0/Ix2 - Peripherals

Note 1: Only available on devices with OpAmp. (78F075x)

Flash [KB]

Up to 20 MHz and 4 MHz (±2%) on-chip with PLL

IY220


Timers16-bit timer0

SerialInterface

UART/I2c/CSI 1/1/1 channel

InterruptsNote 3 6 ext.

10-bit A/D-Converter

Ports 12


IA2

1/1/- channel

5 channels

16

1 channel

16

Memory

Pin count

ClockSources

8 / 164 / 8 / 16384 / 512 / 512 512 / 512

30

8 / 16512 / 512

30 kHz±10 % on-chip

8-bit 2 channels

6 channels 9 ch. with Op.Amp.

25

4 ext.

IB2

Watchdog 1 channel

Op. Amp./PGANote 1 1 channels / 1 channel


16-bit timer X 2 channel

Comparators 3 channel

92

16-bit Micro Series

93

78K0R“Super low-powerhigh performance

16-bit MCU’s”

94

78K0R K Series

44 to 144 pins 16-bit Timers10-bit A/D Converter8-bit D/A Converter

Serial Interfaces• LIN Functionality

Internal OscillatorsSecure Watchdog Wide Operating Voltage RangePOC / LVI CircuitRoHS CompliantWide Package Variety

16-bit 78K0R – K Series

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

95

78K0R/Kx3

78K0R/Kx3

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

96

Family Concept:+ 64 to 144 pins+ 64 KB - 512 KB Flash+ 4 KB - 30 KB RAM+ Same type of peripherals+ POC/LVI/on-chip oscillator

78K0R/Kx3 – Product Line-up

µPD78F1152A…6A

64-256 KB Flash

4-12 KB RAM

8 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KF3

80-pin QFP

µPD78F1162A…8A

64-512 KB Flash

4-30 KB RAM

16 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KG3

100-pin QFP

µPD781142A…6A

64-256 KB Flash

4-12 KB RAM

8 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KE3

64-pin QFP

µPD78F1174A…8A

128-512 KB Flash

8-30 KB RAM

16 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KH3

128-pin QFP

µPD78F1184A…8A

128-512 KB Flash

8-30 KB RAM

16 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KJ3

144-pin QFP

97

78K0R/Kx3 – K Series Overview


x RAM size

Flash (Byte)

384K

256K

64K

80-pinKF3

144-pinKJ3

12K

64-pinKE3

4K

192K

128K

96K 6K

512K

100-pinKG3

128-pinKH3

10K

8K

12K

4K

6K

10K

8K

12K

4K

6K

10K

8K

24K

30K

12K

10K

8K

24K

30K

12K

10K

8K

24K

30K

98

µPD78F114xA – 64pin (78K0R/KE3)

16-bit Timer Array Unit8-ch, Timer Mode or PWM Mode



78K0R Core50 ns @ 20MHz (13 MIPS)

1.8 to 5.5V-40 to +85°C

16 x 16-bit Multiplier

Flash


64 KB Flash 4.0 KB RAM 78F1142A96 KB Flash 6.0 KB RAM 78F1143A

128 KB Flash 8.0 KB RAM 78F1144A196 KB Flash 10.0 KB RAM 78F1145A256 KB Flash 12.0 KB RAM 78F1146A

DMA Controller2-ch

64-Pin LQFP PackageGK (12 x 12 mm2, 0.65 mm pin pitch)GB (10 x 10 mm2, 0.50 mm pin pitch)F1, (5 x 5 mm², 0.50 mm pin pitch)







Up to 55 I/O lines

I2C1-ch


Voltage Regulator

2 x Serial Array Unit4-ch each, up to 2 CSI (SPI), up to 1

simplified I2C, up to 3 UART

Key Return Inputs

NEW

99

µPD78F115xA – 80pin (78K0R/KF3)





1.8 to 5.5V-40 to +85°C


Flash



128 KB Flash 8.0 KB RAM 78F1154A196 KB Flash 10.0 KB RAM 78F1155A256 KB Flash 12.0 KB RAM 78F1156A

DMA Controller2-ch

80-Pin LQFP PackageGC (14 x 14 mm2, 0.65 mm pin pitch)GK (12 x 12 mm2, 0.50 mm pin pitch)







Up to 70 I/O lines

I2C1-ch


Voltage Regulator



D/A Converter2 x 8-bit

Key Return Inputs

100

µPD78F116xA – 100pin (78K0R/KG3)





1.8 to 5.5V-40 to +85°C


Flash



128 KB Flash 8.0 KB RAM 78F1164A196 KB Flash 10.0 KB RAM 78F1165A256 KB Flash 12.0 KB RAM 78F1166A384 KB Flash 24.0 KB RAM 78F1167A512 KB Flash 30.0 KB RAM 78F1168A

DMA Controller2-ch

100-Pin LQFP PackageGF (14 x 20 mm2, 0.65 mm pin pitch)GC (14 x 14 mm2, 0.50 mm pin pitch)





External Memory Access



Up to 88 I/O lines

I2C1-ch


Voltage Regulator




Key Return Inputs

101

µPD78F117xA – 128pin (78K0R/KH3)





1.8 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch

128-Pin LQFP PackageGF (14 x 20 mm2, 0.50 mm pin pitch)








Up to 116 I/O lines

I2C1-ch


Voltage Regulator




Key Return Inputs

102

µPD78F118xA – 144pin (78K0R/KJ3)





1.8 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch

144-Pin QFP PackageGJ (20 x 20 mm2, 0.50 mm pin pitch)








Up to 132 I/O lines

I2C1-ch


Voltage Regulator




Key Return Inputs

103

78K0R/Kx3 – Peripherals

Flash [KB]

2 to 20 MHz extern and 8 MHz on-chip

KE380 100 128

RAM [KB]Main ClockSubclockWatchdog 240 kHz±10 % on-chip

Timers16-bitRTCWatchdog

8 channels

1 channel1 channel

SerialInterface

UART/CSI/I2C

I2C

4/6/4 channel(s)

1 channel

Interrupts 13 ext. / 25 int. 13 ext. / 28 int. 13 ext. / 32 int.


Ports51 88

DMA-Controller 2 channels

POC / LVI Power-On-Reset: 1.61V±0.09V, Power-Down-Reset: 1.59V±0.09V / LVI: 1.91V to 4.22V

KF3

32.768 kHz

3/2/1 channel(s) 4/4/2 channel(s)

8 channels

70

12 channels

8-bit D/A-Converter 2-channels

KH3 KJ364

144

Memory

Pin count

ClockSources

64 / 96 / 128 / 192 / 256

64/96/128/192/256/384/512

128 / 192 / 256 / 384 / 512

128 / 192 / 256 / 384 / 512

KG3

64 / 96 / 128 / 192 / 256

4/6/8/10/12 4/6/8/10/12 4/6/8/10/12/24/30 8/10/12/24/30 8/10/12/24/30

116 132

HW Multiplier 16 x16

104

Introducing78K0R/Kx3-L

“Industry LeadingLow Power

16-bit MCU’s”

105

78K0R Low-power K Series

44 to 64 pins 16-bit Timers10-bit A/D ConverterSerial Interfaces

• LIN Functionality

Analog Functions• Comparator• Operational Amplifier

Internal OscillatorsLow power consumptionSecure Watchdog POC / LVI CircuitWide Package VarietyRoHS Compliant

16-bit 78K0R – Low-Power K Series

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

106

78K0R/Kx3-L

78K0R/Kx3-L

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

107

78K0/Kx28-bit

30-80pin

78K0S/Kx1+8-bit

10-30pin

78K0R/Kx316-bit

64-144pin

78K0R/Next16-bit

78K0/Kx2-L16-48pin

78K0R/Kx3-L44-100pin

Wide operating voltage range

1.8V to 5.5VLow-powerInternal Oscillator

With ±2% accuracyAnalog function

Pin

count

Low Power 78K Series Overview

108

Saving Energy & Saving Cost

“Ultra Low Power”• 5.3mA @ 20MHz operation• 3mA @ 10MHz operation• 190uA @ 1MHz operation • 1uA @ 32KHz+RTC

“High Performance”• 16.9DMIPS @ 20MHz• 0.94mW/MIPS (@ 3V)

“Selectable Clock”• 1MHz for low-power system• 8MHz/20MHz for high-speed system

(+/-1% accuracy)

“Rich Analog”• 12 channels 10bit A/D converter

with 3us conversion• x1 to x12 Programmable Gain Amplifier• 2 Comparator channels

“1.8V Programming”• Operation : 1.8V~5.5V• Flash programming : 1.8V~5.5V

to further extend battery life

78K0R/Kx3-L Concept

109

µPD78F1000...3

16-64 KB Flash

1-3 KB RAM

10/11 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KC3-L

44-pin/48-pin QFP

µPD78F1004…6

32-64 KB Flash

1.5-3 KB RAM

11 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KD3-L

52-pin QFP

Family Concept:+ 44 to 64 pins+ 16 KB - 64 KB Flash+ 1 KB - 3 KB RAM+ Same type of peripherals+ POC/LVI/on-chip oscillator+ Low power consumption µPD78F1007…9

128-512 KB Flash

1.5-3 KB RAM

12 x 10-Bit A/D

16-Bit Timer Unit

78K0R/KE3-L

64-pin QFP/BGA

78K0R/Kx3-L – Product Line-up

110

Flash (Byte)

64K

48K

32K

16K

3K 3K 3K 3K

2K 2K 2K 2K

1.5K 1.5K 1.5K 1.5K

1K

44-pin 48-pinKC3-L

52-pinKD3-L

64-pinKE3-L

x RAM size

128K

96K


4K 4K

80-pinKF3-L

100-pinKG3-L

8K 8K

6K 6K

Portfolio Extension

78K0R/Kx3-L – K Series Overview

111

µPD78F100x – 44pin (78K0R/KC3-L)(1/2)






1.8 to 5.5V-40 to +85°C

16 x 16-bit Multiplier32 / 32-bit Divider

Flash


DMA Controller2-ch


Comp. / Op. Amplifier2-ch / 1-ch




On-chip Oscillator1/8/20 MHz, 30 kHz


Up to 37 I/O lines

I2C1-ch


16 KB Flash 1.0 KB RAM 78F100032 KB Flash 1.5 KB RAM 78F100148 KB Flash 2.0 KB RAM 78F100264 KB Flash 3.0 KB RAM 78F1003

Voltage Regulator

Serial Array Unit4-ch, up to 3 CSI (SPI), up to 1


112

µPD78F100x – 48pin (78K0R/KC3-L)(2/2)






1.8 to 5.5V-40 to +85°C


Flash


DMA Controller2-ch








Up to 41 I/O lines

I2C1-ch



Voltage Regulator



113

µPD78F100x – 52pin (78K0R/KD3-L)






1.8 to 5.5V-40 to +85°C


Flash


DMA Controller2-ch








Up to 45 I/O lines

I2C1-ch



Voltage Regulator



114

µPD78F100x – 64pin (78K0R/KE3-L)






1.8 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch




64-Pin QFP PackageFC (5 x 5 mm2, 0.50 mm pin pitch)GA (7 x 7 mm2, 0.40 mm pin pitch)

GB (10 x 10 mm2, 0.50 mm pin pitch)GK (12 x 12 mm2, 0.65 mm pin pitch)




Up to 55 I/O lines

I2C1-ch


Voltage Regulator



115

78K0R/Kx3-L – Peripherals

Memory

Pin count

Flash [KB]

2 to 20 MHz extern and 1/8/20 MHz on-chip

KC3-L KD3-L KE3-L44 48 52 64

RAM [KB]16 / 32 / 48 / 64 32 / 48 / 64 32 / 48 / 64 32 / 48 / 64

1 / 1.5 / 2 / 3 1.5 / 2 / 3 1.5 / 2 / 3 1.5 / 2 / 3

ClockSources

Main ClockSubclockWatchdog

32.768 MHz30 kHz±10 % on-chip


8 channels1 channel1 channel

SerialInterface

UART/CSI/I2CI2C

3/2/1 channel(s)1 channel

AnalogComparatorOp. Amplifier

Ports37 41 45 55

2 channels1 channel

A/D-Converter 10 channels 11 channels 12 channels

Interrupts 9 ext. / 24 int. 9 ext. /25 int.



116

78K0R/Lx3“High performance, super-low

power, enhanced analog”

117

78K0R L Series

80 to 128 pins 16-bit Timers12-bit A/D Converter12-bit D/A ConverterLCD Controller/Driver

• Voltage boosting method, capacitor split method and resistance splitting method supported

• Six different display modes• Up to 400 segments (50 x 8)

Analog Functions• Comparator• Operational Amplifier


Internal OscillatorsSecure Watchdog Wide Operating Voltage RangePOC / LVI CircuitRoHS CompliantWide Package Variety

16-bit 78K0R – L Series

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

118

78K0R/Lx3

78K0R/Lx3

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

119

Wide LCD application range• 78K0/Lx2: up to 40x4 seg., Booster, 128K Flash, 20MHz • 78K0/Lx3: up to 36x8 seg., ∆∑ A/D-Conv., 60K Flash, 20MHz• 78K0R/Lx3 up to 50x8 seg., 12-Bit A/D-Converter, 128K Flash, 20MHz

L Series - Roadmap

78K0 / LC3 (48pin)

78K0 / LD3 (52pin)

78K0 / LE3 (64pin)

78K0 / LF3 (80pin)

78K0 / LE2 (64pin)

78K0 / LF2 (80pin)

78K0 / LG2 (100pin)

78K0R / LG3 (100pin)

* under planning

78K0R / LH3 (80pin)

78K0R / LF3 (128pin)

120

78K0R/Lx3 – Product Line-up

Family Concept:+ 80 to 128 pins+ 64 KB - 128 KB Flash+ 4 KB - 7 KB RAM+ 12-Bit A/D with Op.Amp.+ Up to 400 LCD segments (50 x 8)+ Same type of peripherals+ POC/LVI/on-chip oscillator

µPD78F1503..5

64-128 KB Flash

4-7 KB RAM

12-Bit A/D

288 seg. (36x8)

78K0R/LG3

100-pin QFP

µPD78F1506..8

96-128 KB Flash

4-7 KB RAM

12-Bit A/D

400 seg. (50x8)

78K0R/LH3

128-pin QFP

µPD78F1500..2

64-128 KB Flash

4-7 KB RAM

12-Bit A/D

216 seg. (27x8)

78K0R/LF3

80-pin QFP

121

78K0R/Lx3 – L Series Overview


x RAM size

Flash (Byte)

128K 7K

6K

80-pinLF3

100-pinLG3

128-pinLH3

96K

64K 4K

7K

6K

4K

7K

6K

4K

122

µPD78F150x – 80pin (78K0R/LF3)





1.8 to 5.5V-40 to +85°C


Flash




DMA Controller2-ch


Operational Amplifier2-ch


80-Pin QFP PackageGK (12 x 12 mm2, 0.5 mm pin pitch)GC (14 x 14 mm2, 0.65 mm pin pitch)




Up to 51 I/O lines

2 x Serial Array Unit2-ch/4-ch, up to 2 CSI (SPI), up to 2



Voltage Regulator


Real Time Clock Unit Key Return Inputs

LCD Controller / DriverUp to 27 x 8 Segments

Voltage Reference

123

µPD78F150x – 100pin (78K0R/LG3)





1.8 to 5.5V-40 to +85°C


Flash




DMA Controller2-ch




100-Pin QFP PackageGC (14 x 14 mm2, 0.5 mm pin pitch)




Up to 67 I/O lines



1 x I2C


Voltage Regulator


Real Time Clock Unit Key Return Inputs


Voltage Reference

124

µPD78F150x – 128pin (78K0R/LH3)





1.8 to 5.5V-40 to +85°C


Flash




DMA Controller2-ch




128-Pin QFP PackageGF (14 x 20 mm2, 0.5 mm pin pitch)




Up to 83 I/O lines



1 x I2C


Voltage Regulator



Voltage Reference


Key Return Inputs

125

78K0R/Lx3 – Peripherals

Memory

Pin count

Flash [KB]

2 to 20 MHz extern and 8 MHz on-chip

LF3 LH380 100 128

RAM [KB]64 / 96 / 128 64 / 96 / 128 64 / 96 / 128

4 / 6 / 7 4 / 6 / 7 4 / 6 / 7

ClockSources

Main ClockSubclockWatchdog 30 kHz±10 % on-chip


6 channels

1 channel1 channel

SerialInterface

UART/CSI/I2C

I2C

4/4/2 channel(s)

1 channel

LCD Controller / Driver

Interrupts 8 ext. / 24 int. 12 ext. / 29 int. 13 ext. / 29 int.

36 x 8 segments


Ports 51 83


POC / LVI Power-On-Reset: 1.61V±0.09V, Power-Down-Reset: 1.59V±0.09V LVI: 1.91V to 4.22V

LG3

32.768 kHz

3/2/2 channel(s) 4/3/2 channel(s)

8 channels

67

8 channels

47 x 8 segments 50 x 8 segments

12-bit D/A-Converter 2-channels

126

78K0R/Lx3 – Performance

127

78K0R/Ix3 ASSP16-bit Motor ControlMicrocontrollers

128

78K0R I Series

30 to 64 pins 16-bit Timers

• Inverter Timer with Motor Control Functionality

• PWM Output Operation with a max. resolution of 40MHz

• Dead-Time Generation10-bit A/D ConverterComparators

• Fail-Safe Application to set PWM output to high-impedance in case of over-current


Internal OscillatorsSecure Watchdog POC / LVI CircuitRoHS Compliant Wide Package Variety

16-bit 78K0R – I Series

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

129

78K0R/Ix3

78K0R/Ix3

V850ESLow-End

32-bit

V850EHigh-End

32-bit

78K0High - End

8-bit

78K0SLow-End

8-bit

ASSP

Devices

78K0R16-bit

130

78K0R/Ix3 – The Concept Parts

The Complete Solution

78K0R/Ix3

131

78K0R/Ix3 – Product Line-up

Family Concept:+ 30 to 64 pins+ 16 KB - 64 KB Flash+ 1 KB - 3 KB RAM+ 16-Bit Timer Array Unit+ Serial Interface Array Unit+ Same type of peripherals+ POC/LVI/on-chip oscillator

µPD781201/3

6 x 10-Bit A/D

16-32 KB Flash

Comparator

16-Bit Timer Unit

78K0R/IB3

1-1.5 KB RAM

30-pin SSOP

µPD781211/3/4/5

8 - 11 x 10-Bit A/D

16-64 KB Flash

Comparator

16-Bit Timer Unit

78K0R/IC3

1-3 KB RAM

38-p. SSOP 44-/48-p. QFP

µPD781223/4/5

12 x 10-Bit A/D

32-64 KB Flash

Comparator

16-Bit Timer Unit

78K0R/ID3

1.5-3 KB RAM

52-pin QFP

µPD781233/4/5

12 x 10-Bit A/D

32-64 KB Flash

Comparator

16-Bit Timer Unit

78K0R/IE3

1.5-3 KB RAM

64-pin QFP

132

78K0R/Ix3 – I Series Overview


x RAM size

Flash (Byte)

64K

48K

32K

16K

3K 3K

2K 2K

1.5K 1.5K 1.5K 1.5K

1K

38-pin 44-pin 48-pinIC3

52-pinID3

64-pinIE3

1.5K

30-pinIB3

3K

2K

1.5K

1K 1K 1K

133

µPD78F120x – 30pin (78K0R/IB3)

16-bit Timer Array Unit12-ch, 40MHz, A/D Timer Trigger, 6-

phase PWM with Dead Time




2.7 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch




30-Pin QFP PackageMC (7.62 (300 mil), 0.65 mm pin pitch)


On-chip Oscillator8 MHz/40 MHz, 30 kHz


Up to 23 I/O lines



I2C1-ch


Voltage Regulator

134

µPD78F121x – 38pin (78K0R/IC3)(1/3)






2.7 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch




38-Pin MC PackageMC (7.62 (300 mil), 0.65 mm pin pitch)




Up to 31 I/O lines



I2C1-ch


Voltage Regulator

135

µPD78F121x – 44pin (78K0R/IC3)(2/3)






2.7 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch








Up to 37 I/O lines



I2C1-ch


Voltage Regulator

136

µPD78F121x – 48pin (78K0R/IC3)(3/3)







2.7 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch








Up to 41 I/O lines



I2C1-ch


Voltage Regulator

137

µPD78F123x – 52pin (78K0R/ID3)







2.7 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch




52-Pin LQFP PackageGB (10 x 10 mm2, 0.65 mm pin pitch)




Up to 47 I/O lines



I2C1-ch


Voltage Regulator

138

µPD78F123x – 64pin (78K0R/IE3)







2.7 to 5.5V-40 to +85°C


Flash



DMA Controller2-ch




64-Pin LQFP PackageGB (10 x 10 mm2, 0.50 mm pin pitch)GK (12 x 12 mm2, 0.65 mm pin pitch)




Up to 55 I/O lines



I2C1-ch


Voltage Regulator

139

78K0R/Ix3 – Peripherals

Memory

Pin count

Flash [KB]

2 to 20 MHz extern, 8/40 MHz on-chip (CPU max. 20 MHz)

IB3 ID3 IE330 38 / 44 / 48 52 64

RAM [KB]16 / 32 16 / 32 / 48 / 64 32 / 48 / 64 32 / 48 / 641 / 1.5 1 / 1.5 / 2 / 3 1.5 / 2 / 3 1.5 / 2 / 3

ClockSources

Main ClockSubclockWatchdog 30 kHz±10 % on-chip


12 channels (incl. Motor Control Feat.: 6-phase PWM with Dead Time, A/D Timer Trigger)1 channel

1 channel

SerialInterface

UART/CSI/I2C

I2C

2/3/1 channel(s)

1 channel

AnalogComparatorOp. Amplifier

Ports23 31 / 37 / 41 47 55

2 channels1 channel

A/D-Converter6 channels 11 channels 12 channels

Interrupts 6 ext. / 31 int. 8 ext. / 34 int.



IC3

32.768 kHz

2/1/1 channel(s) 2/1-3/1 channel(s)

1 ch (48-pin)

8-11 channels

8 ext. / 33-34 int.

140

9. The 78K Architecture

Memory OrganizationProcessor Registers

Mirror AreaPipeline Structure

141

78K0S Memory Organization

Up to 8 KB on-chip Flash • Linear addressing

Up to 256 B on-chip RAM • Short address area 256 byte• Less opcode• Fast memory access

Flash memory is segmented in 256 Byte blocks

8 x 8-Bit register area• Core integrated (not mapped into

RAM)

142

78K0 Memory Organization

Up to 128 KB on-chip Flash• Linear addressing up to 60K• Banking is used for more than 60K

Up to 7 KB on-chip RAM • Short address area 256 byte• Less opcode• Fast memory access

Flash memory segmented in 1KByte blocks

32 x 8-Bit register area

Code execution possible in Internal Expansion RAM

143

78K0 Banked Memory Organization

Interrupt service routines must be located in the common area

Full code banking support by IAR Compiler

144

78K0R Memory Organization

Up to 512 KB on-chip Flash (max. 960KB)• Linear addressing

Up to 30 KB on-chip RAM (max. 64 KB)

Flash memory segmented in:• 1K blocks (78K0R/Ix3/Kx3-L/Fx3)• 2K blocks (78K0R/Kx3)

32 x 8-Bit register area

145

Processor Registers

15

Program Counter• 16-bit / 20-bit register that holds the address information of the next

instruction to be executed• PC is automatically incremented according to the number of bytes of

the instruction to be fetched• Reset signal generation sets the reset vector table values at addresses

0000H and 0001H to the program counter

− 78K0S, 78K0:

− 78K0R:

146

Processor Registers

Program Status Word• 8-bit register consisting of various flags set/reset by instruction

execution• Program status word contents are stored in the stack area upon

interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions

− 78K0S:

− 78K0:

− 78K0R:

IE: Interrupt enable flag AC: Auxiliary CarryZ: Zero Flag CY: Carry flagRBS0, RBS1: Register bank select flagsISP: Interrupt service priority flag

147

Processor Registers

F

F

F

F

F

General Purpose Registers (78K0, 78K0R)• 8 x 8-bit or 4 x 16-bit register

− Flexible use• 4 register banks (For 78K0S is only register bank 0 available.)• switch by software• no push / pop• flexible use by interrupts

148

Processor Registers

Special Function Registers• Registers to control the peripheral hardware, e.g. ports, timers, etc.• Delivering status information of the peripheral hardware• Located in the address area 0xFFF00 to 0xFFFFF (K0R)• Located in the address area 0xFF00 to 0xFFFF (K0 and K0S)

149

IMS Register (78K0)• Used to adapt the internal Flash ROM and high-speed RAM

• Adaptation of the OCD device to the corresponding mass product

IXS Register (78K0)• Defines the internal expansion RAM size

Registers must be initialized after reset !

Processor Registers

150

Mirror Area (78K0R only)

Purpose• Mirror area allows a “near”

access to constant data located in ROM (For devices with >64KB Flash memory only)

Size of the mirror area• Depending on the RAM size• Larger RAM size causes a

smaller mirror area• Maximum mirror area size is

55.75 KB @ 4KB RAM size

151


• Reading data from F0000H to FFFFFH can be done by an instructionwithout using the ES registers as an operand

• E.g. Data move instruction− MOV A, !addr16 instead of MOV ES, #byte

MOV A, ES:!addr16

ClocksInstructionGroup

Mnemonic Operands Bytes

Note 1 Note 2

A, !addr16 3 1 4 A (addr16)

ES, #byte 2 1 - ES byte

8-bit data transfer

MOV

A, ES:!addr16 4 2 5 A (ES, addr16)

Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data access.

2. When the program memory area is accessed.

Operation

152


Processor mode control register (PMC)• This register selects the flash memory space for mirroring to area from

F0000H to FFFFFH• Set PMC only once during the initial settings prior to the DMA

Controller.

− PMC register is written in CSTARTUP routine according to the settings in the Project>Options of the IAR Embedded Workbench

153

Pipeline Structure (78K0R only)

Features• Three-stage pipeline control is used to enable single-cycle execution of

almost all instructions• Instructions are executed in three stages: instruction fetch (IF),

instruction decode (ID), and memory access (MEM)

tSET1 P1.0

CLR1 P1.0

t = 1 clock

typical instructions

154


Numbers of Operation clocks

Access to constants in flash memory• Pipeline operation is stopped at the MEM stage• Number of operation clocks will be increased

Instruction fetch from RAM• Instruction queue becomes empty because reading from RAM takes

more time• CPU waits until the data is set to the instruction queue

155


Instruction fetch from RAM• Instruction queue becomes empty because reading from RAM takes

more time. CPU waits until the data is set to the instruction queue.

Data access to external data memory• CPU is set to wait mode during data access from external memory.

Instruction fetch from external memory• Instruction queue becomes empty because reading from the external

memory takes more time• CPU waits until the data is set to the instruction queue.

156

10. The 78K On-Chip Peripherals

Clock generator, Ports,

Timers,A/D-Converter,

Serial Interfaces, Interrupts…

78K0R16-bit CPU Core

Flash Memory256 KB

RAM12 KB

Main Clock2-20 MHz

On-Chip Osc.8 MHz

* no existing device

157

Internal Structure

8-Bit (78K0) / 16-bit (78K0R) CPU core • Operates at up to 20MHz [@ VDD = 4.0V-5.5V (78K0), @ VDD = 2.7V-5.5V

(78K0R)]• Minimum instruction cycle time 100ns (78K0) , 50ns (78K0R)

Wide operating voltage range• VDD = 1.8V-5.5V @5MHz• 8MHz High-speed on-chip oscillator• On-chip voltage regulator (2.5V) leads to low current consumption and low EMI

Reg.VDD

VSS

HS Osc.

LS Osc.

CPU

Flash

RAMPOC

Peripherals LVI Oscillationcircuit

Port

2.5VREGC

158

Clock Generator

Up to four different oscillators• Main system clock oscillator up to

− 10 MHz (78K0S, 78K0/Kx2-L) − 20 MHz (others 78K0, 78K0R)

• Internal “high speed” on-chip oscillator (typ. 1/4/8/20 MHz)• Internal “low speed” on-chip oscillator (typ. 30/240 kHz)• Subsystem clock oscillator (32.768 kHz) (78K0, 78K0R)

CPU core operation on all clocks possible (except 240 kHz on-chip osc.)• Speed can be selected by software• Reduces power consumption• Adaptation to VDD level• Best speed / IDD relation

159

Oscillator terminals can be used as ports, if no external oscillator is connected.

Clock Generator

Ext. Oscillator:2 - 20 MHz

(others 78K0/78K0R)2 - 10 MHz

(78K0S/78K0/Kx2-L)

Int. Oscillator:

240/30 kHz ±10%

Int. Oscillator:

20/8/4/1 MHz ±

Ext. Oscillator:

32.768 kHz

CPU

Watchdog

Peripherals

SelectorSelector

78K0S78K0

160

Clock Generator

Possible chip operation• Main system clock and high-speed on-chip oscillator

− Operation mode− Different speed selections by software are possible

− Halt mode− Oscillator is operating, CPU core is stopped, peripherals are active− Halt mode release possible with interrupts, reset, by subsystem clock

supplied peripherals or watchdog timer

− Stop mode− Oscillator is stopped, CPU core is stopped, peripherals are not active− Stop mode release possible with external interrupts, reset, by

subsystem clock supplied peripherals or watchdog timer

• Low-speed on-chip oscillator− Operation mode

− Only the watchdog timer can operate with the low-speed on-chip oscillator

− For 78K0S and 78K0 also Timer H1 can operate with the low-speed on-chip oscillator

161

Clock Generator

Possible chip operation• Subsystem clock

− Operation mode− CPU core and peripherals are using subsystem clock

− Halt mode− CPU core is stopped, peripherals are using subsystem clock− Halt mode release possible with external interrupts, reset,

peripherals supplied by subsystem clock or watchdog timer

162

Clock Generator

Start-up behaviour of the oscillators (78K0S)

163

Normal operation modeStabilisation time Clock generator init

The CPU core is operating from here onwards

The switch over of the CPU clock must be done by software, if necessary

The external oscillator must be switched on by software

Clock Generator

Start-up behaviour of the oscillators (78K0, 78K0R)

164

Initialization of Clock Generator (78K0)

Osc > 10 MHzSetup the oscillatorsExternal quartz / resonator on X1,X2No subclockXT1, XT2 used as ports

void initClockGenerator(void){

AMPH = 1; EXCLK = 0; OSCSEL = 1; EXCLKS = 0;OSCSELS = 0;

MOC = 0x00;

while(OSTC <=0x10) {__no_operation();}

PCC = 0x00;

XSEL = 1; MCM0 = 1;

while(MCS != 1){__no_operation();

}

RCM = 0x01; }

Start oscillator

Provide ext. clock to peripherals and core

Wait for stable main oscoperation.Depends on the resonator

High speed modeno internal prescaler is used

Wait for internalswitch form internalosc. to external osc.

stop internal high speed ring oscillator

165

Initialization of Clock Generator (78K0R)

void OscInit(void) // Clock generator initialization{

CMC = 0x51; // Set up the operation mode of the X1/P121, X2/EXCLK/P122,// XT1/P123, and XT2/P124 pins

OSTS = 0x07; // Select the required oscillator stabilization timeCKC = 0x08; // Select the CPU and the peripheral hardware clock and the prescaler. MSTOP = 0; // Enable X1 input clock operationOSMC = 0x01; // Set operation speed mode control, if fX1 > 10MHz

while (OSTC < 0xFF) // Wait until X1 input clock stabilization time has been changed{

__no_operation();}

do{ // Switch CPU clock to fX1 input clock and

MCM0 = 1; // check, if CPU is operating on fX1 input clock} // If not, switch CPU clock again to fX1 input clock and check againwhile (MCS != 1);

// HIOSTOP = 1; // Switch off the high-speed on-chip oscillator and// XTSTOP = 1; // the subclock if not needed

PER0 = 0xFF; // Switch on the peripheral clock supplyPER1 = 0x01;

}

166

Definition of instruction cycle time (78K0: fCPU ≤ 20MHz, 78K0S: fCPU ≤ 10MHz)

• One instruction clock cycle (TCYCL) is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).

• Example (for 78K0):

− fX = 20MHz, PCC = 0x00 => fCPU = 20MHz => TCYCL = 1/ fCPU = 50ns (78K0)

− e.g. MOV r,#byte : TINST = 4 clocks * TCYCL => TINST = 4 * 50ns = 200ns (78K0)

Clock Generator

167

Clock Generator

Definition of instruction cycle time (78K0R: fCPU ≤ 20MHz)

• One instruction clock cycle (TCYCL) is one cycle of the CPU clock (fCPU) selected by the processor clock control register (CKC).

• Example (for 78K0R):

− fX = 20MHz, CKC = 0x18 => fCPU = 20MHz => TCYCL = 1/ fCPU = 50ns

− e.g. MOV r,#byte : TINST = 1 clock * TCYCL => TINST = 1 * 50ns = 50ns

168

Clock Generator (78K0)

Note: This is an example for K0

Minimum instruction cycle time vs. supply voltage

169

Clock Generator (78K0R)

Note: This is an example for K0R

Minimum instruction cycle time vs. supply voltage

170

Clock Generator

Low current consumption (78K0/Kx2)78F0533 current consumption 8MHz intern

0.001

0.01

0.1

1

10

100

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd / V

Idd

/ mA

PCC=0RUN

PCC=0per. onRUNPCC=4HALT

main stoppedLSR and TMH1 RUN

fxt/2 CPU RUN

CPU with fxt/2 into HALT mode

PCC = 1 per. ON RUN

PCC=2 per. ON RUN

Note: The above measured IDD data are only characteristic data and cannot be guaranteed.

171

Clock Generator

Low current consumption (78K0/Kx2)

Current Consumption 78F0533 20MHz

0.0

0.0

0.1

1.0

10.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Vdd / V

IDD

/ m

A

PCC = 0 RUNPCC=0/ per. ON/ RUNPCC=4 / HALTMain stopped/ LSR & TMH1 RUNCPU RUN with fxt/2 into HALT modefxt/2 CPU RUN


172

78F1142 VDD vs IDDMAIN RUN(PER0=FFH)

0

1

2

3

4

5

6

7

8

9

0 1 2 3 4 5 6

VDD(V)

IDD

(mA

)

8MHz_Ring

10MHz_X'tal

20MHz_X'tal

Clock Generator

Low current consumption (78K0R/Kx3)


173

78F1142 VDD vs IDDSUB＆STOP

0

1

2

3

4

5

6

7

8

0 1 2 3 4 5 6

SUB_RUN

SUB_HALT

STOP

IDD

(µA

)

VDD(V)

Clock Generator

Low current consumption (78K0R/Kx3)


174

Clock Generator

Low current consumption

175

Ports

Pin I/O Circuit Types• CMOS I port (2)

− Schmitt-trigger behavior• CMOS O ports (3-C)

− Output only• CMOS I/O port (5-AG)

− Switchable between in- and output− Internal pull-up settable by

software• CMOS I/O port (5-AN)


software− Switchable CMOS or TTL input

characteristic• CMOS I/O port (8-R)


software− Schmitt-trigger behavior

• CMOS I/O port (11-G)− Switchable between A/D converter,

logical input and output

176

Ports

Pin I/O Circuit Types• CMOS I port (12D)

− Switchable between A/D converter, logical input and output

• CMOS I/O port (13-P)− Switchable between input and

N-ch open-drain output• CMOS I/O port (13-R)

− Schmitt-trigger behaviour− Switchable between in- and N-

ch open-drain output• CMOS I/O port (37-A)

− Switchable between in- and output

− Selectable oscillator input function

• CMOS I/O port (39) − Operation mode input− Programming Mode or Normal

operation mode selectable

177

Ports

Example for shared function• Alternate function could be either wired-OR or wired-AND • No port function control registers

Caution:Take care for the correct port settings.

178

Power-On-Clear Circuit

Functions• Generates internal reset signal at power on• Compares supply voltage VDD and detection voltage

VPOC = 1.59 ± 0.09VNote (2.1V @ K0S) and generates internal reset signal when VDD < VPOC

• CPU can be also released by LVI, selectable by option byte

Block Diagram

Note:These are preliminary values and subject to change.

179

VPOC=1.59V

VDD

tmin.

0.5V

/ms

3.6ms

1.8V

(1) Internal resetrelease

(2) Start internal state machine“read“option byte

(3) Start CPU operationAssumed, thatVDD exceeds 1.8Vafter 3.6ms

Operation• Reset not used

− Option byte: POCMODE = 0

• Advantage: Can be used in 1.8 V applications!

Power-On-Clear Circuit (78K0)

180

VPOC=1.59V

VDD

t4.14ms

2.07V


(2) Start internal state machine“read“option bytestart LVI

(3) Start CPU operationVDD exceeds 2.07Vafter 4.14ms

Operation• Reset used or unused

− Option byte: POCMODE = 1

• Can be used in applications with VDD ≥ 2.7V

Power-On-Clear Circuit (78K0)

181

Power-On-Clear Circuit (78K0R)

Operation• Reset not used

− Option byte: LVIOFF = 1

• Advantage: Can be used in 1.8V applications!

VPOC=1.59V

VDD

tmin.

0.5V

/ms

3.6ms

1.8V



(3) Start CPU operationAssumed, thatVDD exceeds 1.8Vafter 3.6ms

182


Operation• Reset used


• Advantage: Can be used in 1.8V applications!

VDD

tmin.

0.5V

/ms

1.8VVPOC=1.59V

Resett

3.6ms1.9ms




183


Operation• Reset used or unused


• Advantage: Can be used in applications with VDD ≥ 2.07V

VPOC=1.59V

VDD

t4.14ms

2.07V


(2) Start internal state machine“read“option bytestart LVI


184

Low-Voltage Indicator

Functions• Compares supply voltage VDD and detection voltage VLVI, and generates an

internal interrupt signal or internal reset signal when VDD < VLVI

• 16 internal detection levels of supply voltage or 1 external level (1.21V) can be selected by software

• Changeable between interrupt or reset function • Operable in STOP mode

Block Diagram

185


Detection voltage levels (for 78K0S)

186


Detection voltage levels (for 78K0R)

Note:These are preliminary valuesand subject to change.

187

16-bit Timer TM0 (78K0S, 78K0)

Operation Modes• Interval Timer• External event counter• Square-wave output• PPG output• Pulse width measurement• Timer output

Features• Selectable clock sources• 1 shared timer input/output port• 1 timer input port• 16-bit capture/compare

188


Block Diagram

189


TM00

CR000

CR010Ti000

INTTM000

INTTM010

f timer

input signal

rising edge startsthe timer

fallig edge force acapture in CR000

78K0/Kx

edgedetector

Example for pulse width measurement• Pulse width measurement by means of restart• The value for the puls width can be read out directly from CR000 • No further calculations needed

190

8-bit Timer TM5x (78K0S, 78K0)

Operating Modes

• Interval timer− Interrupt request generation at preset time interval

• External event counter− Counting of pulses of an external input signal

• Square wave output− Output of square wave signal with any selected frequency

• PWM output− PWM output with 8-bit resolution is possible− Periode defined by overflow

191


Block Diagram

192


PWM output timing

Note The initial value of TO50 is low at output enable (TOE50=1)

N = 01H to FFh TCE50 = 1

Caution Do not set CR50 to 00H in PWM output mode. Otherwise, PWM may not be output normally.

193

8-bit Timer TMH (78K0S, 78K0)

Operation modes• Interval timer (timer output)• High speed PWM

Features of the TMHx• Selectable clock sources• Low-speed on-chip oscillator can be selected as clock source for TMH1• 2 compare registers• 2 timer output ports

194


Block Diagram

195


Countclock

t

CMP0 value

0

CMP1 value

T0O(TOLEV0=0)

T0O(TOLEV0=1)

value 1 value 2

CMP1 value1CMP1 value2

High-speed PWM mode

196

Timer Array Unit TAU (78K0R)

Timer operation• Eight 16-bit timers per Timer Array Unit

− Each 16-bit Timer is called a channel− Each 16-bit Timer can be used as an independent timer− 16-bit Timers can be used in combination with a second timer

Operation Modes• Independent Operation Mode

− Interval timer− Square wave output− External event counter− Divider function− Input pulse interval measurement− Input signal high-/low level width measurement

197


Operation Modes• Combined Operation Mode

− PWM output− One-shot pulse output− Multiple PWM output

• LIN-bus Supporting Function (channel 7 only) used for− Detection of wakeup signal− Detection of sync break field− Measurement of pulse width of sync field

198


Block Diagram

199


Basic rules for combined operating modes

200


Example for interval timer mode• Generation of timer interrupt INTTM0n at a preset interval• Interrupt interval can be calculated as follows:

tINT = Period of count clock x ( Set value of TDR0n + 1 )

Block Diagram of interval timer mode operation

201


Example for interval timer mode• Basic timing of interval timer mode operation

(1) Start Timer

(2) Status Timeroperation enabled

(3) Load content ofTimer Data RegisterTDR0 to Timer CountRegister TCR0

(4) Timer counts downto 0000H

(5) When Timer Count Register TCR0reaches 0000H, an interrupt will begenerated and the timer output toggles.

202


void TAUInit(void) // TAU initialization for interval timer operation{ // Channel 0 is used.

PER0 |= 0x01; // Power on Timer Array UnitTPS0 = 0x0011; // Select clock frequencies CK00 and CK01

// CK00 = fCLK/2 and CK01 = fCLK/2TMR00 = 0x0000; // CK00 is timer input clock

// Software trigger is used to start count operation// Interval timer mode is selected

TDR00 = 0x7FFF; // Select interval time // tINT = (0x7FFF + 1) * 1 / (fCLK / 2)// tINT = (0x7FFF + 1) * 1 / (20MHz / 2)// tINT = 3.2768 ms

TS0 |= 0x0001; // Start timer count operation}

203


Example for PWM mode• Master channel operates in interval timer mode and counts the period• Slave channel operates in one-count mode and outputs the PWM

waveform• The pulse period and the duty factor can be calculated as follows:

Pulse period = Period of count clock x ( Set value of TDR0nMASTER + 1 )Duty Factor = [ Set value of TDR0mSLAVE / ( Set value of TDR0nMASTER + 1 )] x 100%100% output = Set value of TDR0mSLAVE = 0000H100% output = Set value of TDR0mSLAVE ≥ {Set value of TDR0nMASTER + 1}

204


Block Diagram of PWM mode operation

(1) When channel start trigger TS0n is set to 1

(2)TCR0n counts down from the starting value of TDR0n, INTTM0n is output, which is the trigger for the slave timer and the TO0m output is changed

(3)When TCR0n = 0000H INTTM0n is output again

(4)The TO0m output is changed again(5)TCR0m counts down

from the starting values of TDR0m

(6)When TCR0m = 0000H, INTTM0m is output and TM0m output is changed

205


Example for PWM mode• Basic timing of PWM mode

operation

206

Timer Array Unit TAUS (78K0R/Ix3)

Timer operation• 12 x 16-bit timers

− Each 16-bit Timer is called a channel− Each 16-bit Timer can be used as an independent timer− 16-bit Timers can be used in combination with one or more timers

Operation Modes• Independent Operation Mode

− Interval timer− Square wave output− External event counter− Divider function− Input pulse interval measurement− Input signal high-/low level width measurement

207


Operation Modes• Combined Operation Mode

− PWM output− One-shot pulse output− Multiple PWM output− PWM output with dead-time generation− 6-phase PWM output generation (Triangle)− A/D Trigger on triangle wave

• LIN-bus Supporting Function (channel 7 only) used for− Detection of wakeup signal− Detection of sync break field− Measurement of pulse width of sync field

208


Block Diagram

209


Basic rules for combined operating modes

210

Inverter Control Functions

Operation Modes• Complementary PWM output function

− 6-phase PWM output function (triangular wave modulation, upper arm, lower arm, six outputs)− A waveform of an arbitrary period, the duty, and the dead time

can be generated by using channel 7 of the TAUS in combination.

− Half-bridge output function (two outputs × 2)− A waveform of an arbitrary period, the duty, and the dead time

can be generated by using channel 4 of the TAUS in combination.

− Full-bridge output function (four outputs)− This function uses the above-mentioned half-bridge output.

211


Operation Modes• Non-complementary PWM output function

− 6-phase PWM output function (sawtooth wave modulation or triangular wave modulation, six outputs)− A waveform of an arbitrary frequency, the duty, and one

without dead time can be generated by using channel 7 of the TAUS in combination.

• Interrupt-thinning function− The interrupts of channels 0 and 4 that are used for setting the

period can be thinned.

212


Operation Modes• Arbitrary dead time setting function

• A/D converter start timing setting function (Four types of timings can be generated.)− The A/D converter start timing can be output by using channels 8

and 9 of the TAUS.

• 0% and 100% output can be performed− both with the complementary PWM output function and non-

complementary

• Forward and reverse settings of the timer output can be performed for each pin

213


Operation Modes• Real-time output function (PWM modulation can be performed with this

function)

• Forcible output stop function− The outputs of TO02 to TO07 can be set to high impedance during

detection of the valid edge by the internal comparator or by an external pin input (TMOFF0).

214


Major Features• 180 degrees sinusoidal wave generation

− 0%, 100% duty for Space Vector Modulation

• 120 degrees sinusoidal wave generation− Complementary PWM for brake torque

generation− PWM forward/backward chopping with

any timing

• 6-step block control wave generation− BLDC motors

AC InductionPMAC

BLDCSR

Universal DC

78K0R/Ix3

215

Comparators/Operational Amplifiers

Comparator Operation• The output signal of an operational amplifier can be used as the

positive-side input signal of a comparator

• An interrupt request is generated when an overvoltage is detected (INTCMP0 and INTCMP1)

• The output signal of a comparator is connected to the timer array unit and sets the timer output pin (TOn) to a Hi-Z state

216


Operational Amplifiers Operation• An operational amplifier amplifies and outputs an analog voltage that is

input.− Eight amplification factors can be selected

• The output signal of an operational amplifier can be used as thepositive-side input signal of a comparator. (In this case, the output signal is simultaneously input to both channels of comparators 0 and 1)

• The output signal of an operational amplifier can be selected as the analog input of an A/D converter

217


Over-voltage Detection Function• The timer output pin (TOn) can be set to a Hi-Z state while an overcurrent flows

by using an operational amplifier and a comparator.

• A function to set the pin to a Hi-Z state can be selected from the following two functions− 2-stage over-current detection function

− Reference voltage of comparator 0 < input signal voltage < reference voltage of comparator 1 → Sets the TOn pin to a Hi-Z state

− Reference voltage of comparator 1 < input signal voltage → Sets the TOn pin to a Hi-Z state.

− Over-current/electromotive force detection function− Input signal voltage (electromotive force) < comparator 0, or

comparator 1 < input signal voltage overcurrent) → Sets the TOn pin to a Hi-Z state.

218


Block Diagram of Operational Amplifier (for 78K0/Kx2-L)• Two Operational Amplifier channels• One Prog. Gain amplifier channel

=> For A/D Converter

219


Block Diagram of Comparator and Programmable Gain Amplifier (for 78K0R)

220

Real-Time Counter

Operation Modes• Counting year, month, week, day, hour, minute and second

− Counts up to 99 years

• Constant period interrupt function− Period: 1 month to 0.5 seconds

• Alarm interrupt function− Alarm: week, hour, minute

• Interval interrupt function• Pin output function

− 1Hz− 512 Hz− 16.384 kHz− 32kHz

221

Real-Time Counter

Block Diagram

222

Real-Time Counter

Basic operation• Sub-count Register (RSUBC)

− Counts reference time of 1 second− 0000H…7FFFH corresponding to 1 second @ 32.768 kHz− If RSUBC reaches 8000H, the second count register (SEC) will be

incremented by 1

Watch Error Correction• Watch Error Correction Register (SUBCUD)

− Correction of the count value of the Sub-count register (RSUBC)− Improves the accuracy of the real-time counter due to inaccuracy of

the subclock

223

Example for Watch Error Correction• fSUB = 32.768 kHz:

− ( 1 / fSUB ) x 8000H = ( 1 / 32.768 kHz ) x 32768 clks = 1 sec

• fSUB = 32.780 kHz:− ( 1 / fSUB ) x 8000H = ( 1 / 32.780 kHz ) x 32768 clks = 0.9996 sec

− Δclocks = ( fCLK / 32.768 kHz – 1 ) x 32768 clks = 12 clks − Δclocks = [(F5...F0) - 1] * 2− (F5...F0) = Δclocks / 2 + 1 = 12 / 2 + 1 = 7 => SUBCUD = 10000111b = 87H

Real-Time Counter

( 1 / 32.780 kHz ) x ( 32768 + 12) clks = 1 sec

224

Watchdog Timer (78K0S)

Function• Detection of an inadvertent program loop (runaway)• RESET generation

Watchdog Timer mode Register (WDTM)• Enable/Disable Window Watchdog Timer operation• Select clock source• Select overflow time

Watchdog Timer Enable Register (WDTE)• Writing ACH to WDTE clears the watchdog timer and starts counting

again

Option byte• Select, if low-speed on-chip oscillator can be stopped by software or

not

225


Block Diagram

226

Counting starts

WDT operation Count Clock

Ring-OSC

Interval time

Max. time

Time set by WDTM

RESET is released

Set WDTM (Interval time change)

Counter is cleared, if “ACH” iswritten to WDTE. Cannot be stopped Cannot be changed Cannot be changed


Operation• Ring-OSC cannot be stopped

The watchdog timer triggers a hard reset,if the watchdog timer counter overflowsIf WDTM register is written a second timeif a wrong value is written into WDTEif the WDTE register is accessed by a 1-bit manipulation instruction


227

Counting starts

WDT operation Count Clock

Ring-OSC

Ring-OSC fXP STOP

Interval time

Max. time

Time set by WDTM

RESET is released

Set WDTM (Int. time/Source clock change)

Counter is cleared, if “ACH” iswritten to WDTE. Cannot be stopped Cannot be changed Cannot be changed


Operation• Ring-OSC can be stopped



228


Function• Detection of an inadvertent program loop (runaway)• RESET generation

Watchdog functionality is set by option byte• Watchdog timer interval interrupt (K0R only)• Enable/Disable Window Watchdog Timer operation• Select overflow time• Select window size• Window Watchdog timer operation in HALT/STOP mode

Watchdog Timer Enable Register (WDTE)• Writing ACH to WDTE clears the watchdog timer and starts counting

again

229


Block Diagram

230


100%

75%

50%

25%

clos

ed

Writing of magic word into WDTE reset register

Tota

l W

indow

Siz

e

RESET!

Ove

r-flow

*: example shown for50% window opening

(0%)

open

*

The watchdog timer triggers a hard reset,if the watchdog timer counter overflows

if, the magic word is written into WDTE register when window is closed

if a wrong value is written into WDTE

if the WDTE register is accessed by a 1-bit manipulation instruction

The watchdog timer triggers a hard reset,if the watchdog timer counter overflows

if, the magic word is written into WDTE register when window is closed

if a wrong value is written into WDTE

if the WDTE register is accessed by a 1-bit manipulation instruction

231

Option Byte (78K0S)

Option byte area• Address 0080H

− User option byte area 0080H− 0080H:

− Selection of system clock source− Enable/Disable internal on-chip low-speed oscillator can be

stopped by software− Control of RESET pin− Oscillation stabilization time on power application or after

reset release

232

Option Byte (78K0)

Option byte area• Address range 0080H to 0084H

− User option byte area 0080H to 0083H− 0080H:

− Enable/Disable watchdog timer operation− Enable/Disable watchdog timer operation in HALT/STOP mode− Interval time setting− Select window time− Enable/Disable internal on-chip low-speed oscillator can be stopped by

software− 0081H:

− Enable/Disable LVI operation at start-up− 0082H:

− Reserved area, set to 0x00− 0083H:

− Reserved area, set to 0x00

− On-chip debug option byte 0084H− 0084H:

− Enable/Disable on-chip debug function− Flash memory handling in case of failure in on-chip debug security ID

authentication-

233

Option byte setting

#pragma constseg = OPTBYTE

__root const unsigned char option_u08 [] = {0x6E,0x01,0x00,0x00};

#pragma constseg = default

Set the four option bytevalues

Force the compiler to set this constant evenif not used from code

Switch to segmentOPTBYTE

Possible chip operation

234

Option Byte (78K0R/Kx3)

Option byte area• Address range 000C0H to 000C3H

− User option byte area 000C0H to 000C2H− 000C0H:

− Enable/Disable watchdog timer operation− Enable/Disable watchdog timer operation in HALT/STOP mode− Interval time setting− Select window time− Use of watchdog timer interval interrupt

− 000C1H:− Enable/Disable LVI operation at start-up

− 000C2H:− Reserved area, set to 0xFF

− On-chip debug option byte 000C3H− 000C3H:

− Enable/Disable on-chip debug function− Flash memory handling in case of failure in on-chip debug security ID

authentication

235

Option Byte (78K0R/Kx3)

#pragma constseg = OPTBYTE__root const char option[4] = {

0x10, // 00010000// ||||||||// |||||||+-- Watchdog timer operation stopped// ||||||| in HALT/STOP mode// ||||+++--- Watchdog timer overflow time is// |||| 2^10 / fIL = 3.88ms @ fIL = 264kHz(Max.)// |||+------ Watchdog timer operation disabled// |++------- 25% window open period// +--------- Interval interrupt is not used

0xFF, // 11111111// |// +-- LVI off

0xFF, // !!!!! ALWAYS SET TO 0xFF !!!!!0x85 // 10000101

// | | |// | | +-- Does not erase flash memory// | | in case of wrong security ID// | | authentication// | +---- Must be set to 1// +--------- Enable on-chip debug operation

};#pragma constseg = default

236

A/D Converter

Operating Mode• 10-bit A/D Conversion

− Channel selection from 4 to 16 channels− Each time an A/D conversion operation ends, an interrupt request (INTAD)

is generated− The minimum conversion time becomes 4µs (78K0S) , 6.6us (78K0, 78K0R) − Unused A/D Inputs can be set as I/O ports

Note: Current consumption will increase about 1 mA, when A/D conversion operation is enabled.

237

A/D Converter (78K0, 78K0R)

Block Diagram

238

A/D Converter (78K0R)

void ADInit(void){

PER0_bit.no5 = 1; // Switch on A/D Converter input clockADCE = 1; // Start A/D Converter comparator operation (ADCE-bit of ADM register)ADPC = 0x0F; // P15_bit.no7 is used as analog input

PM15_bit.no7 = 1; // P15_bit.no7 is set to input

ADM &= 0x01; // ADCE-bit of ADM register (ADM_bit.no0)is already set and must remain setADM |= 0x10; // A/D Conversion time is 6.6µs@AVREF0=4.0...5.5VADS = 0x0F; // P15_bit.no7 is used as analog input = ANI15

}

void ADStart(void){

ADPR0 = 1; // Select A/D Converter interrupt default priorityADPR1 = 1;ADIF = 0; // Clear A/D Converter interrupt request flagADMK = 0; // Unmask A/D Converter interruptADCS = 1; // Start A/D Converter operation (ADCS-bit of ADM register)

}

// #pragma bank = 0 (optional)#pragma vector = INTAD_vect__interrupt void IsrAD(void){

ADResult = ADCR; // Read conversion result// Store conversion result as value

ADResult = (ADResult >> 6) & 0x03FF;}

239

D/A Converter (78K0R)

Operating Mode• 8-bit D/A Conversion

− 2 channels can be selected− R-2R ladder method− The minimum conversion time becomes 3 µs − Unused A/D Inputs can be set as I/O ports

− UANO = AVREF1 x ( m / 256 )

• Normal Mode− Write operation to the DACSn register triggers the D/A Conversion− Previous D/A conversion result is held until the next D/A conversion is

performed

• Real-time Output Mode− Interrupt request signals (INTTM04 and INTTM05) triggers the D/A

Conversion− Value set in the DACSn register is output every time the INTTM04 and

INTTM05 signals are generated

240

D/A Converter (78K0R)

Block Diagram

241

Analog Block Diagram (78K0R/Lx3 only)

AMP0+/ANI2

AMP0-/ANI0

:Control by register

AMP0O/ANI1

AMP1+/ANI5

AMP1-/ANI3

AMP1O/ANI4

AMP2+/ANI8

AMP2-/ANI6

AMP2O/ANI7

AVDD1

ANO1

-+AMP

AVSS

(2.0V)or

(2.5V)

ADREFP

ADREFM

AVDD0

-+AMP0

AVDD0

AVSS0

AVSS1

AVDD1

ANO0

-+AMP

AVSS1

AVDD1

AVSS0

AVDD0

AVDD0

AVSS0

Analog In

ANI9-10

AVREFM/ANI15

AVREFP/VREFOUT

AVDD1

AVDD1

AVSS

-+AMP1

AVDD0

AVSS0

-+AMP2

AVDD0

AVSS0

AVDD0 AVDD1

AVSS0, AVSS1

OPAMP0

OPAMP1

OPAMP2

Voltage Reference

12bit DAC

12bit DAC

12bit ADC

ＡＤＲＥＦ

ＤＡＲＥＦ

ＤＡＲＥＦ

ＶＲＧＶＶＲＯＮ

ＯＡＥＮ０

ＯＡＥＮ１

ＯＡＥＮ２

ＡＤＳ

AVREFM

DAREFP

DAREFP

OAENx disables the Op. Amp., not just the output.

242

Multiplier (78K0S)

Operation Mode • Multiplication of 8 bits × 8 bits = 16 bits• Multiplication result is available after 16 CPU clocks

243

Multiplier (78K0)

Operating Modes• Available on all 78K0/Kx2, Lx2 with >= 48K and for all 78K0/Fx2

products• Multiplication of 16 bits × 16 bits = 32 bits• Division of 32 bits / 16 bits = 32 bits and 16-bit remainder• Multiplication result is available after 16 CPU clocks• Division result is available after 32 CPU clocks• An interrupt can be generated

Remark:8 x 8 bit Multiplication and 16 / 8 bit Division are part of the instruction set

244

Multiplier/Divider (78K0)

Block Diagram

245

Multiplier (78K0R)

Operation Mode• Multiplication of 16 bits × 16 bits = 32 bits• Multiplication result is available after 1 CPU clock

Remark:8 x 8 bit = 16 bit Multiplication is part of the instruction set (1 CPU clock)

MOVW MULA, #1234HMOVW MULB, #5678HNOP ; 1 clock wait. Doesn’t have to be NOPMOVW AX, MULOH ; The result obtained on upper sidePUSH AXMOVW AX, MULOL ; The result obtained on lower side

246

Multiplier (78K0R)

For use of the Multiplier instead of library software multiplication functions add the following lines to the *.XCL file:

-eNewFktName=LibFktName

e.g. –eHW_I_MUL_L02=?I_MUL_L02-eHW_L_MUL_L03=?L_MUL_L03

Add the lines above to the extra options of the linker options:• Select the project folder icon

projectname - Debug in the workspace window and choose Project>Options.

• Select Linker in the• Category list to display • the XLINK option pages• Then select the Extra Options.

247

Multiplier (78K0R)

Block Diagram

248

Multiplier/Divider (78K0R except 78K0R/Kx3)

Operation Mode• Multiplication of 16 bits × 16 bits = 32 bits• Multiplication result is available after 1 CPU clock

Remark:8 x 8 bit = 16 bit Multiplication is part of the instruction set (1 CPU clock)

• Division of 32 bits / 32 bits = 32 bits, 32 bits remainder• Division result is available after 16 CPU clocks

249

Multiplier/Divider (78K0R except 78K0R/Kx3)

Block Diagram

250

Serial Interface CSI (78K0)

Operating Modes• Operation stop mode

− This mode is used when serial transfer is not performed− Reduces power consumption

• 3-wire serial I/O mode (MSB/LSB first selectable)− 8-bit data transfer mode using three lines: a serial clock line

(SCK1n), a serial output line (SO1n), and a serial input line (SI1n)− The first bit of the serial transfer 8-bit data can be selected as the

MSB or LSB− The serial clock and the data phase/polarity can be selected− The 3-wire serial I/O mode is useful for connection to devices such

as peripheral I/O and display controllers which incorporate a clocked serial interface

251

Serial Interface CSI (78K0)

Block Diagram

252

Serial Interface UART6 (78K0S, 78K0)

Operating Modes• Operation stop mode

− This mode is used when serial transfer is not performed to reduce power consumption

• Asynchronous serial interface (UART) mode− Full-duplex operation is possible− A UART-dedicated baud rate generator is incorporated, allowing

communication over a wide range of baud rates− Full buffered UART for continuous transmission / reception− Three interrupts provided (Receive, Transmit, Error)− Three error flags (Framing, Parity, Overrun)

• Asynchronous serial interface (UART) mode with LIN bus support− Synchronous break field transmission from 13 to 20 bits− More than 11 bits can be identified for synchronous break field

reception

253


UART6

Ext. INT

16 bit capture

RxD6

78K0/Kx

Wake-UpSignalFrame

SynchBreakField

SynchField

IdentField

DATAField

DATAField

CheckSUMField

SleepBus

Message Header Message Response

ISC

ISC

TI000

INTP0

LIN support by UART6• Baud rate calibration

− 16 bit timer to measure the sync-field − Fine tunable baud rate generator to fit master baud rate even with

RC or internal oscillator

• Wake-up with startup-frame− External Interrupt

254


Block Diagram

255

Serial Array Unit (78K0R)

Two Serial Array Units availableFour serial channels per Serial Array Unit availableTwo or more of various serial interfaces (3-wire serial (CSI), UART, and simplified IIC) can be used in combination

256


Operation Modes• 3-wire serial I/O

− Data transmission/reception− Data length of 7 or 8 bits− Phase control of transmit/receive data− MSB/LSB first selectable− Level setting of transmit/receive data

− Clock control− Master/slave selection− Phase control of I/O clock− Setting of transfer period by prescaler and internal counter of each

channel

− Interrupt function− Transfer end interrupt/buffer empty interrupt

− Error detection flag− Overrun error

257


Operation Modes• UART

− Full-duplex UART communication can be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel)

− Data transmission/reception− Data length of 5, 7, or 8 bits− Select the MSB/LSB first− Level setting of transmit/receive data and select of reverse− Parity bit appending and parity check functions− Stop bit appending

− Interrupt function− Transfer end interrupt/buffer empty interrupt− Error interrupt in case of framing error, parity error, or overrun

error

258


Operation Modes• UART

− Error detection flag− Framing error, parity error, or overrun error

− LIN-bus functions UART3 (ch-2 and ch-3 of unit 1 only)− Wakeup signal detection− Sync break field (SBF) External interrupt (INTP0) or

detection timer array unit (TAU) is used− Sync field measurement for

baud rate calculation

259


Operation Modes• Simplified I2C

− Designed for single communication with a device such as EEPROM, flash memory, or A/D converter− Master mode only− No wait state detection

− Data transmission/reception− Master transmission, master reception (only master function

with a single master)− ACK output and ACK detection functions− Data length of 8 bits (When an address is transmitted, the

address is specified by the higher 7 bits, and the least significant bit is used for R/W control.)

− Manual generation of start condition and stop condition

260


Operation Modes• Simplified I2C

− Interrupt function− Transfer end interrupt

− Error detection flag− Parity error (ACK error)

* Functions not supported by simplified I2C• Slave transmission, slave reception• Arbitration loss detection function• Wait detection functions

261


Block Diagram

262


void UART3Init(void){

PER0_bit.no3 = 1; // Switch on serial arry unit 1 input clock// If fCLK = Internal high-speed osc. clock (20MHz (max.)

SPS1 = 0x0044; // fCK10 and fCK11 = fCLK/2^4 = 20MHz (max.) / 16 =1.25MHz

SMR12 = 0x0022;SMR13 = 0x0122;

// Setting Serial Array Unit 1 channel 2 and 3(UART3):// Transmit and Receive Mode only mode, // Baud rate: 9600 Bd @ fCLK=20MHz, // Data bits: 8,// Parity: No,

SCR12 = 0x8097; // Stop bits: 1,SCR13 = 0x4097; // Transmit LSB first

// SDR[15...9] = INT[1/2 * ( fCLK/(2^SPS[3...0] * Baud rate) - 1 )] * 2// SDR[15...9] = INT[1/2 * ( 20MHz/(2^4 * 9600Bd) - 1)] * 2// SDR[15...9] = INT[1/2 * ( 20MHz/153600Bd - 1)] * 2// SDR[15...9] = INT[1/2 * ( 130.2MHz/Bd - 1)] * 2

SDR12 = 0x8000; // SDR[15...9] = INT[64.6] * 2 = 64 * 2SDR13 = 0x8000; // SDR[15...9] = 128 = 0x80

.

. // continue next page

.

263


SOL1 = 0x0000; // Communication data is output as is.SO1 = 0x0004; // Serial data output of channel 0 and 2 is 1SOE1 = 0x0004; // Enables output by serial communication operation.

STIF3 = 0; // Clear SAU1 ch-2 UART transmit interrupt request flag// (Transmit path of UART3)

SRIF3 = 0; // Clear SAU1 ch-3 UART receive interrupt request flag// (Receive path of UART3)

SREIF3 = 0; // Clear SAU1 ch-3 UART receive error interrupt request flag// (Receive path of UART3 not used)

STMK3 = 0; // Unmask SAU1 ch-2 UART transmit interrupt// (Transmit path of UART3)

SRMK3 = 0; // Unmask SAU1 ch-3 UART receive interrupt// (Receive path of UART3)

SREMK3 = 0; // Mask SAU1 ch-3 UART receive error interrupt// (Receive path of UART3)

STPR03 = 1; // Default priority for SAU1 ch-2 UART transmit interruptSTPR13 = 1; // (Transmit path of UART3 not used)SRPR03 = 1; // Default priority for SAU1 ch-3 UART receive interruptSRPR13 = 1; // (Receive path of UART3)SREPR03 = 1; // Default priority for UART receive error interruptSREPR13 = 1; // (Receive path of UART3)

PM1_bit.no3 = 0; // Set port bit direction of TxD3 to outputPM1_bit.no4 = 1; // Set port bit direction of RxD3 to inputP1_bit.no3 = 1; // Set port latch of TxD3 to 0

SS1 = 0x000C; // Start Serial Array Unit 1 channel 2 and 3 operation}

264


void SendByte(unsigned char TxByte_u08)// Transmit one byte{

STIF3 = 0; // Clear Uart3 transmit interrupt requestSTMK3 = 0; // Enable Uart3 transmit interrupt request

SDR12 = TxByte_u08; // Send byte}

#pragma bank = 0 (optional)#pragma vector = INTST3_vect__interrupt void IsrUart3Tx(void) // UART3 transmission interrupt service{

STMK3 = 0; // Enable Uart3 transmit interrupt requestEfsm1_Active_u01 = 1; // Inform state machine Efsm1

}

#pragma bank = 0 (optional)#pragma vector = INTSR3_vect__interrupt void IsrUart3Rx(void) // UART3 reception interrupt service{

RxByte_u08 = (unsigned char)SDR13; // copy (overwrite) received byte into bufferif (!TxBusy_u01)

Efsm0_Active_u01 = 1; // Inform state machine Efsm0}

265

I2C Interface

Operation Modes• Operation stop mode

− No serial transfers performed− Used to reduce power consumption

• I2C bus mode − Supports Multi-master mode− Compliant to I2C-bus specification− Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0

requires pull-up resistors for the serial clock line and the serial data bus line.

266

I2C Interface

Block Diagram

267

I2C Interface

Since the SCL0 and SDA0 pins are open drain outputs, IIC0 requires pull-up resistors for the serial clock line and the serial data bus line

268

Interrupt Functions

Fast interrupt service handlingInterrupt function can be controlled by• Interrupt Mask Flag Registers MKx• Interrupt Request Flag Register IFx

− Can be set / cleared by software− polling or vector service routine

• Interrupt Priority Register PRx

Each source has its own set of flagsStandby release possible by each source

269

Fast interrupt service handling

• 78K0S:

• 78K0:

• 78K0R:

Interrupt Functions

9

270

Interrupt Functions (78K0S)

Basic Interrupt Configuration

• Internal maskable interrupt

• External maskable interrupt

271

Interrupt Functions (78K0)




• Software interrupt

272

Interrupt Functions (78K0R)




• Software interrupt

273

Interrupt Functions (78K0S)

Interrupt Processing and Multiple Interrupt Processing

• Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged, because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction.

• During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment.

274

Interrupt Functions (78K0)

Interrupt Processing and Multiple Interrupt Processing

• Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged, because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction.

• During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment.

275

Key Interrupt Function (78K0, 78K0R)

Operation Mode• One port can be used as Key-Return port• Falling edge detection• Easy keyboard realization• Standby release

276

Key return example

V DD

KR0

KR1

KR2

KR3

V DD

P10

P11

P12

P13

> 1

H

µPD78F0533V DD

off

on

off

on

V DD

KR0

KR1

KR2

KR3

V DD

V DD

P10

P11

P12

P13

> 1INTKR

L

off

on

µPD78F0533

off

on

277

LCD Controller / Driver (78K0/78K0R)

Features

• Display data is read by DMA operation, segment and common signals are generated automatically.

• From static up to 8 times division mode.• Frame frequencies can be adapted to each glass type.• Up to 400 segments (for 78K0R/Lx3) can be driven.• LCD controller operates based on subsystem clock, even in HALT mode.• Different ways to generate LCD voltages

− Resistor ladder type (Internal / External)− Booster type (only for 78K0/Lx2 & 78K0R/Lx3)

278


LCD voltage level drive with external resistors (resistor ladder type)

Static mode ½ bias mode ⅓ bias mode

279


LCD voltage level drive with charge pump (booster)

• External capacitors are used to generate LCD voltage

• Advantage: Stable display contrast quality against supply voltage

• LCD voltage is independent from Vdd

• Recommended Capacitors: 4 * 0.47µF

• Small LCD can use smaller capacitors at VLCx

280


LCD glass panel

S

1S

2S

3

S

4S

5S

6S

7

S

8S

9S 1

0S 1

1

S 1

2S 1

3S 1

4S 1

5

S 1

6S 1

7S 1

8S 1

9

S 2

0S 2

1S 2

2S 2

3

S 2

4S 2

5S 2

6S 2

7

S

0

Timing

CO

M 0

CO

M 1

CO

M 2

CO

M 3

Open

Open

Data memory address

00110000xxxxxxxx

00111110xxxxxxxx

01110010xxxxxxxx

01011110xxxxxxxx

11011111xxxxxxxx

01110100xxxxxxxx

11111110xxxxxxxx

00 H

01 H

02 H

03 H

04 H

05 H

06 H

07 H

08 H

09 H

0A H

0B H

0C H

0D H

0E H

0F H

10 H

11 H

12 H

13 H

14 H

15 H

16 H

17 H

18 H

19 H

1A H

1B H

Bit 0Bit 1Bit 2Bit 3

281

S n

S n

+ 1

S n

+ 2

S n

+ 3

CO

M 0

CO

M 1

V ss

V ss

COM 0 V DD

1/2 V DD

T F

S nV DD

1/2 V DD

COM 1

V ss

V DD

1/2 V DD

V DD

1/2 V DD

V DD

1/2 V DD

- V DD

- V DD

COM 1 - S nsegment on 0 V

+ V DD

+ 1/2 V DD

- 1/2 V DD

COM 0 - S n

0 V

+ V DD

+ 1/2 V DD

- 1/2 V DD

segment off

LCD duplex mode, segment connection and timing


Division by two, LCD drive waveform example ( 1 / 2 bias )

282

Software LCD solution

LCD-C/D SW emulation running on 78K and V850ES Running 100% in background with min. CPU load (less than 2%)Display memory mapped into internal RAMFlexible access from the application point of viewNo DC offset and excellent display quality

283

uPD78xxxx

8 8

4

Segment Lines

Common Lines4 tri-state ports

out port

out port

Software LCD solution

Example without additional hardware• Glass: 5V, 64 Hz, 1/2 Bias, 4 commons, 64 segments

284

DMA Controller

Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without CPU load

Functions• Number of DMA channels: 2• Transfer unit: 8 or 16 bits• Maximum transfer unit: 1024 times• Transfer type: 2-cycle transfer (One transfer is processed in 2 clocks and the

CPU stops during that processing)• Transfer mode: Single-transfer mode• Transfer request: Selectable from the following peripheral hardware interrupts

− A/D converter− Serial interface (CIS00, CSI01, CSI10, UART0, UART1, UART3, or IIC10)− Timer (channel 0, 1, 4, or 5)

285

External Bus Interface (78K0R/Kx3)

The external bus interface function is used to connect an external device to an area other than the internal ROM, RAM, and SFR areas

Functions• The number of address bits can be selected from 8, 12, 16, and 20• Data bus supporting 8 bits and 16 bits• Multiplexed bus and separate bus are supported

286


Example• Connection of external logic (e.g. ASIC, etc.)

287


Example• Connection of synchronous memory

288


Example• Connection of asynchronous memory

289

11. Flash Technology

Parameters and SecurityOn-board Programming

Self-ProgrammingEEPROM Emulation

290

Parameters – Process Density Roadmap

Process Density [μm](Gate length)

0,04

0,1

1,0

2,0

0,2

0,30,4

0,60,8

0,060,08

Core Voltages 3.3V

0.35(0.35)

2.5V

1.5V

0.15(0.13)

1.2V

0.13(0.095)

1.0V

0.095(0.065)

5.0V

Densityequiv.to UC1(0.54)

2.5V

Densityequiv.

to UX4(0.25)

5.0V

(0.54)

CZ6H UC1 UC2 UX4 UX5 UX6MF2CZ6

0.25(0.24)

Process used by V850 core types

Process used by 78K core types

Process used by VR core types

291

Parameters – Technology Overview

CZ6HSF for 78K0S

• Single voltage Self-Programming• Supply voltage: 2.0V ~ 5.5V

− Prog. 2.7V ~ 5.5V• 0.35µm process density• Ta(prog): -40°C ~ +105°C• Ta(read): -40°C ~ +125°C• Max. 10 MHz Operation speed• 256 bytes block size• 1byte write unit

Security

• Chip erase protection• Write protection flag• Block erase protection flag• Block protection

292

Parameters – Technology Overview

MF2 – Technology for 78K0 / 78K0R• Single voltage Self-Programming• Supply voltage: 1.8V ~ 5.5V

− Prog. 2.7V ~ 5.5V (78K0R/Ix3/Kx3/Fx3)− Prog. 1.8V ~ 5.5V (78K0R/Kx3-L)

• 0.15µm process density• TA, prog: -40°C ~ +85°C• TA, read: -40°C ~ +85°C• Max. 20MHz Operation speed• Block size

− 1K blocks (78K0R/Ix3/Kx3-L/Fx3)− 2K blocks (78K0R/Kx3)

• 4 byte write unit

293

Parameters – Security Features

Chip erase protection flag• Disable the chip erase command

Write protection flag• Disables the external write command

Block erase protection flag• Single blocks cannot be erased anymore• Chip erase still possible

Secu

rity

leve

l

low

high

294

Parameters – Security Features

All flags set• No on-board programming possible anymore• Only Self-Programming possible

Boot cluster protection flag• Boot cluster 0 cannot be erased or written anymore

Protection Flags are stored in the extra area• Not part of the normal CPU address space

Flash shield window function support• Self-Programming mode only

295

Development Tools – Flash Programmer

Full support of programming on• dedicated programming adapter or • directly in the user system

USB

Target Application Hardware

UART

x.xV

Flash-Programming Adapter

Power supplyis required for programming via UART

USB

MINICUBE2

Level Shifter

Stand alone

PG-FP5-EE

296

On-board Programming – Interface (78K0S)

VddVssRESET

X2/P122

X1/P121

Programming with dedicated programmer (on-board programming)

• Special single wire UART (78K0S/Kx1+ only)− 8 MHz from programmer is used− Fixed baud rate (115200baud)

297

Programming with dedicated programmer (on-board programming)

• CSI Communication (78K0)− internal 8MHz ring oscillator is used

• UART communication (78K0)− External oscillator or programmer clock is used

On-board Programming – Interface (78K0)

298

On-board Programming – Interface (78K0R)

Programming with dedicated programmer • TOOL0 Communication Interface

− Internal “high speed” on-chip oscillator is used

299

Self-Programming – General

Ability to reprogram the flash contents without a dedicated external programming tool => Self-Programming is performed by the application

All single voltage flash devices will support Self-Programming

User defined programming interface• Interface type (I.e. CAN, LIN, CSI, UART, other)

NEC supports Self-Programming by providing appropriate libraries• Free of charge available

Block swapping is supported for secure Self-Programming• Even if the boot loader has to be updated, it is ensured, that always a valid boot

loader (two boot blocks) is available during Self-Programming

Programming an “erased” device must be done with a dedicated external programmer• Contains at least Self-Programming functionality

300

Secure Self-Programming – Bootloader

• The device is never rendered useless – even if a failure occurs during writing the new boot block!

• If the boot block should not be updated the “Boot cluster protection flag” can be used to secure the Boot cluster 0 against erasing or writing

301

Self-Programming – Hardware Security

Self-Programming requires software control of the FLMD0 pin• FLMD0 = LOW during normal operation• FLMD0 = HIGH during Self-Programming

Caution:Please be sure to set FLMD0 to low level in reset state.

RD = 20 kΩ (typ.)

VDD VSS

302

Self-Programming – Software Environment

General functionality and data exchange flow

• Normal mode− Execution of user application− After RESET operation starts

in this mode

• Self-Programming Mode A1− Used to set up Self-Programming− During this mode the firmware can be

called

• Self-Programming mode A2− Firmware commands are executed− Not visible for the user

303

EEPROM Emulation – General

EEPROM emulation is the ability to use a part of the Flash as a kind of EEPROM memory

The requirements are different, depending on number and type of variables to be stored

Main difference to a real EEPROM is the ability to erase only a complete block

Special algorithm to handle the data sets is required• NEC supports EEPROM Emulation by providing an EEPROM emulation library free

of charge

304

EEPROM Emulation - Calculation

How to calculate the possible write erase cycles

We have to distinguish between write and erase cycles

Example for 78F9222 from the 78K0S Family

• Typ. 1000 erase cycles• Min. write unit 1 byte• Only one data set of 4 bytes should be written

• One data set (4 bytes) can be written 64 times until the block is full and must be erased• This erase can be done 1000 times• To secure the data during erase a second block must be used• Finally we reach 64 x 1000 x 2 = 128000 write cycles for a data set of 4 byte

305

12. The 78K Development Tools

Rich Development Environment

306

Overview (78K0S, 78K0)

QB-78K0SKX1-ZZZ-EE

In-Circuit Emulator for all 78K0S/Kx1+ devices

QB-78K0KX2-ZZZ-EE QB-78K0LX2-ZZZ-EE

In-Circuit Emulators for all 78K0 devices

EW78K-FULL-EE

Compiler, Assembler, Linker, C-Spy Debugger

ID78K0-QB

IntegratedDebugger

AP-78K0SKX1-EE AP-78K0KX2-EE AP-78K0LX2

Device Driver Configurator PG-FP5-EE

Flash Programmer for all NEC single-voltage flash devices

QB-MINI2-EE

On-Chip Debug Emulator for all 78K0S, 78K0 and 78K0R devices

Low-Cost Programmer

307

Hardware Tools (78K0)

78K0LX3-SEEIT

78K0/Lx3 See it! Starter Kit

QB-78K0SKB1-TBQB-78K0KF2-TBQB-78K0KC2L-TBQB-78K0LG2-TBQB-78K0LF3-TB

Target Board

78K0–SAVEIT

78K0/Kx2-L Save it! Starter Kit

78K0-USB

78K0/USB Starter Kit

LPC-DOIT

Low Pin Count 78K0S/Kx1+ Do it! Starter Kit

308

Overview (78K0R)

EW78K-FULL-EE

Compiler, Assembler, Linker, C-Spy Debugger

ID78K0R-QB

IntegratedDebugger

QB-MINI2-EE

On-Chip Debug Emulator for all 78K0S, 78K0 and 78K0R devices

Low-Cost Programmer

QB-78K0RKX3-ZZZ-EE

QB-78K0RIX3-ZZZ-EEQB-78K0RLX3-ZZZ-EE

In-Circuit Emulator

PG-FP5-EE

Flash Programmer for all NEC single-voltage flash devices

AP-78K0RKX3-EE

Device DriverConfigurator

UNDERDEVELOPMENT

309

Hardware Tools (78K0R)

QB-78K0RKG3-TBQB-78K0RKE3L-TBQB-78K0RIE3-TB

Target Board

78K0R–SAVEIT

78K0R/Kx3-L Save it! Starter Kit

78K0RLX3–SENSEIT

78K0R/Lx3 Sense it! Starter Kit

78K0R-SAYIT

78K0R/Kx3 Say it!

Starter Kit for Voice Synthesis

78K0R-COOLIT

78K0R/Kx3 Cool it! Starter Kit

78K0RIX3-SPINIT

78K0R/Ix3 Starter Kitfor Motor Control

310

Performance (78K0R)

78K0R – Spin it!

78K0R/Ix3 Starter Kit for Motor Control

UNDERDEVELOPMENT

78K0R – Cool it!

78K0R/Kx3 Starter Kit

Pric

e Pe

rfor

man

ce

QB-78K0RKX3-ZZZ-EE

QB-78K0RIX3-ZZZ-EEQB-78K0RLX3-ZZZ-EEIn-Circuit Emulator

PG-FP5-EE

Flash Programmer

78K0R – Say it!

78K0R/Kx3 Starter Kitfor Voice Synthesis

QB-MINI2-EE

On-Chip Debug Mode

QB-MINI2-EE

Programming Mode

78K0R – Save it!

78K0R/Kx3-L Starter Kit

78K0R – Cool it!

78K0R/Lx3 Starter Kit

311

Target Board

Features• Flash programming via On-Chip Debug Connector for MINICUBE2• Universal “Patch” area

− Allows simple interface circuitry to be added

• All pins of the microcontroller are available− Allows use as daughter board for initial product evaluation or

development

• Main clock− Full speed resonator (i.e. 78K0)− Max. input (resonator)

(i.e. V850 with PLL)

• Power supply LED (red)• User function LEDs (2 x yellow)• User switch

CN2

CN1

16-pin connector

Test LEDsLED2LED1Universal

area

VSS and VDD pins

Test switch

Power LED

Main clock

QB-78K0RKG3-TB

312

Target Board

Possible Uses• Designed as a MINICUBE diagnostic tool

− Test PC installation and Driver − Test USB interface− Test MINICUBE2 functions

• Simple evaluation board for 78K and V850ES devices− Download, Run and Evaluation of sample programs

• Daughter board− Connection to target system through CN1 and CN2 connectors

• Reference design (Hardware and Schematic)− Basic CPU configuration− Basic external functions, such as RESET, OCD/Programming interface,

Crystal

313

IAR Embedded Workbench

ICC78K/ICC78K0RC/EC++ Compiler

A78K/A78K0RAssembler

XLINKLinker

C-SPY Simulator

C-SPY DebuggerQB-78K0Sxxx-ZZZ-EEQB-78K0xxx-ZZZ-EEQB-78K0Rxxx-ZZZ-EE

C-SPY DebuggerQB-78K0MINI-EE

QB-MINI-EE

C-SPY DebuggerIE-78K0S-NS-AIE78K0-NS-A

Other 3rd Party Debugger

i.e. NEC Debugger...

314


General Features• One version with GUI and DOS Interface

− DOS interface: useful for various projectmanagement tools

− Win interface: compiler, assembler, linker, simulatorand debugger included in the Embedded Workbench

− Editor and a project management tool is also included

• Intuitive user interface• The Make Utility recompiles, reassembles, and links files only if necessary• Full integration between Workbench tools and editor• Support of 78K0S, 78K0 and 78K0R microcontrollers• Embedded C++ support• A #pragma directive to maintain portability while using processor specific

extensions• Central Device Selection

315


Stack Window Features• Stack contents are displayed as

− raw data,− C/C++ variables and− function frames

• Current and maximum stack consumption is displayed graphically• Warnings can be issued,

− if the stack exceeds a certain level or − if the stack pointer points outside the stack memory

316


Trace Window Features• Function Trace

− Displays a subset of the trace datacorresponding to calls to and returns from functions

• Find In Trace− Shows the same columns and data as full trace but only those rows

which matches a certain search criteria

• Trace Expressions− Possibility to enter expressions that appears as extra columns in the

Trace window

• Browse mode− Follow the execution history by scrolling the Trace window− The source and disassemble windows highlight the corresponding

location

317


C-Spy Debugger Features• All C-Spy Drivers are included in one product

package:− EW78K-FULL-EE: Full version− EW78K-KSxx-EE: Kickstart version (limited code size)

• The C-Spy Debugger supports different targets:− IECUBE Emulators (QB-78K0xxx-ZZZ-EE, QB-78K0Rxxx-ZZZ-EE)− MINICUBE Emulators (QB-78K0MINI-EE, QB-MINI2-EE)− TK-Interface (direct USB Interface to starter kits)− Simulator (Instruction set simulator)

318


Basic C-Spy Debugger Windows• Workspace Window• Source Window(s)• Watch Window• Disassembler• Message Window

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License for a single user• Installation of the software

directly possible with “Quick”-Start-key

• Receiving permanent key after registration

• Different license assignments available− Individual PC

− License transfer by floppy disk

− License management needed

− DONGLE− License transfer by

“DONGLE”

License formultipleusers• Server handles

licenses automatically• Different license assignment

available− Individual server

− License transfer by floppy disk

− License management needed

− DONGLE− License transfer by

“DONGLE”

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IAR EWB-PACKETSoftware, License number, “Quick” Start-key and License manager

Decision for a license to a "DONGLE”

Decision for a license on an individual PC

Installation of software with license number and

“Quick” Start-key

Install the “DONGLE” Automatic generation of the individual license information during the installation of the

software [registration.txt]

Time limited installation of the software, after 30

days the license will expire

Reception of permanent key from IAR

Upgrade to unlimited installation with license manager, the license is now

assigned to a “DONGLE”

Installation of software with license number and

“Quick” Start-key

Time limited installation of the software, after 30

days the license will expire

Sending license information to IAR [registration.txt]

Upgrading to unlimited installation with the license manager, the license is now

assigned to an individual PC

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Applilet

Applilet is a software tool to generate device driver code for initialization and use of on-chip peripherals

Features• Device driver code generation

based on the user settings in the Graphical User Interface

• Initialization Code and API functions are provided

Targets• Easy to use Graphical User

Interface• Fasten the Development Process• Improve Code Quality• Common API to all devices

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Applilet

Applilet®

Configurator

CPU Device LayerLibrary sw generated by the Configurator

CPU

User Application LayerUser Code

Applilet API Specification

CPU Application LayerAbsorbs differences of each CPU type

Calls library sw of the CPU Device Layer

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Applilet

Project Wizard• The integrated project wizard guides the user step by step through the

New Project creation

78K0R/KE3

uPD78F1166

78K0R/KE3uPD78F1166

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Applilet

Graphical User Interface – Peripheral View

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Applilet

Graphical Device Configuration• User friendly and intuitive• Automatical plausibility checks avoid illegal configurations

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Applilet

Graphical Device Configuration• Source code generation can be started, when configuration is completed• Configuartion changes can be merged into a previously generated

configuration or previously generated source code

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MINICUBE2

Features• On-chip Debug Emulator

• Flash Programming

• Standard debug function support

• Go & Go, Start from here, Come here, Restart, Step execution, Forced break

• Hardware breakpoints: 1

• Software breakpoints: 2000

• Pseudo Real-Time RAM Monitoring (2-wire mode only)

• Direct Memory Manipulation during RUN (2-wire mode only)

• USB 2.0 interface

• Supplied via USB (no power supply necessary)

• 10 byte security ID code to avoid unauthorized access to device

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MINICUBE2

Circuit connection example• Target connector can be used for

MINICUBE2 and FlashPRO5• TXD and RXD are internally

connected in MINICUBE2, but not in FlashPRO5

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MINICUBE2

Memory Resources

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MINICUBE2

Hardware Configuration

78K0

This cable cannot be used for 78K0R microcontrollers debugging

78K0S/

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IECUBE

Features

• Professional In-Circuit Emulator• 512kB Emulation memory• Various Real-time and Non-

real-time program execution functions

• Event break function• Software break function• Trace function: 128K frames• Real-time RAM monitoring• Time measurement• USB 2.0 interface

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IECUBE

Trace Setting

• Emulator

− Trace …

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IECUBE

Tracewindow

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IECUBE

Self-Test Utility• Checks IECUBE operation when it does not operate normally• Takes about 1 minute for testing• Logs test results

− useful when making technical inquiries

• Included in the NEC Integrated Debugger

Screen during testing Result output screen

78K0R

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IECUBE - Sockets and Probes

Mandatory• Probe Extension Cable

QB-144-EP-01S

• Exchange AdapterQB-<nn><pp>-EA-0<x>TCaution:Pls. refer to the UM for the correct number of <x>

• ICE ConnectorQB-<nn><pp>-YQ-01T

• Target ConnectorQB-<nn><pp>-NQ-01T

<nn> : pin number, e.g. 80-pins => <nn> = 80<pp> : package type, e.g. GC-package => <pp> = GC<x> : 1, 4, 6, or 8 according to device type, e.g. <x> = 1

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IECUBE – Sockets and Probes

Selectable• Space Adapter

QB-<nn><pp>-YS-01T

• Check Pin AdapterQB-144-CA-01

• Mount AdapterQB-<nn><pp>-HQ-0<x>T

<nn> : pin number, e.g. 80-pins => <nn> = 80<pp> : package type, e.g. GC-package => <pp> = GC<x> : 1 or 3 according to device type, e.g. <x> = 1

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IECUBE – Sockets and Probes

Mandatory• Probe Extension Cable (EP)• Exchange Adapter (EA)• ICE Connector (YQ)• Target Socket (NQ)

Selectable• Space Adapter (YS)• Chip Cap (HQ)• Check pin Adapter (CA)

Mounting the device

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Flash Programmer

Programming with external programmer• FlashPRO5 PG-FP5-EE• MINICUBE2 QB-MINI2-EE

− In flash programming mode

• Flash Programming Support Package• Dedicated third party programmers

− Ertec (www.ertec.de) − Data I/O (www.dataio.de)− BP Microsystems (www.bpmicrosystems.com)

• Programming Adapter

Self-programming• NEC Self-programming Library

Under

plannin

g

Under

plannin

g

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Flash Programmer

Full support of programming on• dedicated programming adapter or • directly in the user system

USB

Target Application Hardware

UART

x.xV

Flash-Programming Adapter

Power supplyis required for programming via UART

USB

MINICUBE2

Level Shifter

Stand alone

PG-FP5-EE

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Flash Programmer

PG-FP5-EE• Supports programming of all single-voltage and the

most dual-voltage NEC flash devices• On-board programming• Stand-alone programming• Program files and programming parameters are stored in the internal flash

memory• Multiple program files and programming parameters can be stored in the

internal flash memory• Universal host connection, a Windows User interface is provided for

terminal connection• CSI, CSI + HS, UART, I2C, Port Mode and TOOL interface supported for

data transfer to flash devices• USB 2.0 interface or RS232 interface selectable

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Flash Programmer - Programming Modes

Host controlled:

In this mode, the programmer is controlled by a host PC via USB or RS232 cable.

Stand-alone:

Up to 16 MB code can be stored in the internal memory for stand-alone programming.

Target hardware orprogramming adapter

or

Target hardware orprogramming adapter

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Flash Programmer

Functional Overview PG-FP5-EE

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Flash Programmer

MINICUBE2 QB-MINI2-EE• Supports programming of all 78K devices• Attached to 78K0R IECUBE?• Universal host connection, a Windows User interface

is provided• Uses same PRM files as PG-FP4• Host connection via USB 2.0

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13. Support

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Technical Product Support

TPS provides comprehensive Pan-European support for all technical issues related to the NEC microcontroller/computer products:• Device specific support• Application specific support• Hardware and software development tool support• Quality and reliability support• Device failure analysis• Workshop & Trainings on devices and development tools

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Organization

Today 26 engineers are involved in the direct general support for microcontrollers

• The support team is organized in “groups” which take care for one specific device family and have a dedicated “group” - email address

− [email protected] for all 78K support− [email protected] for all V850 support− [email protected] for all flash-related questions− [email protected] for all compiler related issues

(IAR/Greenhills)

• Additional “in-house” resources areavailable for special subjects

• CAN, LIN• other automotive related subjects• EMI

mailto:[email protected]




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http://www.eu.necel.com

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http://www.eu.necel.com

Generaldocumentation

Microcontrollerrelated

downloads

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Document Database

Access on all released documents• Product Information, Product Letters• Data Sheets, User‘s Documents• Customer Notifications• Technical Reports• Application Notes• ...

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Tool Update

Tool Update Requestis possible via Internet• Free of charge

Pick-Up Service

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Development Tool Download

•Device Files•Flash ProgrammerSW package•Flash ProgrammingParameter Files•...

Development ToolsSoftware downloadpossible via Internet• Compiler, Assembler

and Linker SW package(License necessary)

• Debugger SW package

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Tool Repair

Tool Repair Request ispossible via Internet• Easy by filling our

Tool Repair Questionnaire

• Free of charge Pick-Up Service

EPMC-PU-0114-1.0

Documents

Transcript of EPMC-PU-0114-1.0