EOS Training Coursestaff.utar.edu.my/limsk/Consultancy/EOS.pdf · 2010. 10. 12. · EOS Test...
Transcript of EOS Training Coursestaff.utar.edu.my/limsk/Consultancy/EOS.pdf · 2010. 10. 12. · EOS Test...
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Electrical Overstress Course
EOS Training CourseDr. Lim Soo King
Dip Sc (Merit); B Sc (Hons); Dip Mgt (Dist)M Sc; PhD; MIPM
Associate ProfessorUniversiti Tunku Abdul Rahman
31 Jul 06.
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Electrical Overstress Course
� Understand the phenomena of EOS.
� Ability to set-up an effective EOS program for the organization.
� To improve the cost, quality, cycle time, and reliability.
� To reduce customer complaint.
� Reduce the wastage due to EOS.
Objectives of the Course
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Electrical Overstress Course
Introduction
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� Introduction.
� Theory of EOS.� Characteristics of EOS.
� Miniaturization of device.� Device structures.
� Causes of EOS.
Outline of the Course
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� Failure mechanism of EOS.
� Theory of failure.� EOS test methodology.
� EOS prevention� Reference.
� JVC case study.
Outline of the Course
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� EOS is defined as electrical overstress.
� Semiconductor devices have a limited ability to sustain electrical overstress.
� The device susceptibility to EOS increases as the device is scaled down to submicron feature size.
� 37% for the IC failures can be attributed to ESD/EOS events.
Introduction
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World Revenue of Semiconductor
0
50
100
150
200
250
'86 '90 '92 '94 '96 '98 '00 '02 '05 '06
Bil $
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Roadmap of Device
664M
269M
109M
44 M18 M6.6MTransistor density (cm 2)
0.5 -
0.6
0.6 -0.8
0.8 -1.2
1.0 -1.5
1.5 -1.9
1.9 -2.5
Equivalent oxide thickness ( µµµµm)
0.0350.050.070.100.130.18Channel length (µµµµm)
141108050299Year
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Field Return Failure Mode
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Theory of EOS
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Theory of EOS
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� An EOS failure is typically catastrophic and causes irreparable damage to the device.
� ESD and EOS are interrelated. Device weaken by ESD would have EOS easily.
� It is the large scale ESD.� The duration of EOS events ranges from
milliseconds to seconds (typical > 50 µsec).
Theory of EOS
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Characteristics of
EOS
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Characteristics of EOS
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�Time duration a few ns to a µs to resulting ESD.
�Time duration > 50 µs to < 100 µs causes junction punch through.
�Time duration > 100 µs causes melt metal, fused wire, and bond wire.
Characteristics of EOS
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Miniaturization of
Device
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Miniaturization of Device
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�The permissible critical field strength of expitaxial layer can be only 100V depending on thickness and doping level.
�Shallow junction depth. �Junction breakdown voltage is usually
around 20V.
Miniaturization of Device
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Device Structure
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Device Structure
CMOS output consist of p-channel and n-channel MOSFET
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Device Structure
CMOS output consist of p-channel and n-channel MOSFET
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Device Structure
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Device Structure
Power MOSFET device structure - BJT and diode parasitic components
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Device Structure
IGBT device structure
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Causes of
EOS
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Causes of EOS
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�Device designed with parasitic component which is the source of EOS.
�Bad fabrication controlOver etch.Photo resist residue.Violation of design rule.
Causes of EOS
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Causes of EOS
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�No common ground test system and device.Inductive effect.Resistive effect.
� Improper shutdown of deviceWrong power sequencing.Hot-plug the device.
Causes of EOS
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�Poor quality system. Burn-in spike.
�Poor specifications.�Wrong orientation.�PCB signal integrity.�Transient overshoot and undershoot
controlled within absolute max. rating.
Causes of EOS
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Causes of EOS
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�Noisy power sourceTransient spike.5 V part with a 2.5 V spike – 50% EOS.2.5 V part with a 2.5 V spike – 100% EOS.1.5 V part with a 2.5 V spike – 167% EOS.
Causes of EOS
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Failure Mechanismof
EOS
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Failure Mechanisms� Thermal-Induced failure
Doping level.Junction depth.Device characteristic particularly dimension.
� Electro-migrationHigh electric field.Migration of metal ion from high field to low field area.
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Failure Mechanisms
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Failure Mode
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Failure Mode
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Failure Mode
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Failure Mode
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Failure Mode
Secondary breakdown Metallization burn
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Failure Mode
Diffusion damage
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Failure Mode
I/O resistor damage
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Failure Mode
Thermal EOS – base-emitter region
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Failure Mode
Thermal EOS – melt wires
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Failure Mode
Thermal EOS – latch-up
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Failure Mode
Blown metal line Melt contact and bus
Melt bond pad
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Theory of Failure
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Theory of Failure
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Theory of Failure – Current Density
High current density that melts aluminum metallization and blows gold/Al bond wire.
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Theory of Failure - Undershoot
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Theory of Failure - Undershoot
� Simultaneous switching causing current from package, wire to be greater than forward current of diode resulting net current flow in package parasitic resistive and inductive components.
� This would cause the device’s ground well below the system.
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Theory of Failure - Undershoot
� The voltage difference between power pin and device ground will be far exceeding its normal VCC voltage.
� This would cause EOS.� The illustration is shown in next few foils.
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Theory of Failure - Undershoot
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Dr. Lim Soo King 54
Electrical Overstress Course
Theory of Failure - Undershoot
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Dr. Lim Soo King 55
Electrical Overstress Course
Theory of Failure - Undershoot
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Dr. Lim Soo King 56
Electrical Overstress Course
Theory of Failure - Overshoot
� As illustrated in pervious graph, overshoot would result the ground of the device being shifted upward.
� The voltage across the device is less than VCC.
� Soft-bit would be resulted as a problem.
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Dr. Lim Soo King 57
Electrical Overstress Course
Theory of Failure – Latch-up
� This is true for CMOS and IGBT devices.� It is caused by input voltage is greater than
the power supply voltage by at least 0.7V.� 0.7 V is the forward voltage VF of a diode.� The p-channel MOSFET acts lateral pnp
transistor.� The n-channel MOSFET act as vertical npn
transistor.� These two transistors are connected as
thyristor.
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Dr. Lim Soo King 58
Electrical Overstress Course
Theory of Failure – Latch-up
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Dr. Lim Soo King 59
Electrical Overstress Course
Theory of Failure – Latch-up
� This event creates tremendous increase of current that the power density would melt the Al metallization or blow wire.
� Unclean power supply voltage would cause latch-up.
� Noise input such as overshoot would cause latch-up.
� The illustration of latch-up is shown in the following foils.
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Dr. Lim Soo King 60
Electrical Overstress Course
Theory of Failure – Latch-up
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Dr. Lim Soo King 61
Electrical Overstress Course
Theory of Failure – Latch-up
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Dr. Lim Soo King 62
Electrical Overstress Course
Theory of Failure – Latch-up
VBE of npn transistor > 0.7V, leakage current, latch-up occurs.
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Dr. Lim Soo King 63
Electrical Overstress Course
Theory of Failure – Electro-migration
High electric field.Electro-migration forces metal ions to movedownstream mainly along the grain structure.
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Dr. Lim Soo King 64
Electrical Overstress Course
EOS Test Methodology
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Dr. Lim Soo King 65
Electrical Overstress Course
EOS Test Methodology
� Purpose is to weed out the infant mortality failure due to fab, assembly, handling, etc.
� Applying HBM, MM, CDM, field induced model, floating induced model according to Mil-std-883 E method 3015.7.
� Burn-in or “dirty” burn-in according to Mil-std-38510.
� Final test.
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Dr. Lim Soo King 66
Electrical Overstress Course
Bathtub Curve of Device
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Dr. Lim Soo King 67
Electrical Overstress Course
EOS Prevention
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Dr. Lim Soo King 68
Electrical Overstress Course
EOS Prevention
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Dr. Lim Soo King 69
Electrical Overstress Course
EOS Prevention
� Prevent power surge by using uninterrupted power supply.
� Power line of PCB should be designed not too close to prevent high induced voltage.
� Use isolation when necessary. � Use capacitor filtering (0.01µF) connecting
to the power supply of device.
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Dr. Lim Soo King 70
Electrical Overstress Course
EOS Prevention
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Dr. Lim Soo King 71
Electrical Overstress Course
EOS Prevention
� Measure the parasitic resistance and inductance of the device package to minimize voltage difference between device ground and system ground.
� Prevent hot-plug of device into or out of PCB or test socket.
� Prevent high tension inductive field such as from computer terminal.
� Use shielding technique to eliminate interference.
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Dr. Lim Soo King 72
Electrical Overstress Course
EOS Prevention
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Dr. Lim Soo King 73
Electrical Overstress Course
References
�ESDA S20.20.�DOD-HBK-263 B.�Mil-std-1686A.�883 E method 3015.7.�Mil-std- 38510.
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Dr. Lim Soo King 74
Electrical Overstress Course
Q and ASession
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Dr. Lim Soo King 75
Electrical Overstress Course
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