LETI Innovation Days—D43D 2019: Design for 3D Stacking Workshop June 25th, 2019

Shawna Liff

Principal Engineer & Assembly Prototyping Lab Manager

Intel Corporation

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Outline• Industry Trends

• Heterogeneous Integration Optimizations

• Cost

• Performance

• Time-to-Market (& Dependable)

• Summary

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A Data-Centric World

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Ubiquitous Data Provides Opportunity

Goal—Enable Scalable, Energy Efficient Compute from Sensors to Servers

Amount of data generated is growing exponentially

Raw data by itself is of little value, but when refined into useful data, it can be significant

Storage and movement of data becomes as critical as computation

Ref: https://blog.seagate.com/human/idc-asks-whats-your-datcon-are-you-ready-for-never-ending-global-data-expansion/

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Data Volume Changes Data Center Topology

Data transport cost exceeds compute cost

Consequently, data centers proliferating near the edge, closer to data

Enabling reduced transmission costs, greater privacy, lower latency

Within a data center, compute/data are distributed which has hardware & software implications

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Ref: R. Nagisetty, Chiplet Ecosystem Presentation, OSDA 2019.

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Rise of Domain Specific Architectures

Google’s TPU for neural net inference

Efficiency gains by tailoring architecture to domain characteristics

Benefits enhanced by co-design of Domain Specific Language (DSL) with Domain Specific Architectures (DSA)

- More effective parallelism for a specific domain

- More effective use of memory bandwidth

- Elimination of unneeded accuracy

DSA’s/DSL’s are designed for targeted environments (eg.)

- Neural networks for Machine Learning

- GPU’s for graphics and VR

- Imaging, graph processing

- Programmable network switches & interfaces…Ref: Norman P. Jouppi, Cliff Young, Nishant Patil, David PattersonCommunications of the ACM, September 2018, Vol. 61 No. 9, Pages 50-59

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Generalization vs. Specialization Inflection

Ref: https://www.defensemedianetwork.com/stories/the-intertwined-history-of-darpa-and-moores-law/ Nov. 19, 2018 Ref: Gordon Moore, Nov. 8, 1965

It may prove to be more economical to buildlarge systems out of smaller functions, whichare separately packaged and interconnected.The availability of large functions, combinedwith functional design and construction, shouldallow the manufacturer of large systems todesign and construct a considerable variety ofequipment both rapidly and economically.

Moore’s Law Evolves & Heterogeneous Integration Provides Flexibility for Product Performance & Cost Optimization

LETI Innovation Days—D43D 2019: Design for 3D Stacking Workshop June 25th, 2019 9

Numerous Integration Solutions Available

How to select the right advanced packaging solution for the product?

FC-LGA InFO EMIB CoWoS(Passive Interposer)

Foveros (3D)

AMD Zen 2 Apple A10 Intel Stratix 10 Intel LakefieldNvidiaTesla V100

• Cost

• Performance

• Time-to-Market (& Dependable)Ref: Cheung, Wai Ming, Newnes, Linda, Mileham, Antony, Marsh, Robert and Lanham, John (2009) Data Modelling and Optimization in Cost Estimation for Innovative Low Volume Product Development. In: ICMR'09 - 7th International Conference on Manufacturing Research, 8th - 10th September 2009, Warwick, UK

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Cost Optimization

Ref: Open Compute Project, https://www.eetimes.com/document.asp?doc_id=1334826#

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Interconnect Optimization

Ref: https://semiengineering.com/waiting-for-chiplet-interfaces/Ref: https://newsroom.intel.com/wp-content/uploads/sites/11/2019/04/interconnect-scope-infographic.pdf

Ideally a multi-chip package would perform as near to monolithic IC as possible, but physical & cost constraints drive interconnect & protocol selection.

On Board & Off

On Package & Off

On Die & Off

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Lateral Interconnect Solutions

Solution cost trends inversely with half-line pitch

• Where organic is less expensive than silicon

Consequently a trade-off between dense and slow signaling vs. wide and fast is made, pending reach.

IO/m

m/L

ay

er

Half Line Pitch (mm)

Technologies that use Si backend wiring

Traditional Organic Packages (FCBGA)

FO-Interposers or High Density Organic Interposers

Ref: R. Mahajan, 3D & Systems Summit, 2019Ref: R. Mahajan, ECTC, 2016

HDI….PCB

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Vertical Interconnect Solutions

Higher Density (smaller pitch) enables• Smaller die size• Simpler, smaller circuits• Lower power

However, smaller pitch drives• Denser lateral interconnect solution• More complex assembly with

• More stringent cleanliness

Pitch (mm)

Ve

rtic

al

De

nsi

ty (

IO/m

m2)

HDI PCBTraditional Organic

Package (FCBGA)

2.5D & 3D Solutions

Ref: I. Jani et al, ECTC 2019

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Comparison of Advanced Solutions

Package (FCxGA)

Fan Out (Chip First)

Fan Out (Chip Last)

EMIB Passive Silicon Interposer

Foveros On-die

Package Size (mm2)

<10,000 <400<2000

<3200 <10,000 (local Si Bridge)

<1600 2400

<830 < 830

Lateral Density (IO/mm/ly)

~35 100-333 60-333 1000+ 1000+ 1000+ 1000+

Vertical Density (IO/mm2)

>100 NA TBD >330 >330 >400 >105

AMD Zen 2 Apple A10

Ref. D. Oh, IMAPS Keynote, 2019

Intel Stratix 10 Intel LakefieldNvidiaTesla V100

Samsung TBD

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Other ConsiderationsAffordable chiplet solutions drive need for

True KGD• Comprehensive coverage at wafer sort

• DFT differentiation

Multi-vendor solution interoperability, debug & validation

• Resilience to chiplet & system solution differences • Design to avoid marginalities e.g. voltage margining,

repair/recoverability, etc.• Mechanical & electrical characteristics known • Manufacturing traceability

Comprehension of power & thermals• Predictive workloads and power density mapping• Solutions for

• Thermal cross-talk• Junction temperature limitations • Power/Temperature management

Ref: R. Nagisetty, Chiplet Ecosystem Presentation, OSDA 2019.

Ref: R. Mahajan & R. Sankman, “3D Packaging Architectures and Assembly Process Design” Chapter 2 of 3D Microelectronics Packaging, 2017.

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Heterogeneous Integration

Enables Compelling Products

17

Summary

Changing Market Drives

Domain Specific Architectures

Explosive growth of data

diverse and complex workloads

Sophisticated customer requirements

Agile Advanced Packaging

Provides Performance, Cost & Time-To-Market Flexibility

Opportunities abound in a burgeoning chiplet industry (“A New Golden Age”) & rapid advancements in performance, cost, & manufacturing are expected.

Ref: J.L. Hennessy and D.A. Patternson, “A New Golden Age for Computer Architecture,” Communications of the ACM, February 2019