ENEE 644ENEE 644

Dr. Ankur SrivastavaDr. Ankur SrivastavaOffice: 1349 A.V. WilliamsOffice: 1349 A.V. Williams

Email: ankurs@eng.umd.eduEmail: ankurs@eng.umd.eduURL: http://www.ece.umd.edu/class/enee644/URL: http://www.ece.umd.edu/class/enee644/

Computer-Aided Design of Digital Systems-- Logic Synthesis and Optimization

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Course OutlineCourse Outline

IntroductionIntroduction Algorithms and ToolsAlgorithms and Tools Two-Level Logic SynthesisTwo-Level Logic Synthesis Multi-Level Logic SynthesisMulti-Level Logic Synthesis Sequential System SynthesisSequential System Synthesis

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IntroductionIntroduction

Very Large Scale Integration (VLSI)Very Large Scale Integration (VLSI) Computer-Aided DesignComputer-Aided Design Design ProcessDesign Process Design StylesDesign Styles Logic Synthesis: an OverviewLogic Synthesis: an Overview Design Space and OptimizationDesign Space and Optimization

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Integrated CircuitsIntegrated Circuits SSI, MSI, LSI, and VLSISSI, MSI, LSI, and VLSI Moore’s LawMoore’s Law

Microelectronics is the Enabling TechnologyMicroelectronics is the Enabling Technology

(Micro-Electro-Mechanics more recently)(Micro-Electro-Mechanics more recently) Design Automation is the Enabling ToolDesign Automation is the Enabling Tool

VLSI CircuitsVLSI Circuits

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Moore’s LawMoore’s Law

The logic density of silicon integrated circuits The logic density of silicon integrated circuits is doubled every 18 months.is doubled every 18 months.

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Intel 4004 (1971)Intel 4004 (1971)

Intel’s first Intel’s first microprocessormicroprocessor

2,300 transistors2,300 transistors 108 KHz108 KHz 10 micron10 micron

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Intel386™ (1985)Intel386™ (1985)

First 32-bit chipFirst 32-bit chip 275,000 transistors275,000 transistors 16MHz – 33 MHz16MHz – 33 MHz 1 micron1 micron Multi-taskingMulti-tasking

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PentiumPentium®®III(1999)III(1999)

9.5 million transistors9.5 million transistors 0.25-micron technology0.25-micron technology Internet Streaming Internet Streaming

SIMD extensionsSIMD extensions

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Design Technology ChallengesDesign Technology Challenges

Productivity Productivity design meaningfully with huge number of transistorsdesign meaningfully with huge number of transistors

PowerPower design under the single-chip package power limitdesign under the single-chip package power limit

Manufacturing IntegrationManufacturing Integration InterferenceInterference

resource-efficient communication and synchronizationresource-efficient communication and synchronization

Error-ToleranceError-Tolerancerelaxation of the requirement of 100% correctnessrelaxation of the requirement of 100% correctness

Source: ITRS 2001 EditionSource: ITRS 2001 Edition

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Computer Aided DesignComputer Aided Design

RoleRole HistoryHistory Difficulty: size, NP-hardDifficulty: size, NP-hard Market and Key PlayersMarket and Key Players

Tens of billions $ industryTens of billions $ industry 4 major CAD companies4 major CAD companies CAD groups in large companiesCAD groups in large companies Universities with strong CAD groupsUniversities with strong CAD groups

Conferences and Journals Conferences and Journals

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Brief History of CADBrief History of CAD 1950-1965 1950-1965

manual design, impractical algorithms (even for MSI).manual design, impractical algorithms (even for MSI). 1965-19751965-1975

physical design tools for automatic layout of gate arraysphysical design tools for automatic layout of gate arraysIBM: Engineering Design SystemIBM: Engineering Design SystemAT&T: LTX system for standard cellsAT&T: LTX system for standard cells

logic design tools: logic design tools: IBM’s Mini: 2-level heuristic minimizerIBM’s Mini: 2-level heuristic minimizerEspresso: (IBM and Berkeley) PLA-based designEspresso: (IBM and Berkeley) PLA-based design

1975-19851975-1985placement and routing, technology mapping, multi-level optimizationplacement and routing, technology mapping, multi-level optimizationtheoretical development in physical designtheoretical development in physical design

1985-1985-performance/power driven design methodologiesperformance/power driven design methodologiesparallel algorithm, graph theory, combinatorial optimization problems parallel algorithm, graph theory, combinatorial optimization problems

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Design ProcessDesign Process

System SpecificationSystem Specification Functional DesignFunctional Design Logic DesignLogic Design Circuit DesignCircuit Design Physical DesignPhysical Design FabricationFabrication PackagingPackaging

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Design StylesDesign Styles

Full CustomFull Custom Semi-CustomSemi-Custom Programmable Programmable

Trade-off:Trade-off:Cost, flexibility, performance, area, power, time-to-Cost, flexibility, performance, area, power, time-to-

marketmarket

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Logic Synthesis: OverviewLogic Synthesis: Overview

Goals:Goals: Generate the logic-level model of the systemGenerate the logic-level model of the system Optimize the logic-level modelOptimize the logic-level model

Problems and Tools:Problems and Tools: Two-level circuits: Boolean algebra, Binary decision Two-level circuits: Boolean algebra, Binary decision

diagramdiagram Multi-level circuits: Boolean networks, Factored formMulti-level circuits: Boolean networks, Factored form Sequential circuits: Finite state machine, graph Sequential circuits: Finite state machine, graph

algorithmsalgorithms

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Design Space and OptimalityDesign Space and Optimality

Implement a circuit that outputs true iff all four Implement a circuit that outputs true iff all four inputs are true using 2- and 3-input AND gates.inputs are true using 2- and 3-input AND gates. Logic specification.Logic specification. How many different implementations?How many different implementations? Area and delay: optimization targets. Area and delay: optimization targets. Trade-off curve and Pareto points.Trade-off curve and Pareto points.

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Design Space and Optimality (cont’d)Design Space and Optimality (cont’d)

area

delay

area constraint

delay constraint

Trade-off curveSet of Pareto pointsOptimal designs

failed design

successful design

optimal design

Xinfeasible design

optimization