eMMC 5.0 Total IP Solution
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Transcript of eMMC 5.0 Total IP Solution
Copyright © 2014, Arasan Chip Systems, Inc.Slide 1
eMMC 5.0
Total IP Solution
Zachi FriedmanSenior Director of Marketing
Arasan Chip Systems, Inc.
Apr. 2014
Copyright © 2014, Arasan Chip Systems, Inc.Slide 2
Agenda
• eMMC 5.0 Market Adoption Update
• eMMC 5.0 Technical Overview
• Arasan’s Total IP Solution for eMMC 5.0
• Questions & Answers
Copyright © 2014, Arasan Chip Systems, Inc.Slide 3
eMMC 5.0 Market Adoption
New Application Processors:
• Qualcomm Snapdragon 801
• Marvell 88NV1088
New Smart Phones:• HTC One M8• Samsung Galaxy S5
New Devices:• Sandisk
Copyright © 2014, Arasan Chip Systems, Inc.Slide 4
What is eMMC?
• eMMC is a fully managed flash memory solution• Bad Block Management• Error Detection / Error Correction• NAND Flash Wear Leveling
• Seamless transition from SLC NAND to MLC NAND
• Compact FBGA footprint
• Streamlines development and qualification
• Very mature and widely used – most smartphones & tablets
Copyright © 2014, Arasan Chip Systems, Inc.Slide 5
eMMC –Evolution of Performance & Features
eMMC 4.51 (2012) eMMC 5.0 (2013) Next eMMC 5.1 (2014-5)
Max ThroughputHS200
1.6 Gbps (200MB/s)HS400
3.2Gbps (400MB/s)HS400
3.2Gbps (400MB/s)
Pin Count 10 Pins 11 Pins 11 Pins
Data Strobe - √ √
Enhanced Strobe - - √
Command Queuing - - √
Data Bus Width 4 or 8 bit 8 bit 8 bit
Max Clock (MHz) 200 (SDR) 200 (DDR) 200 (DDR)
Copyright © 2014, Arasan Chip Systems, Inc.Slide 6
Trends in Standards & Specs
Time
# of Standards
Decreasing TimeBetween Standard Revs
Gpbs
AnalogDigital Increasing
Performance
Copyright © 2014, Arasan Chip Systems, Inc.Slide 7
Processor
Application
Device Driver
NAND flash
eMMC 5.0 Host & Device Block DiagramPro
cess
or
(AR
M)
Syst
em
mem
ory
Hos
t Int
erfa
ce(M
aste
r / T
arge
t)
eMMCHost Register
Hos
t DM
A(S
DM
A/AD
MA2
)
Clock / PowerManagement
BlockBuffer eMMC Interface
Control (CMD/DAT/RES)
eMMCBus
eMMC 5.0 Host eMMC 5.0 Device
Transmitter / Receiver
Bus State Machine
AHB Slave
AHB Master
FIFOController
eMMCRegister
Command Decoder
Command Validator
Response Generator
eMMC Tuning Control
(CMD/DAT)
eMMC 5.0 PHY
eMM
C 5.
0 I/
O P
ads
Copyright © 2014, Arasan Chip Systems, Inc.Slide 8
eMMC 5.0 Analog PHY - HS400
• Hard PHY
• 200MHz DDR
• 3.3V / 1.8V pad
Digital Logic and
Control
Digital Logic and
Control
In
Drive Strength Register
Drive Strength Register
Out
VCDL32 Phase Tapped Delay Line
• Includes DLLs• For Tx, Rx, Rx STRB
• 28nm Process Technology
Rx Tuning Mode
VCDL32 Phase Tapped Delay Line
Tx Mode
VCDL32 Phase Tapped Delay Line
Rx Strobe Mode
Phase Detector
Charge Pump
Input strobe
Tx Clock
Rx Phase Select
Tx Phase Select
Copyright © 2014, Arasan Chip Systems, Inc.Slide 9
Arasan Provides End-End Solutions
• Analog IP – Lowest power & silicon size• GDS-II for customer specific process
technology • Full on-chip testability
• Digital IP – Easy integration to SoC• Delivered as RTL • Verification IP and synthesis scripts
• Verification IP – Enables low risk design• Verilog simulation environment with a
comprehensive test suite
• Full software stacks accelerates design• Bus interface layer, low level driver, protocol
stack and API’s
• Hardware Validation Platform • Full-speed emulation of host/device • Early software development platform
Copyright © 2014, Arasan Chip Systems, Inc.Slide 10
Mobile Storage Total IP Solution
Ara
san
SW
IP
Ara
san
Dev
ice
IP
Ara
san
Hos
t IP
OS / File System
Application SW
UFS SD/SDIO
SD/SDIO Controller
UFSController
UHS II M-PHY
Software Stack
SD/SDIO Controller
UFS Controller
UHS IIM-PHY
ONFIcontroller
NV-DDR2 & Pads
eMMC 5.0Controller
eMMC
Standard Interfaces
Ara
san
Har
dwar
e V
alid
atio
n P
latfo
rm
Ara
san
Ver
ifica
tion
IP
ONFIcontroller
ONFI
eMMC 5.0Controller
NV-DDR2 & Pads
eMMC 5.0 Pads & DLL
eMMC 5.0 Pads & DLL
Copyright © 2014, Arasan Chip Systems, Inc.Slide 11
eMMC 5.0 Hardware Validation Platform
Transaction Layer
PHY
LINUX
Middleware
Protocol Stack
Low Level Device Driver
PCI-Xpress Bus Interface Layer
So
ftw
are
Sta
ck
IP H
ardw
are
Bitm
ap
API
API
Memory CPUPCIe Bus FPGA
X86 Motherboard eMMC 5.0 Host IP Board
eMMC 5.0 Device
• Functions as eMMC 5.0 Host
• Supports HS400 (400MB/s)
• Backward compatible to eMMC 4.51
• Used as a “Gold Model” - enables early
validation and SW development
Link Layer
Copyright © 2014, Arasan Chip Systems, Inc.Slide 12
eMMC 5.0 HVP with On-Board Device
Copyright © 2014, Arasan Chip Systems, Inc.Slide 13
Availability & Maturity
• Arasan is a contributing member in the JEDEC committee defining eMMC standard
• Arasan is the leading IP provider for eMMC IP
• eMMC 5.0 Host and Device IP is shipping now
• eMMC 5.0 PHY (I/O Pads and DLLs) is shipping now in TSMC 28nm (HPM and LP) and TSMC 40LP
• TSMC 16FF in June 2014
• TSMC 16FF+ in July 2014
• Partners and Associations