Microprocessor Interface and

Programming (EMIP432C)

Dr. Prasanna Kumar MisraDepartment of Electronics and Communication Engineering

IIIT Allahabad

1. Review of Digital Electronics

2. Introduction to Microprocessor and Microcomputer

3. 8086 Architecture, Instruction sets

4. Peripherals and Interfacing

5. Basics of 80186,80286,80386,80486 and Pentium Processors

6. Conclusion and Summary

Outline

Microcomputer Architecture

Clock Gen.8284

ROM

RAM

ProgrammableperipheralInterface

8255

8259

8254

8251

ProgrammableInterruptController

ProgrammableIntervalTimer

RS232

PC

8086

Classification

Microprocessor

General Purpose Application Specific

Following parameters are used to classify the microprocessors

based on its applications.

• Performance

• Cost

• Power consumption

Classification

Intel Pentium 4 Processor [ISSCC 2004]

General Purpose

•Die size = 112 mm2

• 90 nm Process Technology

• 16 kB L1 Cache, 1 MB L2

Cache

• 125000000 transistors

Classification

Network Processor [IITK-2011]

process the incoming IPv4 packet headers of 20 bytes

Application Specific

• Die size = 2.25 mm2

• Core size = 1 mm2

• 180 nm Process Technology

• No Cache memory (Used

only registers)

• Clock Freq = 20 MHz

Classification

Following parameters are used to classify the microprocessors

based on its design.

• Semiconductor Technology (CMOS/BiCMOS)

• Technology node (500/350/250/180/130/90/65/45/32/22 nm)

• Data Width (8bit/16 bit/32 bit/64 bit)

• Instruction set (CISC or RISC)

CISC: Complex Instruction Set Computer

RISC: Reduced Instruction Set Computer

RISC minimizes CISC minimizes

CISC and RISC

Example

Main Memory

Register

+ - ×Execution

MULT 2:3, 5:2

LOAD A, 2:3LOAD B, 5:2MUL A, BSTR 2:3, A

1 2 3 4 5

1

2

3

4

5

CISC:

RISC:

[1] WILLIAM ASPRAY, “The Intel 4004 Microprocessor: What Constituted Invention”IEEE Annals of the History of Computing, Vol. 19, No. 3, 1997, pp.4-15.

Intel 4004 Microprocessor

• First µP (1971)

• 10 µm process technology

• 2300 transistors

• 400-800 KHz

• 4- bit word size

• 16 pin DIP package

Intel 8008 Microprocessor

•1972

• 10 µm process technology

• 3500 transistors

• 400-800 KHz

• 8- bit word size

• 18 pin DIP package

Intel 8080 Microprocessor

•1974

• 6 µm process technology

• 4500 transistors

• 2 MHz

• 8- bit word size

• 40 pin DIP package

Intel 8086 Microprocessor

•1979

• 3 µm process technology

• 29000 transistors

• 5-10 MHz

• 16- bit word size

• 40 pin DIP package

* X86 Instruction set architecture

* 20-bit adddresses (220 = 1 MB memory locations

Intel 80286 Microprocessor

•1982

• 1.5 µm process technology

• 134000 transistors

• 6-12 MHz

• 16- bit word size

• 68 pin DIP package

* Virtual Memory

* 20-bit adddresses (220 = 1 MB memory locations

Intel 80386 Microprocessor

•1985

• 1.5 µm process technology

• 275000 transistors

• 16-33 MHz

• 32- bit word size

• L1 Cache (off chip)

• 100 pin PGA

Intel 80486 Microprocessor

•1989

• 1 µm process technology

• 1200000 transistors

• 25-100 MHz

• 32- bit word size

• L1 (on chip) + L2 (off chip)

• 168 pin PGA

Pentium Processor

• Pentium -1993 (800 nm Process technology)

• Pentium II (350 nm Process technology)

• Pentium III (250 nm Process technology)

• Pentium IV- 2001(180 nm Process technology)

• Xeon-2003 (90 nm, Strained silicon)

• Dual core xeon -2005 (65 nm, Strained silicon, 3.5 GHz, 8-copper layer)

• Quad core xeon- 2007 (45 nm, High-K metal gate)

• Xeon 8 core-2009 (32 nm, High-K metal gate, 64-bit), 9-copper layer, L3)

• Processor with trigate devices - 2011(22 nm, L3)

* In Pentium processors separate instruction and data cache (on chip)

8 core Processor

Die of 8-core processor

Moore’s and Amdahl’s law

Moore’s Law: It states that the number of transistors on an

integrated circuit doubles every 1-2 years.

Amdahl’s Law: It states that if one enhances a fraction (f) of a

computation by a speed up (s), then the overall speedup is

• If f is small optimizations have little effect.

• If s goes very high, speedup = 1/(1-f).

Performance gap (Microprocessor and Memory)

• Microprocessor performance has been improving nearly

60% per year.

• Memory Performance (access time) however has been

improving nearly 10% per year.

• The resulting gap between microprocessor and memory

performance forced microprocessor designs toward complex

and power hungry architectures. This is due to introduction of

large cache hierarchies to hide main memory latency.

• Average time to access memory

IBM z196 Processor [ICICDT-2011]

IBM z196 Processor

45 nm SOI CMOS Technology

512 mm2

5.2 GHz speed

1.4 Billion transistors

1.5 MB L2 Cache,24 MB L3 cache

Core Area [ICICDT 2010]IBM Power7 Processor [ICICDT 2010]

Power7 Processor

45 nm SOI CMOS Technology567 mm2

4 GHz speed1.2 Billion transistors256 kB L2 Cache and 32 MB L3 cache

IBM Power8 Processor [ISSCC 2014]

Power8 Processor

22 nm SOI CMOS Technology649 mm2

4.8 GHz clock4.2 Billion transistors256 kB L2 Cache and 32 MB L3 cache

• A cache hit is a state in which data requested for processing by

a component/ application is found in the cache memory.

• It is a faster method of delivering data to the processor.

• A cache hit occurs when an application/software requests data.

Memory Hierarchy

Hard drive

Main Memory

Cache (L1,L2,L3)

Registers

Flash MemoryIntegration density Speed

Instruction Set Architecture

Hardware

Software

Hardware/Software Interface

Instruction Set Architecture

CPU I/OMemory

Digital Circuit

Transistors (NMOS, PMOS)

Compiler Firmware

Operating System

Applications

Instruction Set Architecture provides a well defined hardware/softwareinterface that has complete collection of instructions understood by CPU.