EMC aspects of High speed digital design

8/12/2019 EMC aspects of High speed digital design

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Henry W. OttHOCELECTROMAGNETICCOMPATIBILITY

EMC ASPECTS OF FUTUREHIGH SPEED DIGITAL DESIGNS

OOOO1

2000

By

Henry W. OttHenry Ott Consultants

Livingston, NJ 07039

(973) 992-1793

www.hottconsultants.com [email protected]

PCB Design Conference - EastKeynote Address

September 12, 2000


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ELECTROMAGNETIC COMPATABILITYDRIVING FORCES

SYS - 01008

2000

EMC

Regulations Technology

Signal

Integrity

Time to

Market


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DIFFERENTIAL - MODE RADIATION

DIG 00269

Signal

Ground

I

PCB

1998

Radiated

Emission

E = K1f2AI0


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CONTROLLING DIFFERENTIAL-MODE EMISSIONS

! Reduce Loop Area

PCB Technology Has Not Keep Up Withthe Increase in Frequency Squared

! Cancellation Techniques

Canceling Clock Loops

Multiple Decoupling Capacitors

!Spread Spectrum Techniques

Clock Dithering

ADIG - 01028

2000


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DIG - 01013

2000

Clockwise Loop Counter-Clockwise Loop

C CIC

Clock

Gnd

Gnd

CCW

CW

CANCELLATION TECHNIQUES


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COMMON-MODE RADIATION

DIG 00268

Gnd Plane

Or Grid

VN

PWB

IcmI/O Cable

Gnd Wire

IcmCable

Equivalent Circuit

VN

1998

E=K2fLIcm


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SKIN EFFECT

! Due to the Skin Effect, High Frequency Currents Can Only

Penetrate a Metal a Very Small Distance

! Therefore, at High Frequencies all Currents are on the Surface

of Conductors, and Cannot Penetrate them.

PCB - 01013

1996


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GROUND RETURN CURRENTS

! Return Currents Will Always Flow on the Nearest Plane

! The Top and Bottom Surfaces of a Plane Act as SeparateConductors

! If The Top and Bottom Surfaces of a Plane Are Used for the

Return Current, How Does the Return Current Get From the Top to the

Bottom of the Plane?

! If a Mixture of Power and Ground Planes are Used for the

Return Current,

How Does the Return Current Get From One Plane to theOther?

PCB - 01022A

1996


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GROUND CURRENT FLOW

PCB - 01049

1999

Plane

Signal

Layer

Signal

LayerPlane 1

Signal

Layer

Signal

Layer

Plane 2

?

Signal Traces Adjacent to the Same Plane Signal Traces Adjacent to Different Planes

OKA Problem Unless We

Do Something

Via

Via


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HIGH SPEED CLOCK ROUTING GUIDELINES(in order of preference)

! Route Clock on One Layer Adjacent to a Plane

! Route Clock on Two Layers, Adjacent to the Same Plane

!

Route Clock on Two Layers, Adjacent to Two Planes of theSame Type (i.e., Ground orPower) and Connect PlanesTogether With a Via Wherever there is a Signal Via

! Route Clock on Two Layers, Adjacent to Two Different Types ofPlanes (i.e., Ground andPower) and Connect Planes Together

With a Decoupling Capacitor Wherever There is a Signal Via

PCB - 01044

1998


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SLOT INDUCED GROUND PLANE VOLTAGE DROP(3 nS RISE-TIME SQUARE WAVE)

MEA - 00204X

1996

Notes:

Slot is 0.025 Wide.

Signal Trace Width is 0.050.

Holes = A Pattern of Fifteen 0.052 Diam.

Holes Along a 1 Line

llll VAB dB

0 in 15 mV

in 20 mV 2.5

in 26 mV 4.8

1 in 49 mV 10.3

1 in 75 mV 14.0Holes 15+ mV

BA

ViaVia

1

3

Ground

Plane

llll

Trace on Opposite

Side of Board


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We Must Learn To Ask The Question,

Where Does The Return Current Flow?

GRD - 01020

1999


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MEA - 00216X

1994

Ground Plane Current Distribution

I

Via

Ground Plane

Constriction of

Current, High

Inductance

Current Spreads Out, Low InductanceConstriction of

Current, High

Inductance

Trace on Opposite

Side of Board


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MEA - 01223

1998

Ground Plane Voltage Measurements(Peak to Peak Voltage)

Ground Plane

I

Via

6

1

88 mV15 mV15 mV15 mV

111


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0 1

0.1

1.0

10

100

2 3 43.52.51.50.5

GROUND PLANE INDUCTANCE NEAR VIA

1996

nH/inch

Inches from Via

MEA - 00218


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DECOUPLING NETWORK - EQUIVALENT CIRCUIT

DIG 00263

PWB

Trace

Inductance

Decoupling

CapacitorIntegrated

Circuit

15H 5H

5H3H

R

C

2H

1998


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MULTIPLE CAPACITORS

DEC - 01017A

1997

1

2

1

1

1

2

2

2

L/2

L/2 C

CC

Ct = C

Lt = L

L/2

L/2

L/2

L/2

L/2

L/2CC

L/2

L/2

L/2

L/2

L/2

L/2

C

C

C

Ct = 2C

Lt = L

Ct = 2C

Lt = L/2

Lt= L/3

Ct= 3C

General Equation

Ct= NC

Lt=L/N

For N Capacitors

of Value C, Each

in Series With anInductance L


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DECOUPLING

! It is Difficult to Achieve Good Decoupling at High Frequencies(> 50 MHz)

! One Way to Achieve This is With Multiple Capacitors (2-50)

Make Them The Same Value Spread Them Out Physically

! Another Approach is by Using Embedded PCB Capacitance

! Interdigitated Power & Ground Pins Helps Lower the IC Lead

Inductance! One of the Biggest Limitations in Using Decoupling Capacitors

is the Inductance of the Pad to Via Trace.

Use Multiple Vias, or

Pad in Via Technology to Reduce This

! Another Approach is to use Multiple Capacitors Inside the ICPackage Itself

! Isolated Power Planes Can be Helpful in Minimizing the BadSide Effect of Poor Decoupling But Does Not Solve the Basic

Problem

SI - 01017

2000


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SIGNAL INTEGRITY (SI) & EMC

! Signal Integrity: How a SignalEffects Itself

!Signal Integrity: UsuallyConcerned With Millivolts &Milliamps

! EMC: How a Signal EffectsOthers

! EMC: Usually Concerned WithMicrovolts & Microamps

SI - 01005

2000


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EMC & SIGNAL INTEGRITY

SI - 01006

2000

Physical PCB

LayoutElectrical

Design

EMC & Signal Integrity


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ELECTRICAL & PHYSICAL PARAMETERS

! Physical PCB Layout

Copper

Dielectric

Traces

Vias

Pads

! This is What We Build

! Electrical Parameters

Inductance

Capacitance

Resistance

Characteristic Impedance

! This is What The Signal Sees

SI - 01015

2000


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THERE ARE FOUR SOURCES OF

SIGNAL DISTORTION

! The Signal Net Itself

Discontinuities

Reflections

Attenuation

! Crosstalk

! Power & Ground Noise

Ground Bounce

Decoupling

! External Noise Sources

Radiated

Conducted

SI - 01011

2000


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HIGH DENSITY INTERCONNECT

! Chip Scale Packaging (CSP)

Ball Grid Arrays

Chip on Board

Flip Chip

Reduced Pkg. Inductance

! System on a Chip (SOC)

Large I/O Counts (>500)

!

PCB Layout/Stackup Closer Spaced Layers

Elimination of Surface LayerTraces

Transmission Lines

Faraday Shields! Testability Issues

Test Point Access

! PCB Materials

FR-4

Polyamide

Ceramic/Glass

PolyTetraFluroEthelyne (PTFE)

! Vias

Microvias (


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IC PACKAGE INDUCTANCE

IC - 01066

1998

200 400 600 800 1000 12000

Package Pin Count

5

10

15

20

0

Indu

ctance

(nH)

Flip Chip

BGA

PQFP

Ref: Lau, p. 37


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TRANSMISSION LINE LOSSES

! Skin Effect

! Dielectric Loss

! Ground Plane Loss

! Surface Roughness

! Radiation Losses

ADIG - 01001

2000


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SUMMARY(TRANSMISSION LINE LOSSES)

! For Traces Shorter Than 12 You Can UsuallyIgnore all Losses up to 1 GHz.

! Above 1 GHz Skin Effect Losses BecomeSignificant

! Above 3 GHz Dielectric Losses BecomePredominant

ADIG - 01024

2000


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IN SUMMARY

! The Difference Between Signal Integrity (SI) & EMCis Why You Do Something, Not What You Do

For EMC You Do Something to Minimize the

Emissions and Susceptibility or For RegulatoryCompliance

For Signal Integrity You Do The Same Thing toMake the Circuit Work Reliably

SI - 01022

2000


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NEW TECHNOLOGY

! Evolution of New Technology

State of the Art

Leading Edge

Commodity

! Embedded Capacitance

! Micro-Vias, Buried Vias. Blind Vias

! Chip Scale Packaging

! New PCB Materials

SYS - 01009

2000


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BE INNOVATIVE

! Understand the Basic Principles of EMC & SIand Apply them in New Innovative Ways

! Dont be Afraid to Do Things Differently

! Fund Some R & D With Respect to EMC & SI

! Consider New Technologies

! Whats New Today Will Probably be CommonTomorrow

! Continue to Learn and Educate Yourself

! Remember, Whatever You Did Last Time WillProbably Not Work Next Time

SYS - 01010

2000


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REFERENCES

! Ott, H. W., Noise Reduct ion Techn iques in Electron ic Systems, SecondEdition, Wiley Interscience, 1988.

! Johnson, H. W. & Graham, M., High-Speed Digital Design, Prentice-Hall,1993.

! Montrose, M. I., Printed Circui t B oard Design Techn iques for EMCCompl iance, IEEE Press, 1996.

! Fitts, M., The Truth About Microvias, Printed Circui t Design, February2000.

! Edwards, T. C., Foundat ions o f Microstr ip Circui t Design, Second

Edition, John Wiley & Sons, 1992.! IPC-D-317A, Design Guidel ines fo r Electronic Packaging Ut i l iz ing High

Speed Techniques, 1995.

! Wadell, B. C., Transm ission Lin e Design Handbook, Artech House, 1991.

! Johnson, H., Why Digital Engineers Dont Believe in EMC, IEEE EMC

Society News letter, Spring, 1998.! Lau, J. H., Ball Grid Array Technology, McGraw-Hill, 1995.

! IEEE EMC Society web page at .

! Henry Ott Consultants web page at .

2000

REFERENCES

EMC aspects of High speed digital design

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