Embedded Computing Systemslibvolume3.xyz/.../embeddedcomputing/embeddedcomputingnotes2.pdf · Notes...

Embedded Computing Systems

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Mangalore


6th SEMESTER COMPUTER SCIENCE

SUBJECT CODE: 10CS72

Sushma Shetty

7th Semester

Computer Science and Engineering

[email protected]

Notes have been circulated on self risk. Nobody can be held responsible if anything is wrong or is improper information or insufficient information provided in it.

Text Books: 1. Raj Kamal: Embedded Computing Systems, Mc Graw Hill Companies

Visit WWW.VTULIFE.COM for all VTU Notes

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UNIT 1

INTRODUCTION TO EMBEDDED SYSTEMS

EMBEDDED SYSTEMS

SYSTEM:

A way of working, organizing or performing one or many tasks according to a fixed set of

rules, program or plan.

It is an arrangement in which all units assemble and work together according to a

program or plan.

Eg:

o A time display system.

o A washing machine.

EMBEDDED SYSTEM:

An embedded system is a system that has software embedded into computer-hardware,

which makes a system dedicated for an application (s) or specific part of an application

or product or part of a larger system.

COMPONENTS OF A COMPUTER:

A microprocessor.

A large memory:

o Primary memory (RAM, ROM and fast accessible caches).

o Secondary memory (hard disks, diskettes and cartridge tapes, optical memory in CD-

ROM).

I/O units (touch screen, modem, fax cum modem).

Input units (keyboard, mice, digitizer, scanner).

Output units (LCD screen, video monitor, printer).

Networking units (Ethernet card, bus drivers).



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An operating system.

EMBEDDED SYSTEM COMPONENTS:

It embeds hardware similar to a computer. Fig below shows the hardware units of an

embedded system. It usually embeds in the ROM of flash memory and doesn’t require a

secondary memory.

It embeds main application software. It may perform tasks concurrently.

It embeds a real time operating system (RTOS).

CHARACTERISTICS:

Real time and multirate operations. (how the system works, reacts to events, interrupts

and schedules system’s functioning in real time).

Complex algorithm.

Complex GUI and other user interfaces.

Dedicated functions.

CONSTRAINTS:

Available system memory.



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Available processor speed.

Need to limit power dissipation when system is run continuously.

PROCESSOR EMBEDDED INTO A SYSTEM

EMBEDDED PROCESSORS IN A SYSTEM:

A processor has two essential units:

o Program Flow Control Unit (CU) : It includes fetch unit for fetching instructions from

memory.

o The EU : It has the ALU and circuits that execute instructions (halt, interrupt, jump) ,

data transfer and data conversion from one form to the other.

It runs the cycles of fetch and execute.

It is in the form of

o IC chip

o Core form in an Application Specific Integrated Circuit (ASIC).

o System on Chip (SoS)

EMBEDDED SYSTEM PROCESSOR CHIP OR CORE CAN BE ONE OF THE FOLLOWING:

General Purpose Processor (GPP) : Instruction set designed not specific to the

applications.

o Microprocessor.

o Embedded Processor.

Application Specific Instruction Set Processor (ASIP) : The instruction set is designed

specific to the applications on a VLSI chip.

o Microcontroller

o Embedded microcontroller

o Digital Signal Processor (DSP) and media processor

o Network Processor, IO Processor or domain specific programmable processor.

Single Purpose Processors.

o Coprocessor (graphic processing, flating point processing, encryption, decryption)

o Accelerator ( java codes accelerator)

o Controller (for peripherals, DMA, buses)



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GPP or ASIP cores integrated into ASIC or VLSI.

Application Specific System Processor (ASSP).

Multicore Processor or Multiprocessor.

SYSTEM DESIGNER CONSIDERATIONS FOR SELECTING A PROCESSOR:

Instruction set

Maximum bits in an operand in a single arithmetic or logical operation.

Clock frequency in MHz and processing speed in MIPS.

Processor ability to solve complex algorithms while meeting deadlines for their

processing.

REASONS FOR USING A GPP OR A MICROPROCESSOR :

Processing instructions available in the GPP results in quick system development.

Once the board and I/O interfaces are designed for a GPP, they can be used for a new

system just by changing embedded software in the ROM.

Ready availability of compiler.

Ready availability of well tested and debugged processor specific APIs.

MICROPROCESSOR

CPU is a unit that centrally fetches and processes a set of general purpose instructions.

CPU instruction set includes instructions for oprations such as for data transfer, ALU,

stack, IO and program control, sequencing and supervising.

The basic functional units:

o Control Unit (CU) for fetching instructions.

o An ALU.

A transceiver is a transmitting cum receiving circuit.

An encryption engine is a system that encrypts the data to be transmitted on the

network.

High performance processors have pipeline and superscalar architecture, fast ALUs and

Floating Point Processing Units (FLPUs).



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The important microprocessors used in embedded systems are ARM, 68HCxxx, 80x86,

SPARC family of microprocessors.

MICROCONTROLLER

An integrated chip that has processor, memory and several other hardware units in it.

It is the most essential part component of a control or communication circuit.

It is a single chip VLSI unit.

Even though it has limited computational capabilities, possesses enhanced input-output

capabilities and a number of on-chip functional units.

It is used when a small or part of the embedded software has to be located in the

internal memory and when on-chip functional units such as the interrupt handler, port,

timer, ADC, PWM and CAN controller are required.



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SINGLE PURPOSE PROCESSORS

Single purpose processors used in embedded systems include:

Coprocessor (for floating point operation).

Graphics Processor (gaming, display, move and rotate image segments).

Pixel Coprocessor (in digital cameras for displaying images directly or operations such as

rotate left, rotate right, rotate up, rotate down, Shift to next etc).

Encryption Engine (to encrypt data for secure transmission).

Decryption Engine ( to decrypt the encrypted data).



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A Disrete Cosint Transform (DCT) and Inverse DCT (IDCT) (for speech and video

processing).

Protocol Stack Processor.

Network Processor (to establish a connection, finish, send and receive ack, transmission

requests, check and correct data frame errors).

Accelerator ( eg, java codes accelerator).

CODEC ( coder and decoder) (encodes input and decodes the encoded information).

JPEG CODEC (jpg compression and decompression).

MPEG CODEC (mp3 compression and decompression).

Controller ( for pheripheral, DMA or bus).

EMBEDDED HARDWARE UNITS AND DEVICES IN A SYSTEM

POWER SOURCE:

Some embedded systems don’t have their own power supply and need to connect to PC

power supply lines or are powered by charge pumps. Eg: NIC and Graphic Accelerator.

Various units in an embedded system operate in one of the following four power

ranges: 5.0V+-0.25V, 3.3V+-0.3V, 2.0V+-0.2V and 1.5V+-0.2V.

Low voltage operations eg: cellular phone, in a system with smaller overall geometry.

CLOCK OSCILLATOR CIRCUIT AND CLOCKING UNITS

The clock controls the time for executing an instruction.

It controls the various clocking requirements of the CPU, of the system timers and CPU

machine cycles.

The processor clock out signal provides the clock for synchronizing all system units with

the processor.

SYSTEM TIMERS AND REAL-TIME CLOCKS

A timer circuit is suitably configured as the system clock which ticks and generates

system interrupts periodically for schedulers, real time programs and for periodic saving

of date and time in the system.



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The ISRs perform required operations after the time out.

RESET CIRCUIT, POWER-UP RESET AND WATCHDOG-TIMER RESET

The program counter (PC) (Instruction Pointer (IP) in case of 80x86) holds the address

from where the instruction is to be fetched for execution.

Code segment (CS) register holds the base address of the code memory segment.

Reset means that the processor begins the processing of instructions from the starting

address.

A program that is reset or power-up can be one of:

o A system program that executes from the beginning.

o A system boot up program.

o A system initialization program.

A reset circuit activates for a fixed period (few clock cycles) and then deactivates. On

deactivation of the reset that succeeds the processor activation, a program executes

from a start-up address.

Reset can be activated by an external reset circuit that activates on power-up, on

switching-on reset of the system or on detection of a low voltage. Alternatively, it can

also be activated by any one of the following :

o Software instruction.

o Watchdog timer.

o A clock monitor detecting a slowdown below certain frequencies.

Watchdog timer is a timing device that resets the system after a predefined timeout.

It is activated within first few cycles after power-up.

It is very essential because it helps in rescuing the system if a fault develops and the

program gets struck. It is used in control applications like in satellites, robots.

MEMORY

Figure below shows a chart of various forms of memory that are present in systems.



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Internal RAM of 256 or 512 bytes in a microcontroller for registers, temporary data and

stack.

Internal ROM/PROM/EEPROM for about 4kB to 64kB of program.

External RAM for temporary data, stack or internal caches.

Internal flash (non volatile memory).

Memory stick.

External ROM or PROM for embedded software.

RAM memory buffers at ports.

Caches.

INPUT, OUTPUT AND IO PORTS, IO BUSES, IO INTERFACES

System gets input through input ports. Input ports eg:

o A system gets input from touch screen, keyboard, sensors, transducer.

o A controller gets input from sensor and transducer.

o A receiver of signals or a network gets input from communication system.

o Ports receive input from a network or peripheral.

Output port eg:



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o Output may be sent to a LED, LCD or touch screen display panel.

o Output to a printer.

o Output to a communication channel or network.

o Control system sends output to alarms, actuators, furnaces or boilers.

o Robot is sent output to various motors.

There are general purpose ports for both input and output operations.

o Eg: touch screen.

o IO port is identified by an address to which a read and write operations both take

place.

o A system may have to send output to various channels. A demultiplexer or

multiplexer can then be used.

o A demultiplexer is a digital circuit that sends digital outputs at any instance to one

of the provided channel.

o A multiplexer is a digital circuit that receives digital inputs at any instance from

multiple channels and sends data output only from a specific channel at a

instance.

Bus: It consists of a common set of lines to connect multiple devices, hardware units

and systems for communication between any two of these at any given instance.

The bus protocol specifies how signals communicate on the bus. It specifies the

following:

o Ways of arbitration.

o Ways of polling.

o Ways of daisy chaining.

DAC USING A PWM AND AN ADC

Digital to Analog Converter (DAC) is a circuit that converts digital 8 or 10 or 12 bits to

the analog output. The analog output is with respect to the reference voltage.

o When all input bits are 1, analog output is the difference between the positive

and negative pin voltages.

o When all input bits are 0, analog output is the negative pin voltage.

o A Pulse Width Modulator (PWM) with integrator circuit is used for the DAC. It

operates as follows: pulse is made proportional to the analog output needed.

o Analog output V=K pw, where K is a constant, pw is pulse width.



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Analog to Digital Conveter (ADC) is a circuit that converts the analog input to digital 4,

8, 10 or 12 bits. The input is applied between the positive and negative pins and is

converted with respect to the reference voltage.

o Input from sensors, pressure, heart beats.

o The output bits may be transferred to memory address, a serial port or a parallel

port.

o The processor may process the converted bits and generate a Pulse Code

Modulated (PCM) output. PCM signals are used to digitize voice into digital

format.

o Problem: A 10 bit ADC with reference voltages V+ref=5V and V-ref=-5V. Find the

output when the input voltage is 5.12V.

Solution: Formula: N= v.(V+ref – V-ref)/2n.

N= 5.12 * (5-(-5))/210

= 0.05

Converting it into binary form.

0.05*2=0.1 bit=0

0.1*2=0.2 bit=0

0.2*2=0.4 bit=0

0.4*2=0.8 bit=0

0.8*2=1.6 bit=1

0.6*2=1.2 bit=1

0.2*2=0.4 bit-0

.

.

.

So, N= 0.0000110

LCD, LED AND TOUCHSCREEN DISPLAYS

A system requires an interfacing circuit and software to display the status or message

for a line, for multiline displays, or for flashing displays.

The LCD is a diode that absorbs or emits light and 3 to 4V ang 50 to 60 Hz voltage- pulses

with currents less than -50microA are required.



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To indicate the ON status of the system, there may be a LED that glows. The LED is a

diode that emits yellow, green, red or IR light in a remote controller. It needs current

upto 12 mA above 5 mA. It is much brighter than the LCD.

A touchscreen is an input as well as an output device, which can be used to enter a

command, a chosen menu or to give a reply. Input is by either selecting the option by

touching on the screen or by a stulus.

KEYPAD/KEYBOARD

The keypad or keyboard is an important device for getting user inputs. The system

provides the necessary interfacing and key-debouncing circuit as well as the software

for the system to receive input from a set of keys, from a keyboard, keypad or virtual

keypad.

PULSE DIALER, MODEM AND TRANSCEIVER

For user connectivity through the telephone line, wireless or a network, a system

provides the necessary interfacing and circuits. It also provides the software for pulse

dialing through the telephone line, for modem interconnection for fax, for internet

packages routing and for transmitting and connecting to a wireless cellular system or

personal area wireless network.

INTERRUPT HANDLER

An interrupt handling mechanism must exist in each system to handle interrupts from

various processes and for handling multiple interrupts simultaneously pending for

service.

o There can be a number of interrupt sources and groups of interrupt sources in a

processor. It may be a hardware signal indicating occurance of an event. Also

through timers, instruction in a program, error during processing.

o The system may prioritize sources and service them accordingly.

o Certain interrupts are unmaskable and cannot be disabled.

o The processor’s current program has to divert to service routine to complete the

task on the occurance of the interrupt.



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o There is a programmable unit on chip for the interrupt handling mechanism in a

microcontroller.

o The OS is expected to control the handling of interrupts and running of routines

for the interrupts in a particular application.

EMBEDDED SOFTWARE IN A SYSTEM

FINAL MACHINE IMPLEMENTABLE SOFTWARE IN A SYSTEM

The instruction code and data in the final phase are placed in the ROM or flash memory

for all the tasks that are executed when the system runs. The software is called ROM

image.

The system requires bytes at each ROM address, according to the tasks being executed.

A machine implementable software file is therefore like a table having in each rows the

address and bytes. The bytes are saved at each address of the system memory. The

table has to be readied as a ROM image for the targeted hardware.



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CODING OF SOFTWARE IN MACHINE CODES

During coding in this format, the programmer defines the addresses and the

corresponding bytes or bits at each address.

Coding in machine implementable codes is done only in specific situations because it is

time consuming and the programmer must first have to understand the processor

instructions set and then memorize the instructions and their machine codes.

SOFTWARE IN PROCESSOR SPECIFIC ASSEMBLY LANGUAGE



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Assembler is a software used for developing codes in assembly which is useful for

configuring physical devices like ports, a line display interface, ADC and DAC and reading

into or transmitting from a buffer.

The process of converting an assembly language program into machine implementable

software file and then finally obtaining a ROM image file is in fig below.

o An assembler translates the assembly software into the machine codes using a

step called assembling.

o The next step is linking. A linker links these codes with the other codes required.

The linked file in binary for run on a computer is commonly known as an

execultable file or simply an ‘.exe’ file.

o The loader program performs the task of reallocating the codes after finding the

physical memory address at a given instant. It is a part of OS and places codes into

memory after reading the .exe file.

o The final step of the system design process is locating these codes as a ROM

image. The codes are permanently placed oat the addresses actually available in

the ROM.

In embedded system, the next step instead of loader after linking is the use of

locator. The locator program reallocates the linked file and creates a file for a

permanent location of the codes in a standard format. The file format mey be in

the INTEL HEX file format or Motorola S-record format.

o Lastly either (i) device programmer takes ROM image as input and burns it into

the PROM or flash. (ii) at a foundry, a mask is created for the ROM of the

embedded system from the ROM image file.



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Fig 1.6

SOFTWARE IN HIGH LEVEL LANGUAGE

Fig below shows the different programming layers in a typical embedded C

software.

A compiler generates the object codes. It assembles the codes according to the

processor instruction set and other specifications. The C compiler for embedded

systems must, as a final set of compilation, use a code optimizer that optimizes

the code before linking. After compilation, the linker links the object codes with

other needed codes.



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The process of converting a C program into the file or ROM image is shown in the

block diagram below.

PROGRAM MODELS FOR SOFTWARE DESIGNING



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Diferrent models employed during design process of embedded software:

Sequential Program Model

Object Oriented program model

Control or Data flow graph or Synchronous Data Flow (SDF) graph.

Finite State Machine

Multithreaded Model

SOFTWARE FOR CONCURRENT PROCESSING AND SCHEDULING OF MULTIPLE

TASKS AND ISRs USING AN RTOS

An embedded system program is most often designed using multiple processes or

multitasks or a multithreads. The OS processes them concurrently. It can be interrupted

for running the ISRs (higher priority tasks).

An OS provides for processes, memory, devices, IOs and file system management. A file

system specifies the way it is created, named, called, used, copied, saved, deleted,

opened or closed.

OS software has scheduling functions for all the processes. Running of the tasks and ISRs

have real time constraints and deadlines. RTOS functions are highly complex.

SOFTWARE FOR DEVICE DRIVERS AND DEVICE MANAGEMENT IN AN OS

An embedded system is designed to perform multiple functions and had to control multiple

physical and virtual devices. A program can als be developed using virtual devices. Virtual

devices eg:’

File (records open, read, write, close)

Pipe (sending and receiving byte data from source to destination)

Socket (sending and receiving byte data between client and server, source and

destination).

RAM

A device for the purpose of control, handling, reading and writing actions can be consisting of

3 components:

A control register (control device actions by setting and resetting bits in device driver).

A status register (flag or bit to show device status to device driver).



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A device mechanism that controls device actions.

A device driver I a software written in high level language for opening, connecting or binding,

reading, writing and closing or controlling actions of the device.

A driver controls three functions

Initializing (activated by placing appropriate bits at the control register or word)

Calling an ISR on interrupt, setting status in status register, running ISR.

Resetting status flag after interrupt service.

A device manager software provides codes for detecting the presence of devices, for

initializing them and for testing the devices that are present.

SOFTWARE TOOLS FOR DESIGNING AN EMBEDDED SYSTEM

Editor : for writing the codes, addition, deletion, insert, appending, merging them.

Interpretor : line by line translation to machine codes.

Compiler: it creates object file.

Assembler: for translating assembly mnemonics into binary opcodes.

Cross assembler: for converting object codes or executable codes for a processor to

other codes for another processor and vice versa.

Simulator: to simulate all functions of an embedded system circuit.

Source-code engineering software: for source code comprehension, navigation,

browsing, editing, debugging, configuring and compiling.

RTOS: real time OS in an embedded system.

Stethoscope: for dynamically tracking the changes in any program variable or

parameter.

Trace scope: tracing the changes in modules and tasks with time on X axis.

Integrated development environment: this is a development software and hardware

environment consisting of simulators.

Prototyper: this simulates and does source code engineering, compiling, debugging,

browsing.

Locator: uses cross assembler output and memory allocation map. Provides locator

program output as a hex file.



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SOFTWARE TOOLS REQUIRED IN EXEMPLARY CASES

Refer table 1.3 in text

EXAMPLES OF EMBEDDED SYSTEM

Stepper motor

Washing, cooking systems

Keyboard controller

Remote of TV

Mobile phones

Robots

Chocolate vending machine

CD drive or hard disk drive controller

Mobile computer

EMBEDDED SYSTEM-ON-CHIP (SoC) AND USE OF VLSI CIRCUIT DESIGN

TECHNOLOGY

SoC is a system on a VLSI chip that has all needed analog as well as digital circuits, processors

and software, for example, single-chip mobile phone .



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A SoC may be embedded with the following components:

embedded processor GPP or ASIP core.

Single purpose processing cores or multiple processors.

A network bus protocol core.

An encryption function unit.

DCT.

Memories.

IP cores.

Programmable logic device and FPGA core.

Other logic and analog units.



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APPLICATION SPECIFIC IC (ASIC)

They are designed using VLSI tools with GPP or ASIP embedded into design. The designing is

done using the Electronic Design Automation (EDA) tool.

INTELLECUAL PROPERTY (IP) CORE

A standard source solution for synthesizing a higher-level component by configuring a core of

VLSI circuit or FPGA core available as an Intellectual Property, called (IP).

An IP may provide a

Design for adaptive filtering of a signal.

Full design for implementing Hypertext Transfer Protocol (HTTP) or File Transfer

Protocol (FTP) to transmit a web page or file on Internet.

USB port controller, Bluetooth, GPS interface, Wireless 802.11or 802.16 interfaces.

FPGA CORE WITH SINGLE OR MULTIPLE PROCESSORS

An FPGA consists of a large number of programmable gates on a VLSI chip. There is a set

of gates in each FPGA cell, called 'macro cell'.

Embedded system designed with a view of offering enhancing functionalities in future,

then FPGA core can be used in the circuits.

Each cell has several inputs and outputs. All cells interconnect like an array (matrix).

Each interconnection is programmable through the associated memory RAM in a FPGA

programming tool.

COMPLEX SYSTEMS DESIGN AND PROCESSORS

EMBEDDING A MICROPROCESSOR



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EMBEDDING A MICROCONTROLLER

EMBEDDING A DSP

A digital signal processor is a processor core or chip for the application that process digital

signals.



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EMBEDDING A RISK

It provides the speedy processing of instructions, each in a single clock cycle. This facilitates

pipelining and superscalar processing.

EMBEDDING AN ASIP

It is a processor with an instruction set designed for specific application areas on a VLSI chip or

core. Eg: microcontroller, DSP, IO, media.

EMBEDDING A MULTIPROCESSOR OR DUAL CORE USING GPPs

In a embedded system, several processors or dual core processors may be needed to execute

an algorithm faster within a deadline.

Eg: in a cell phone

Dialing

Modulating and transmitting

Demodulating and receiving

SMS message display

EMBEDDED PROCESSOR/EMBEDDED MICROCONTROLLER

Embedded processor specially designed with following capabilities:

Fast context switching.

32 bit or 62 bit atomic addition and multiplication, no shared data problem in

operations with large operands.



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32 bit RISK core for fast, more precise and intensive calculations by the embedded

software.

Table 1.7 for application, advantage, disadvantage.

GPP, Microcontroller, DSP, SPP and ASIP, Dual core processor, Accelerator.

EMBEDDING ARM PROCESSOR

An example of GPP. The core of these processors can be embedded onto a VLSI chip or an SoC.

It provides CISC functionality with RISK architecture at the core.

EMBEDDING ASSP

It is used as an additional processing unit for running application specific tasks in place of

processing using embedded software.

Eg; in set-up boxes, DVD players.

DESIGN PROCESS IN EMBEDDED SYSTEM

The concepts used during design process are as follows:

1. Abstraction: each problem component is first abstracted. Eg: terms of control of arms

and motors in a robot.

2. Hardware and software architecture: architecture should be well understood before a

design.

3. Extra functional properties: other functionalities required also should be well

understood from the design.

4. System related family of designs: family of related systems developed earlier should be

taken into consideration during designing.

5. Modular design: decomposition of software into modules . should ensure effective :

functional independence, cohesion, coupling.

6. Mapping: mapping into various representations is done from software requirements.

7. User interface design: it is designed as per user requirements.



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8. Refinements: till each component becomes most appropriate for implementation by the

software team.

DESIGN METRICS

Power dissipation

Performance

Process deadlines

User interfaces

Size

Engineering cost



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Manufacturing cost

Flexibility

Prototype

Development time

Time to market

System and user safety

Maintenance.

ABSTRACTION OF STEPS IN THE DESIGN PROCESS

A design process bottom-to-top design if it builds starting from the components.

A design process top-to-down design if it first starts with abstraction of the process and

then after abstraction the details are created. Top-to-down design approach is most

favoured approach .

o Requirements

o Specifications

o Architecture

o Components

o System integration

CHALLENGES IN EMBEDDED SYSTEM DESIGN: OPTIMIZING DESIGN METRICS

Amount and type of hardware needed: optimizing the requirements of the components

of the system on the basis of performance, power dissipation, cost and other design

metrics.

Optimizing power dissipation and consumption: power consumption during the

operational and idle state of the system should be optimal.

Clock rate reduction: on reducing the clock rate, the computations willtake longer time.

Voltage reduction: a CMOS circuit reduces power dissipation by one sixth.

Wait, stop and cache disable instructions: an embedded system might need to run

continuously, without being switched off; the system design is therefore constrained to

limit power dissipation while it is ON but in idle state. One way to reduce power



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dissipation is by wait and stop instructions. Cache disable is to disable certain structural

units of the processor.

Process deadlines: meeting the deadline of all the processes in the system.

Flexibility and upgrade ability: while keeping the cost minimum.

Reliability: testing is to find errors, verification to ensure if the functions are correctly

implemented. Validation to ensure that the system being created is as per the

requirements.



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UNIT 2

INTRODUCTION TO EMBEDDED SYSTEMS (CONT.)

FORMALIZATION OF SYSTEM DESIGN

It is done using a top down approach by abstraction and by:

Detailing requirements and specifications of hardware and software.

Defining architecture of hardware and software.

Coding and implementation as per the architecture.

Testing, validation, verification of system.

A diagrammatic model like UML clears design concepts.

DESIGN PROCESS AND DESIGN EXAMPLES

AUTOMATIC CHOCOLATE VENDING MACHINE (AVCM)



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• Coin insertion slot.

• Keypad on the top of the machine.

• LCD display unit on the top of the machine. It displays menus, text entered into the

ACVM and pictograms, welcome, thank and other messages.

• Graphic interactions with the machine.

• Displays time and date.

• Delivery slot so that child can collect the chocolate and coins, if refunded.

• Internet connection port so that owner can know status of the ACVM sales from

remote.

HARDWARE UNITS:

• Microcontroller or ASIP (Application Specific Instruction Set Processor)

• RAM for storing temporary variables and stack

• ROM for application codes and RTOS codes for scheduling the tasks

• Flash memory for storing user preferences, contact data, user address, user date of

birth, user identification code, answers of FAQs

• Timer and Interrupt controller

• A TCP/IP port (Internet broadband connection) to the ACVM for remote control and for

getting ACVM status reports by owner.

• ACVM specific hardware

• Power supply .

SOFTWARE UNITS:

• Keypad input read

• Display

• Read coins

• Deliver chocolate

• TCP/IP stack processing



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• TCP/IP stack communication

SMART CARD

• Smart card– a plastic card in ISO standard dimensions, 85.60 mm x 53.98 x 0.80 mm.

• Embedded system on a card.

• SoC (System-On-Chip).

• ISO recommended standards are ISO7816 (1 to 4) for host-machine contact based cards

and ISO14443 (Part A or B) for the contact-less cards.

• Silicon chip is just a few mm in size and is concealed in-between the layers. Its very

small size protects the card from bending



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HARDWARE COMPONENTS:


• RAM for temporary variables and stack


• EEPROM for storing user data, user address, user identification codes, card number and

expiry date

• Timer and Interrupt controller

• A carrier frequency ~16 MHz generating circuit and Amplitude Shifted Key (ASK)

• Interfacing circuit for the I/Os

• Charge pump

• ROM:

Fabrication key, Personalization key An utilisation lock

RTOS and application using only the logical addresses.

SOFTWARE COMPONENTS:

• Boot-up, Initialisation and OS programs

• Smart card secure file system

• Connection establishment and termination

• Communication with host

• Cryptography

• Host authentication

• Card authentication

• Addition parameters or recent new data sent by the host (for example, present balance

left)

DIGITAL CAMERA



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• 4 M pixel/6 M pixel still images, clear visual display (ClearVid) CMOS sensor, 7 cm wide

LCD photo display screen, enhanced imaging processor, double anti blur solution and

high-speed processing engine, 10X optical and 20X digital zooms

• Record high definition video-clips. It therefore has speaker microphone(s) for high

quality recorded sound.

• Audio/video Out Port for connecting to a TV/DVD player.

• Keys on the camera.

• Shutter, lens and charge coupled device (CCD) array sensors

• Good resolution photo quality LCD display unit

• Displays text such as image-title, shooting data and time and serial number. It displays

messages. It displays the GUI menu when user interacts with the camera.

• Self-timer lamp for flash.

• LCD screen to display frame view.

• Saved images display using the navigation keys.

• Frame light falls on the CCD array, which through an ADC transmits the bits for each

pixel in each row in the frame and for the dark area pixels in each row for offset

correction in CCD signaled light intensities for each row.

• The CCD bits of each pixel in each row and column are offset corrected by CCD signal

processor (CCDSP).

HARDWARE UNITS:



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• Multiple processors (CCDSP, DSP, Pixel Processor and others)



• Timer, Flash memory for storing user preferences, contact data, user address, user date

of birth, user identification code, ADC, DAC and Interrupt controller

• The DAC gets the input from pixel processor, which gets the inputs from JPEG file for the

saved images and also gets input directly from the CCDSP through pixel processor or the

frame in present view

• USB controller Direct Memory Access controller

• LCD controller

• Battery and external charging circuit

SOFTWARE UNITS:

• CCD signal processing for off-set correction

• JPEG coding

• JPEG decoding

• Pixel processing before display

• Memory and file systems

• Light, flash and display device drivers

• LCD, USB and Bluetooth Port device- drivers for port operations for display, printer and

computer communication control

MOBILE PHONE

HARDWARE UNITS:

• Microcontroller or ASIP (Application Specific Instruction Set Processor) to process

encoding and deciphering and another ASIP for voice compression.

• ASIC for the actions of dialing, modulating, demodulating, interfacing the key board

interfacing and multiple line LCD matrix displays, stores data input and recalls data from

memory.

• DSP core, CCDSP, DSP, video, voice and Pixel Processors



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• Flash, EEPROMs and SRAMs,

• Peripheral circuits, ADC, DAC and Interrupt controller

• Direct Memory Access controller

• LCD controller

• Battery

SOFTWARE COMPONENTS:

• OS– Windows Mobile, Palm OS, or Symbian, BREW

• Java 2 Micro Edition (J2ME) along with KVM as a Java Virtual Machine

• (Java Wireless toolkit with JDK (Java Development kit)

• Mobile browser for access the Web

• Downloader for Java games, ring-tones, games, wall papers

• Simple camera with Bluetooth synchronisation, IrDA and WAP connections support

• Bluetooth.

MOBILE COMPUTER

• OS (Windows CE, Windows Mobile, PocketPC, Palm or Symbian

• Touch screen GUIs, Memory and file systems

• Memory stick

• Outlook, Internet explorer, PocketWord, PocketExcel, PocketPowerPoint, hand written

text processor

• Applications or Enterprise software

A SET OF ROBOTS



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MASTER ROBOT FUNCTIONS:

• It commands receives from a remote controller commands to start the music, stop the

music and the code for the specific orchestra to be played.

• It sends the PWM signals to the ports for the moving the sticks in both hands as per the

program.

• It establishes and binds the sockets (the virtual devices) connection with the slaves. It

sends the signals through sockets using IrDA protocols. The byte streams response to

the clients are as per the music file being played .

SLAVE ROBOT FUNCTIONS:

• It establishes and binds the sockets (the virtual devices) connection with the master.

• It receives from a master socket the commands accept ( ) and write ( ) from the master.

It receives commands from master to start the music, stop the music and the code for

the specific orchestra to be played.

• It receives the signals through sockets using IrDA protocols. The byte streams from the

server re as per the music file being played.

• Slave robots speaker outputs for playing the music.

HARDWARE UNITS:




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• Music file processor


• ROM for application codes and RTOS codes for scheduling the robot actions and tasks

• Timer, Flash memory for storing user preferences and music files.

• IrDA controller (Section 3.10.3)

• Direct Memory Access controller (Section 4.8)

• Power supply source or battery

SOFTWARE UNITS:

• Socket functions

• Music coding

• Music decoding

• Memory and file systems

• Light, flash and display device drivers

• IrDA and socket Port device drivers

• Motor drivers

• IO Interrupt Service routines

CLASSIFICATION OF EMBEDDED SYSTEM

SMALL SCALE EMBEDDED SYSTEM

o Designed with a single 8- or 16-bit microcontroller;

o Little hardware and software complexities and involve board-level design.

o C or Java used for developing

o Software fits within the memory available and keep in view the need to limit

power dissipation when system is running continuously

MEDIUM SCALE EMBEDDED SYSTEM

o Designed with a single or few 16- or 32-bit microcontrollers or DSPs or Reduced

Instruction Set Computers (RISCs).

o Employs the readily available single purpose processors.

o Employ the readily available IPs for the various functions like bus interfacing.

o Both hardware and software complexities.



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o Programming tools: C/C++/Visual C++/Java, RTOS, and Source code engineering

tool, Simulator, Debugger.

SOPHISTICATED EMBEDDED SYSTEM

o Enormous hardware and software complexities and may need scalable processors

or configurable processors and programmable logic arrays.

o Used for cutting edge applications.

o Constrained by the processing speeds available in their hardware units.

o Certain software functions such as encryption and deciphering algorithms, DCT

and IDCT algorithms, TCP/IP protocol stacking and network driver functions

implemented in the hardware to obtain additional speeds.

o Software implements some of the functions of the hardware resources in the

system.

o Development tools for these systems may not be readily available at a reasonable

cost or may not be available at all.

SKILLS REQUIRED FOR AN EMBEDDED SYSTEM DESIGNER

SKILLS FOR SMALL SCALE EMBEDDED SYSTEM DESIGNER

• Full understanding of a microcontroller with a basic knowledge of computer

architecture, digital electronic design, software engineering, data communication,

control engineering, motors and actuators, sensors and measurements, analog

electronic design and IC design and manufacture.

• Computer architecture and organization.

• Interfacing the memories.

• Burning the executable machine codes in PROM or ROM.

• Use of decoders and demultiplexers.

• Use of Direct memory accesses.

• Use of Ports and device-drivers.

• Device drivers in assembly.

• Simple and sophisticated buses.

• Timers.

• Interrupt servicing mechanism.

• C programming elements.



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• Memory optimization.

• Selection of hardware and microcontroller.

• Use of ICE (In-Circuit-Emulators), cross-assemblers and testing equipment.

• Debugging

SKILLS FOR MEDIUM SCALE EMBEDDED SYSTEM DESIGNER

• C/C++/Java programming and RTOS programming and program modeling skills

• Programming the Tasks or threads and their scheduling by RTOS.

• Programming priorities and Cooperative and preemptive scheduling.

• Use of Inter processor communication functions.

• Use of shared data, and programming the critical sections and re-entrant

functions.

• Use of semaphores, mailboxes, queues, sockets and pipes.

• Handling of interrupt-latencies and meeting task deadlines.

• Use of various RTOS functions.

• Use of physical and virtual device drivers.

SKILLS FOR SOPHISTICATED EMBEDDED SYSTEM DESIGNER

• Team is needed to co-design and solve the high level complexities of the

hardware and software design.

• An embedded system hardware engineer should have full skills in hardware units

and basic knowledge of C/C++ and Java, RTOS and other programming tools.

• Software engineer should have basic knowledge in hardware and a thorough

knowledge of C, RTOS and other programming tools.

DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK

IO TYPES AND EXAMPLES

Port is a device used to send the bytes to external peripheral or device or processor using

instructions executed on processor.



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A serial port is a port for serial communication.the bits are transmitted at periodic intervals

generated by a clock.

A parallel port is a port for parallel communication. Multiple bits can communicate over a set

of parallel lines at any given instance.

Serial and parallel ports of IO devices can be classified into following IO types:

1. Synchronous Serial Input

2. Synchronous Serial Output

3. Asynchronous Serial UART input

4. Asynchronous Serial UART output

5. Parallel port one bit input

6. Parallel port one bit output

7. Parallel port input

8. Parallel port output.

SYNCHRONOUS SERIAL INPUT

Each bit in each byte and each received byte is in synchronization.

The bytes are received at constant rates. Each byte at input port separates by 8T and

data transfer rate for the serial line bits is (1/T) bps. [1bps = 1 bit per s].

The sender along with the serial bits also sends the clock pulses SCLK.

The receiver detects clock pulses and receives data bits after decoding or demodulating.

Synchronous serial input is also called master output slave input (MOSI) when SCLK is

sent from sender to receiver.

Synchronous serial input is also called master input slave output (MISO) when SCLK is

sent from receiver to sender.



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Used for interprocess transfers, audio inputs.

Eg: reading from CD or Hard Disk.

SYNCHRONOUS SERIAL OUTPUT

Each bit in each byte sent in synchronization with a clock.

Bytes sent at constant rates. If clock period = T, then data transfer rate is (1/T) bps.

Sender either sends the clock pulses at SCLK pin or sends the serial data output and

clock pulse-input through same output line with clock pulses either suitably modulate or

encode the serial output bits.

Synchronous serial output is used for inter-processor transfers, audio outputs and

streaming data outputs.

Eg: writing to CD or hard disk.

SYNCHRONOUS SERIAL INPUT-OUTPUT



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Each bit in each byte is in synchronization at input and each bit in each byte is in

synchronization at output with the master clock output .

The bytes are sent or received at constant rates. If clock period = T, then data transfer

rate is (1/T) bps.

ASYNCHRONOUS SERIAL INPUT

Each Receive Data (RxD) bit is received in each byte at fixed intervals but

each received byte is not in synchronization.

Bytes separate by the variable intervals or phase differences.

Asynchronous serial input is used for keypad inputs and modem inputs in

computers. Eg: keypad controller serial data-in,mice.

Also called UART (universal receiver and transmitter) input when according

to UART mode.



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FORMAT OF BITS AT UART PROTOCOL

ASYNCHRONOUS SERIAL OUTPUT

Refer above fig.

Each Transmit Data (TxD) bit in each byte transmit at fixed intervals but each output

byte is not in synchronization (separates by a variable interval or phase difference).

Minimum separation is 1 stop bit interval

Does not send the clock pulses along with the bits.

Sender transmits the bytes at the minimum intervals of nT.

Also called UART output if serial output is according to UART protocol.

It is used for output from modem, output for printer.

PARALLEL PORT

It can have one or multipoint input or output and can be multidirectional IO.

One bit input, output and IO.

Eight or more bit input, output and IO.

HALF DUPLEX AND FULL DUPLEX

Half duplex means at any point communication can only be one way (input or output)

on a bi-directional line. Eg: telephone communication.

Full duplex means that at an instant, the communication can be both ways. Eg: modem.



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SERIAL COMMUNICATION DEVICES

SYNCHRONOUS, ISO-SYNCHRONOUS AND ASYNCHRONOUS COMMUNICATIONS

FROM SERIAL DEVICES

SYNCHRONOUS COMMUNICATION:

o When a byte or frame of data is received or transmitted at constant time intervals

with uniform phase differences, the communication is called sysnchronous.

o Bits of data frame are sent in a fixed maximum time interval.

o Eg: frames sent over the LAN, inter processor communication in a multiprocessor

system.

o Two characteristics:

Bytes or frames maintain a constant phase difference.

To serially transmit the bits of all bytes there must be a clock which ticks at a

constant rate.

ISO-SYNCHRONOUS : is a special case when the max time interval can be varied which is

fixed in synchronous communication.



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ASYNCHRONOUS COMMUNICATION :

When a byte or frame of data is received or transmitted at variable time intervals,

it is called asynchronous.

Eg: voice data over a telephone line, RS232C.

Two characteristics:

Bytes need not maintain a constant phase difference.

Even though the clock must tick at a certain rate to transmit bits of a single

byte serially, clock is implicit to the receiver ie, clock pulse is not

transmitted.

RS232C/RS485 COMMUNICATION

RS232C : communication is between DTE (Computer) COM (communication) port and

DCE (modem) port. DTE: Data Terminal Equipment. DCE: Data Communication

Equipment. RS232C is an interfacing signal between DTE and DCE.

RS485: now called as EIA-

485. It is a protocol for physical layer in

case of two wire full or half duplex

serial connection between

multiple points.

UART

The fig below shows the handshaking

signals os RS232C port and UART serial bits

in the output to a serial line device.

The UART mode is as follows:

A line is in non return to zero (NRZ) state.

The start of serial bits is signaled by 1->0 transition.

When sending a byte, the format is :

o Start bit, 8 data bits, option programmable bit (P bit), stop bit.

The data bits in certain specific cases can be 5 or 6 or 7 instead of 8.



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The stop bit can be for a minimum interval of 1.5 ΔT or 2 ΔT instead of ΔT in some cases.

Optional P bit can be used for parity detection.

HDLC PROTOCOL

High Level Data Link Control (HDLC) is an International Standard Protocol for a data link

network.

Used for linking data from point to point and between multiple points.

Used in telecommunication and computer networks.

It is bit oriented protocol.

Full duplex communication.

SERIAL DATA COMMUNICATION USING THE SPI, SCI AND SI PORTS

SYNCHRONOUS PERIPHERAL INTERFACE (SPI) PORT

Full-duplex Synchronous communication.

SCLK, MOSI and MISO signals for serial clock from master, output from master and input

to master, respectively.

Device selection as master or slave can be done by a signal to hardware input SS. (Slave

select when 0) pin



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Programmable for defining the instance of the occurrence of -ve negative edges and +ve

positive edges within an interval of bits at serial data out or in.

Programmable for the clock bits, and therefore of the period T of serial out data bits.

SPI PORT SIGNALS

SPI PORT PROGRAMMABLE FEATURES

SERIAL CONNECT INTERFACE (SCI) PORT



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Fig shows an SCI port programmable features and DDR port bits in 68HC11/12.

SCI is a UART asynchronous mode port.

Full duplex mode.

Baud rate is selectable among 32 possible ones by the three- rate bits and two

prescaling bits.

SCI receiver wake up feature programmable by RWU (Receiver wakeup Unavailable bit). If RWU if set, then the receiver of a slave does not interrupt by the succeeding frames.

SERIAL INTERFACE (SI) PORT

Fig below shows an SI port.

It also functions as USRT (universal synchronous receiver and transmitter). SI

is therefore synchronous- asynchronous serial communication port called

USART (universal synchronous-asynchronous receiver and transmitter) port.

It is internal serial IO device in 8085.

SI operates as one of the 2 ways:

o Mode 0 Half- duplex synchronous mode of operation.



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o Mode 1 or 2 or 3 Full- duplex asynchronous serial communication. Modes 1 and

3 baud rate programmed Using the timer bits.

SECURE DIGITAL INPUT OUTPUT (SDIO)

SD an association of over 700 companies started from 3 companies in 1999.

Created a new flash memory card format, called SD format for IOs.

SDIO card has become popular feature in handheld mobile devices, PDAs, digital

cameras and embedded systems.

A processing element functions used SDIO host controller to process the IOs.

Controller may include SPI controller to support SPI mode for the IOs and also supports

the needed protocol functionality internally.

Functions include IOs with several protocols, for example, IrDA adapter, Ethernet

adapter, GPS or WiFi, Bluetooth, WLAN, digital camera, barcode or RFID code readers.

SDIO has 9 pins. Total 6 pins are for SPI and SD.



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PARALLEL DEVICE PORTS

Transfers number of bits over the wires in parallel.Short distances, generally within a

circuit board or IC or nearby external devices.

Advantage Number of 8 bits over the wires in parallel. High data transfer rate.

Disadvantage More number of wires. Capacitive effect in parallel wires reduces the

length up to which communication in parallel can take place. This results in noise and

cross talk being induced.

IO device interfacing-circuit with the processor and system buses and connections to

external peripherals/systems

Parallel port inputs I0 to I7 may be from a keypad controller.

Parallel port outputs O0 to O7 may be output bits to LCD display output controller.



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Bri and Bro buffers may be provided at bi-directional I/O port

Device makes a strobe request to port, STROBE after it is ready to send the byte and

System I/O port sends the acknowledgement, PORT READY.

System I/O port receives data in buffer and then issues an interrupt signal, INT to

processor to enable an ISR execution.

Device sends the message ACKNOWLEDGE when and the I/O device port ends the

BUFFER FULL signal to inform that the is buffer full.

The processor is sent the INTERRUPT REQUEST message, when the transmitting-buffer is

empty (available for next write).

When receiving-buffer is full (available for next read).

When transmitting-buffer is empty (available for next write).

CHARACTERISTICS TAKEN INTO CONSIDERATION WHEN INTERFACING A DEVICE PORT:

A device or port may have multi-byte data input buffer(s) and data output buffer(s).

Eight-byte buffer in 80196 microcontroller port can generate three interrupts, one on

receiving a byte, one on receiving the fourth byte and one on when the buffer full.

A port may be with a DDR (Data Direction Register) (for example, in 68HC11

microcontroller).

When the port connects to more than one LSTTL then an appropriate pull-up circuit will

be required for each port pin.



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Quasi bi-directional port (for example, in 80196) port limited driving capability for a

period of one or a few clock cycles and for one or a few LSTTL gates only.

There may be multiple or alternate functionality in the port pins. 80196 input port pins.

Each pin of P2 has alternative use as a multi-channel analog input facility for 8 analog

inputs.

A port may have provision for multiplexed output to connect to multiple systems or

units.

A port may have provision for demultiplexed inputs from multiple systems or units.

PARALLEL PORT INTERFACING WITH SWITCHES AND KEYPAD

A 16 keys keypad has many applications.

16 keys are divided in four columns and four rows for circuit design. four menu select

up, down, left, right keys.

In fig, 4 bits of an 8-bit input port.

One column connects to one poll line.

One key in a row connects to one sense line.

Idle state logic state = 1.

Four bits of an 8 bit input port A (A4-A7) for four menu select keys.

Other four bits of A (A0-A3)input from four common ends of four rows.

Four bits of output port C (C0-C3) output to four common ends of four columns.

Activates for polling output from port C ten times each second and sends C0-C3 = 0000

and after a wait it reads D0-D7 and A4-A7. The processing element computes the code

of the key pressed and generates status signal.

Processes the bounces when a key is pressed. This takes care of bouncing effects.

PARALLEL PORT INTERFACING WITH ENCODERS



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It is a device which measures the angular or linear position of a rotating or moving shaft.

Application in robots and industrial plants.

PARALLEL PORT INTERFACING WITH STEPPER MOTOR

A stepper motor rotates by one step angle when its four coils are given currents in a

specific sequence and that sequence is altered.

Eg: assume that currents at an instance equal +I, 0, 0, 0 in four coils X, X’, Y, Y’. The

motor rotates by one step when the currents change to 0, +1, 0, 0. The sequences at

intervals of T are changed as follows: 1000, 0100, 0010, 0001, 1000, …

PARALLEL PORT INTERFACING WITH LCD CONTROLLER



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An LCD controller has a processing element that needs three control signals as inputs

and 8 input/output bits for parallel set of 8 IO bits.

Interfaces Eight-bit parallel output port B pins PB0-PB7, which sends commands for

programming the controller and send data for display.

Three control signals IO PC0-PC2 as inputs to LCD controller.

PB0 to PB7 8 input/output bits for parallel set of 8 IO bits for commands and data.

LCD controller is sent control words and data words for initialization and programming

by setting the PB0-PB7, PC0 and PC1 outputs for each word to LCD controller.

One bit PC0 at an output port for RS (register select).

When RS is reset as 0, the PB0-PB7 communicates a control word to control register of

the LCD controller. When RS is set as 1, the PB0-PB7 communicates data to LCD

controller

One bit PC1 at an output port. Set to 1 when status register of LCD controller is read

using PB0-PB7. PC1 is reset to 0 when write into LCD controller using PB0-PB7 bits.

After setting R/W, RS and data-bits the LCD controller enables by setting 1 at E pin.

LCD controller connects to one bit PC2 at an output port for E (enable). There is an

interval depending on the LCD controller, the controller is disabled. This is because



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during this interval, the LCD controller cannot accept instructions or data through

output of other port pins.

PARALLEL PORT INTERFACING WITH TOUCHSCREEN

Touchscreen is an input device cum LCD display device. It is also interfaced through IO

port B functioning as data bus for display, control and status words to an LCD display

device controller.

It is either resistive or capacitive. On touching the touchscreen, there is a change in

resistance or capacitance which depends on the touched position.

SOPHISTICATED INTERFACING FEATURES IN DEVICE PORTS

Conditioning of the signal by noise-elimination. Example, 5V Schmitt trigger circuit

property─ On a transition from 0 to 1 occurs, if the voltage level exceeds 2/3 of 5V level,

then only then there is transition to 1. When a transition from 1 to 0 occurs, if the

voltage level lowers below 1/3 of 5V level, then only then there is there a transition to 0.

DataGate ─ a programmable ON/OFF switch for power management makes it possible

to reduce power consumption by reducing unnecessary toggling of inputs when the

device port is operated at fast speeds and not in use.

LVTTL (Low Voltage TTL) and LVCMOS (Low Voltage CMOS) gates may be used at the

device ports for 1.5 V I/O. HSTL (High Speed Trans-receiver Logic) and SSTL (Stub-series

Terminated Logic) standards. HSTL for high-speed operations. SSTL when the buses are

to be isolated from relatively large stubs.

A device connects to a system bus and also to IO bus when it is networked with other

devices. Device and bus impedances during an IO should match.

An IO device may consist of multiple gigabit transceivers. Special support circuitry like

Rocker IOTM is needed for this rate.

Device for I/O may integrate a SerDes (serialization and De-serialization) subunit. SerDes

is a standard subunit at in a device where the bytes placed at 'transmit holding buffer'

serialize on transmission and once the bits are received these de-serialize.

Analog audio and video signals ─ pulse code modulated (PCM) at the sub-layer. PCS sub-

layer directly provides the codes from the analog inputs within the device itself. The

codes then saved in the device data buffers. Advantage of an in-built PCS ─ No need of

external PCM coding, in background operations, fast coding.



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Unit for connecting direct inputs and outputs of voice, music, video and images. In-built

PMA─ the device directly connects to the physical media. PMA is needed for real- time

processing of video and audio inputs at the device.



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UNIT 3

DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK (CONT.)

WIRELESS DEVICES

For serial transmission of bits.

They use infrared (IR) or radio frequencies after suitable modulation of data bits. IrDA,

Bluetooth, WiFi, 802.11 WLAN and ZigBee are the famous protocols.

An IR source communicates over a line of sight and the receiver phototransistor is used

for detecting IR rays. Eg: TV remote.

Radio frequencies communicate over short and long distances.

The number of frequency bands is limited, while a large number of devices may need to

communicate. So, time and frequency division multiplexing is used. Another method is

to use radio frequency hopping over a wider spectrum.

Several wireless devices network use FHSS or DHSS transmitters and receivers.

TIMER AND COUNTING DEVICES

TIMING DEVICE

It counts the regular interval (ΔT) clock pulses at its input.

The counts are stored and incremented at each pulse.

Time= counts * (ΔT)

Time interval between two instances when the present count bits are read and the

initial counts are read is given by initial count * (ΔT).

It has a input pin which can be reset. Als a output pin, when all bits are zero for timeout

or overflow.

COUNTING DEVICE



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Counts the input for events that may occur at irregular or regular intervals.

BLIND COUNTING SYNCHRONIZATION:

A counting device may be free running with a prescalar.

Prescalar for the clock input pulses, for comparing count with the ones loaded in the

compare register and for capturing counts in an input event. It can be programmed as

p=1,2,4,8,16,32,…

The counter overflows at p*2n*ΔT interval.

This device is useful for the alarm or processor interrupts at preset instances or after preset

intervals with respect to another event from another source.

The counting device it is also useful for action or initiating a chain of actions.

TIMER CUM COUNTING DEVICE

It is a counting device with two functions:

o It counts the input due to the events at irregular instances.

o It counts the clock input pulses at regular intervals.

An input or a status bit in the timing device register controls the mode as timer or counter.

The counts gives the number of input events or pulses since it was last read. It has output

pin to indicate overflow.

Fig below shows hardware timer control bits and status flags.

Control bits can be of 9 types: timer enable, timer start, timer stop, prescaling bits, up count

enable, down count enable, load enable, timer interrupt enable, time out enable.



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USES OF TIMER DEVICE

Real Time Clock Ticks [once the system starts, it does not stop and can't be reset and its

count value can't be reloaded] Real Time Clock is set for ticks using prescaling bits in

appropriate control registers.

Initiating an event after a preset delay time.

Initiating an event (or a pair of events or a chain of events) after a comparison(s) with

between the pre-set time(s) with counted value(s). A preset time is loaded in a Compare

Register.

Capturing the count value at the timer on an event. The information of time is thus stored

at the capture register.

Finding the time interval between two events.

Wait for a message from a queue or mailbox or semaphore for a preset time when using

RTOS.

Watchdog timer.

Baud or Bit Rate Control for serial communication on a line or network.

Input pulse counting when using a timer, which is ticked by giving non-periodic inputs

instead of the clock inputs. The timer acts as a counter if, in place of clock inputs, the inputs

are given to the timer for each instance to be counted.

Scheduling of various tasks.

Time slicing of various tasks. For a multitasking or multi-programmed operating system.



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Time division multiplexing (TDM)

Timer device used for multiplexing the input from a number of channels.

STATES IN A TIMER

Reset State (initial count = 0)

Initial Load State (initial count loaded)

Present State (counting or idle or before start or after overflow or overrun)

Overflow State (count received to make count = 0 after reaching the maximum count)

Overrun State (several counts received after reaching the overflow state)

Running (Active) or Stop (Blocked) state

Finished (Done) state (stopped after a preset time interval or timeout)

Reset enabled/disabled State (enabled resetting of count = 0 by an input)

Load enabled/disabled State (reset count = initial count after the timeout)

Auto Re-Load enabled/disabled State (enabled count = initial count after the timeout)

Service Routine Execution enable/disable State (enabled after timeout or overflow).

TEN FORMS OF TIMER

Hardware internal timer

Software timer

User software controlled hardware timer

RTOS controlled hardware timer

Timer with periodic time out events

One shot timer

Up count action timer

Down count action timer

Timer with its overflow status bit

Timer with overflow flag.

WATCHDOG TIMER

A timing device such that it is set for a preset time interval and an event must occur during

that interval else the device will generate the timeout signal on failure to get that event in

the watched time interval.



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Timeout may result in processor start a service routine or start from beginning.

An application in mobile phone is that display is off in case no GUI interaction takes place

within a watched time interval.

This saves power.

A software task can also be programmed as a watchdog timer

Microcontroller may also provide for a watchdog timer.

REAL TIME CLOCK

RTC provides system clock.

It generates system interrupts at preset intervals. An ISR executes on each tick.

This timing device once started is generally never reset or never reloaded to another value.

NETWORKED EMBEDDED SYSTEMS

IO devices may be connected to others using specific interfaces.

Bus communication simplifies the number of connections and provides a common protocol

for interconnecting different or same type of IO devices.

IO buses are very flexible, system support to many different IO devices, also allows users to

change the IO devices which are attached.



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Disadvantage of IO bus: each bus has fixed bandwidth that must be shared by all devices

connected to the bus.

IO bus communicate with the processor through the IO bus. The following IO buses, each

functioning according to specific protocols.

o Using a serial bus, allows a computer or controller or embedded system to interface

network with a wide range of IO devices without having to implement a specific

interface for each IO device. All communicate through a common serial bus.

o Using a parallel IO bus, allows a comuter or controller or embedded system to

interface with a number of internal systems at a very short distances without having

to implement a specific interface for each IO device.

o Using the internet or intranet, a computer or controller or embedded system’s IO

device can interface globally and can network with other systems or computers and a

wide range of devices in the distributed systems.

o Using a wireless protocol, allows a handheld computer or controller or embedded

system IO device to interface and network with a number of handheld system IO

device at short distances up to 100m using a wireless personal area network (WPAN)

protocol, without having to implement a specific wireless interface to each IO device.

SERIAL BUS COMMUNICATION PROTOCOLS

I2C BUS

Assume that there are number of device circuits in a number of processes in a plant, one IC

each for measuring temperatures and pressures. These ICs mutually network through a

common synchronous serial bus. I2C (Inter IC connect ) bus is a popular bus for these

circuits.

There are three I2C bus standards: o Industrial 100 kbps I2C o 100 kbps SM I2C o 400 kbps I2C

The I2C bus has two lines that carry its signals: for clock, for bidirectional data.

The fig below shows the protocol for I2C bus, the signals during the transfer of a byte.



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The fig below shows the format of the bits at the I2C bus:

o First field (1 bit): start bit

o Second field (7 bits): address field

o Third field (1 control bit): to define whether its read or write cycle

o Fourth field (1 control bit): acknowledgement (ACK)

o Fifth field (8 bits): IC device data bits

o Sixth field (1 bit): Negative ACK (NACK)

o Seventh field (1 bit): stop bit.



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Disadvantage: time taken by the algorithm in the master hardware that analyses the bits

through I2C in the case the slave hardware does not provide for the hardware that supports

it.

CAN BUS

Embedded controllers must network through a bus. CAN (controller area network) bus is a

standard bus in distributed network.

Mainly used in automotive electronics, medical electronics, industrial plant controllers.

Fig below shows a CAN bus network has a serial line, which is bi-directional. It has

multimaster and multicast features.



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Each field in a CAN frame:

o First field (12 bits): arbitration field. 11 bits destination, 1 bit RTR. Remote

transmission request (RTR)

o Second field (6 bits): control field. First bit for identifier extension, 2nd bit always 1, 4

bits are code for data length.

o Third field (0-64 bits): length depends on data length code in control field.

o Fourth field (third if there is 0 bits in third field) (16 bits): Cyclic Redundancy Check

(CRC).

o Fifth field (2 bits): ACK

o Sixth field (7 bits): end of frame bit.

USB BUS

USB is a bus between the host system and number of interconnected peripheral devices. A

maximum of 127 devices can connect to a host. Devices like flash memory cards, digital

camera, mice, pocket PC, video games.

Serial transmission and reception between host and serial devices.

A USB device can be hot plugged (attached), configured and used, reset, reconfigured and

used; it can share bandwidth with other devices, detached (while others are in operation).



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FIREWIRE-IEEE 1394 BUS STANDARD

Some devices like didital camcorders, DVD, set top boxes, printers need a high speed bus

standard interface for communicating directly to a personal computer.

FireWire can operate upto 400Mbps and the latest machines include FireWire ports that

support IEEE 1394b which operate upto 800Mbps.

A single 1394 port can interface upto 63 external FireWire devices. It supports both plug

and play and hot plugging. It also provides self plugged and bus powered support on the

bus.

ADVANCED SERIAL HIGH SPEED BUSES

IEEE 802.3-2000

IEE P802.3oe draft 4.1

IEE P802.3oe draft 4.1

XAUI

XSBI

SONET OC-48

SONET OC-192

SONET OC-768

ATM OC-12/46/192

PARALLEL BUS DEVICE PROTOCOLS- PARALLEL COMMUNICATION

NETWORK USING ISA, PCI, PCI-X AND ADVANCED BUSES

The computer system connects a high speed to other subsystems having a range of IO

devices at a very short distances (<25 cm) using a parallel bus without having to implement

a specific interface for each IO device.

A parallel bus has a large number of lines as per the protocol.



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A interconnection bus within PC or embedded system to a number of PC-based IO cards,

systems and devices. This bus needs to be separated from system bus that connects the

processor to memories. The system bus and interconnection bus operate at different

levels of speeds.

A switch, popularly called PCI bus interface, switches a processor communication with

the memory bus to PCI bus. The switch communicates with the memory through

memory bus and dedicated set of wires that transfer data between these systems. A

separate IO bus connects the switch io IO devices.

Two old interconnection buses for communication between the host and a device are ISA

and EISA (extended ISA). A new interconnection for the bus is either PCI or PCI/X.

ISA BUS

It is used in IBM standard architecture. It connects only to an embedded device that has an

8086 or 80186 or 80286 processor, and in which the processor addressing and IBM PC



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architecture addressing limitations and interrupt vector address assignments are taken into

account. There is no geographical addressing.

Limitations for memory access by a system using the ISA bus of the original IBM PC were :

o ISA bus memory accesses can be in two ranges, 640 to 1MB and 15 to 16MB.

The IO port address limitations for devices are: the 8086 to 80286 processor has IO mapped

IOs, not memory mapped IOs. Though the instruction set provides for IO instructions for

64kB IO addresses, the IBM PC configuration ignores the address lines A10 to A15 and these

are not decoded.

There is a limited availability of interrupt vectors in IBM PC 80x86 family.

ISA and EISA buses are compatible with IBM architecture. They are used for connecting

devices following IO addresses and interrupt vectors as per IBM PC architecture. EISA is 32

bit extension of ISA. It also supports software interrupt functions and Ethernet devices.

PCI AND PCI/X BUSES

Recently, the most used synchronous parallel bus in the computer system for interfacing PC-

based devices is PCI (Peripheral Component Interconnect). It provides a superior throughput

than EISA. PCI and PCI/X buses are used for parallel bus communication.

It is platform independent.

Its clock rate is nearest to the submultiple of the system clock.

PCI bus has 32 bit data bus extensible to 64 bits. Als 32 bit addresses extensible to 64 bits.



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Its protocol specifies the interaction between the different components of a computer.

Fig shows 64 bytes at standard device independent configuration registers in a PCI device or

host.

The PCI feature of automatically detecting the interfacing systems and assigning new

addresses is important for coding a device driver. The PCI bus therefore simplifies the

addition and deletion of the system pheripherals.

A device host identifies its address space by three identification numbers:

o IO port

o Memory locations

o Configuration registers

The unique feature is its configuration address space. A uniquely assigned interrupt type

handles an interrupt. Interrupt type can be between 0x00 and 0xFF.

A PCI controller must access one device at a time. A device cannot modify other

configuration registers but can access other device resources or share the work or assist

other device.

A PCI device on boot up disables its interrupt.

ARM BUS



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ARM processor interfaces the memory, external DRAM controller and on chip IO devices

which connect to 32 bit data and 32 bit address line at high speed using AMBA (ARM main

memory bus architecture)-AHB (ARM high performance bus).

ARM bus is of 2 types: AMBA-AHB and AMBA-APB. AHB connects to high speed memory.

Fig shows AMBA-AHB and AMBA-APB bridges. The bridges interface the memory APB

connects the external peripherals to the system memory bus through the bridge.

A switch, AMBA-APB bridge, switches ARM CPU communication with the AMBA bus to APB

bus. The ARM processor based microcontroller has a single data bus in AMBA-AHB that

connects to the bridge, which integrates the bridge onto the same IC as the processor to

reduce the number of chips and hence the cost.

The APB can connect the I2C, touchscreen, SDIO, MMC, USB, CAN.

ADVANCED PARALLEL HIGH SPEED BUSES

GMMI

XGMI

CSIX-1

RapidIOTM Interconnect Specification v1.1

INTERNET ENABLED SYSTEMS- NETWORK PROTOCOLS



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Embedded systems are internet enabled by using TCP/IP protocol suite protocols for

networking to internet and assigning the IP addresses to each system.

Fig shows an internet enabled embedded system communicating to other systems on the

internet. Internet enabled embedded systems use html or MIME type files.

TCP or UDP transport layer protocol, and are addressed by an IP address and use IP protocol

at network layer.

An IP address is of 32 bits or 48 bits in IPv4 or IPv6 respectively.

Network connectivity is through the layers.

There are five layers in a TCP/IP network.

o Application, transport, network, data link, physical layers.

HYPER-TEXT TRANSFER PROTOCOL (HTTP)

An application layer protocol is as per the application. This layer accepts the data, for eg, in HTML

or text format. Puts the header words as per the protocol and send the

o Header plus application layer data

to the transport layer.

1. NTP (Network Time Protocol) synchronizes system clocks on a network.

2. MIME enables attachment of multiple types of files. Eg: txt, doc, gif, jpg, wav



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3. HTTP

4. FTP (file transfer protocol), TFTP (Trivial FTP).

5. TELNET

6. SMTP (Simple Mail Transfer Protocol)

7. PoP3 enables e-mail retrieval.

8. NNTP (Network News Transfer Protocol) is used for news transfer port.

9. DNS (domain name service)

10. SNMP (simple network management protocol)

11. Bootps and Bootpc for Bootstrap protocol (DHCP) server and client, respectively.

12. DHCP (dynamic host configuration protocol) for remote booting as well as configuring a

system.

HTTP port 80 is an application layer protocol. The HTTP features are as follows:

HTTP is a standard protocol for requesting for a URL address.

HTTP is a stateless protocol.

HTTP is a file transfer like protocol for HTML files.

The HTTP protocol is very light and thus speedy as compared to other existing protocols.

Flexibility of HTTP.

HTTP protocol is based on the object oriented programming system (OOPS).

From HTTP 1.0 and 1.1 version onwards, following features have been included:

o MIME (multipurpose internet mail extension) for making feasible multimedia file

access.

o There are 8 specified methods and extension methods.

GET, POST, HEAD, CONNECT, PUT, DELETE, TRACE, OPTIONS.

o Digest Access Authentication prevents the transmission of username and password as

HTML or text.

o An error report to client when a HTTP request is without a host header field.

o An absolute URL is acceptable to the server. Earlier only proxy server accepted that.

o Status codes in the response.

o Caching of a resource is provided at server (and proxy).

o Byte range specification helps in larger response in parts.

o Selection among various characteristics on retrieval by the client is feasible when a

server sends response to client request.



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o Length specification helps in presentation in chunks.

An HTTP message header during a request from a client or during a response from server

consists of two parts : (a) A start line, none or several message- headers (fields) and empty

line (b) body of the message.

HTTP provides for entity headers.

HTTP interaction scheme is that a client requests server directly or through proxy or a

gateway. An HTTP message is therefore either request or response.

TRANSPORT CONTROL PROTOCOL (TCP)

It is a protocol used in transport layer.

o This layer accepts messages from the upper layer on transmission by application or

session layer.

o This layer also accepts a data stream from the network layer at receiving end.

o Before communicating a message to the next network layer, it may add a header. The

message may communicate in parts or segments or fragments.

o The header generally has the additional bits for source and destination addresses.

o Also bits for sequence and acknowledge, flow and error controls, etc.

There are bits for the offset, window, flags, checksum, urgent pointer, option and for

padding. TCP supports point to point networking mode.

TCP is used for a full duplex acknowledged flow. Its format has a TCP header of five plus (n-

5) words for options and padding and data of maximum 1 word. Then 1>= 214-n where n>=5.

n is data offset. If n>5,there exists words for options and padding.

TCP is virtual-connection oriented. It does not permit multicasting but point to point virtual

connection.

USER DATAGRAM PROTOCOL (UDP)

TCP/IP also supports at the transport layer a simple protocol than TCP. When a message is

connectionless and stateless, then the transport layer protocol in the TCP/IP suite is UDP.

UDP is the broadcast networking mode.

Eg: application for communicating header before a data stream.

The header specifies the bits for source and destination ports, total length of message

including header and check sum.



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INTERNET PROTOCOL (IP)

All internat enabled devices communicate using Internet Protocol (IP).

The transport layer data transmits on the network, divides into the packets at the network

layer. Each packet transmits through a chain of routers on the internet.

A packet is minimum unit of data that transmits on the internet through routers. It consists

of IP header plus data or IP header plus routing protocol along with the routing messages.

The packet has a maximum of 216 bytes.

Various fields at IPV4 header:

o Version

o Precedence

o Service

o QoS (quality of service)

o Fragment ID

o Flags

o Checksum

o Time-to-live

o Protocol type

o Header length

o Source and destination addresses options

ETHERNET

At present, about one third of the LANs in the world are the Ethernet LANs.

In each frame, there is a header like in a packet.

In Ethernet LAN standard is IEEE 802.2 (ISO 8802.2).

It is a protocol for local network of computers, workstations and devices.

Data for transmission fragments into frames. Each frame has a header. The format is:

o Preamble (8 bytes) : indicates start and is used for synchronization.

o Destination address (6 bytes)

o Source address (6 bytes)

o Type field (6 bytes)

o A minimum of 72 bytes and maximum of 1500 bytes of data.

o CRC (4 bytes).



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Features:

o Topology and transmission mode: bus

o Speed: 10Mbps, 100Mbps

o Broadcast medium: passive. Wired connection based, frame format like the IEEE

802.3

o SNMP (Simple Network Management Protocol)

o System: open

o Operation: each one connected to a common communication channel in the network.

o Control: passive, connection based.

o Address Resolution Protocol (ARP)

o Connectivity to internet and intranet.

WIRELESS AND MOBILE SYSTEM PROTOCOLS

INFRARED DATA ASSOCIATION (IrDA)

IR is electromagnetic radiation of wavelength greater than visible red length.

IrDA recommends a protocol suite as standard. It supports data transfer rates upto 4Mbps.

There should be no obstructions or wall in between the source and receiver.

Fig shows a handheld device connected to other computer using IrDA protocol.

IrDA supports 5 levels of communication.

o Level 1 is minimum required communication.

o Level 2 is access based communication.

o Level 3 is index based communication.

o Level 4 is synchronized communication.

o Level 5 is SyncML (synchronized markup language) based communication.

IrDA is used in mobile phones, digital cameras, keyboard, mouse, printers.

It supports several protocols at three layers.



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o Lower layer is physical layer 1.0 or 1.1

o Intermediate layer is data link layer. It specifies IrLMP (IR link management protocol).

o An IrDA upper layer protocol is Tiny TP (transport protocol). Another upper layer

protocol is IrLMIAS (IR link management information access service protocol).

IrDA protocol overhead is between 2% to 50% of Bluetooth device overhead.

BLUETOOTH

Fig shows a handheld device connected to other computers through wireless protocol using

Bluetooth.

Bluetooth is an IEEE standard 802.15.1 protocol. The physical layer radio communicates at

carrier frequencies in 2.4 GHz band with FHSS (frequency hopping spread spectrum)

It supports range upto 10m low power and upto 100m high power. Range depends on radio

interface at physical layer.

Bluetooth 2.0 has enhanced maximum data rate of 3.0 Mbps over 100m.

It discovers nearby devices (<10m) and they synchronize and form a WPAN (wireless

personal area network).

Bluetooth protocol supports power control so that the device communicate at minimum

required power level.

The physical layer has three sublayers: radio, baseband, link manager or host controller

interface.

There are two types of links: best effort traffic links and real time voice traffic links. Real

time traffic uses reserved bandwidth.

The link manager sublayer manages the master and slave link.



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o It specifies data encryption and device authentication handling, and formation of

device pairs for Bluetooth communication.

o It gives specifications for state transmission mode, supervision, synchronization,

packet flow latency etc.

The Host Controller Interface (HCI) interface is a hardware abstraction layer. It is used in

place of link manager sublayer.

Blutooth communication latency is 3s.

Features:

o Provision of encrypted secure communication

o self discovery

o self organization

o radio based communication between tiny antennae.

802.11

Wireless LAN uses IEEE standards 802.11a to 802.11g. Data transfer rates are 1 and 2 Mbps.

The 802.11b is called WiFi.

802.11b supports data rates of 5.5 Mbps by mapping 4 bits and 11 Mbps mapping 8 bits

simultaneously during modulation.

A given set of the LAN station access points network together and the set is called extended

service set (ESS). It supports fixed infrastructure network.

Two types of wireless service sets;

o Basic Service Set (BSS): one service set has one wireless station, which communicates

to an access point, also called hotspot. The service set is BSS.

o The other service set has several stations. It is called Independent BSS (IBSS).

802.11 provides specifications for physical layer and data link layers.

The data link layer specifies a MAC layer. The MAC layer uses CSMA/CA protocol. The RTS

packet is sent first. If the other end responses by the packet call CTS, then the data is

transmitted.

ZigBee

It is an IEEE standard 802.15.4 protocol.



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The physical layer radio operates at 2.4 GHz band carrier frequencies with DSSS (direct

sequence spread spectrum). It supports a range upto 70 m. Data transfer rate supported is

250 kbps. It supports 16 channels.

The ZigBee network is self organizing and supports peer to peer and mesh networks.

Data transfer is between two devices in peer to peer or between a device and multiple

devices in the mesh network.

ZigBee protocol supports a large number of sensors, lighting devices, air conditioning,

industrial controller and other devices for home and office automation and their remote

control and formation of WPAN (wireless personal area network).

ZigBee network has a ZigBee router, end devices and coordinator.

o Router transfers packets from neighbouring source to a nearby node in the path to

destination.

o Coordinator connects one ZigBee network with another.

o End devices are transceivers of data.

Communication latency is 30ms.



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UNIT 5

PROGRAM MODELING CONCEPTS

PROGRAM MODELS

Polling for events model: there is polling in cyclic loop for the events, state variables,

messages, and signals using the switch case statements.

Sequential program model: Use of multiple function calls sequentially. Fig shows a

sequential model for AVCM. (automatic chocolate vending machine).

Data flow model: DFGs and Control DFG (CDFG)s are used for modeling the data paths

and program flows of software. A program is modeled as handling the input streams and

creating output data streams.

State machine model: a programming model is that there are different states and the

model considers a system as a machine, which is producing the states.



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Concurrent processes and interprocess communication model: A programming model is

that there are several concurrent tasks (or processes or threads) and each task has the

sequential codes in infinite loop. A task sends a message or signal for another task. A

task, which gets a message or signal, runs and the remaining tasks remain in the blocked

state.

DFG MODELS

DATA FLOW GRAPH

A data flow means that a program flow and all program execution steps are determined

specifically only by the data. The software designer predetermines the data inputs and

designs the programming steps to generate the data output.

It doesn’t have any conditions within it so that the program has one data entry point

and one data output point. There is only one independent path for the program flow

when the program is executed.

A circle or node represents each process in DFG. An arrow directed towards the circle

represents the data input and an arrow originating from the circle represents a data

output. Data input along an input edge is considered as token. Input edge must have

atleast one token. The node is said to be fired by the tokens from all input edges.

When there is only one set of values of each inputs and and only one set of values for

each outputs for the given output, its ADFG (acrylic data flow graph).

Eg for non-acrylic data inputs: an event, a status flag setting in a device, input as per

output condition condition of the previous process.

Fig shows DFG during a DSP algorithm.



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CONTROL DFG MODEL

A control flow means that specifically only the program determines all program

execution steps and the flow of a program. The software designer programs and

predetermines these steps.

It may have loops or condition statements in between.

Data that is input generate the data output after a control data flow as per the

controlling conditions. Output(s) depends on the control statements for various

decisions in a process.

It graphically represents the conditions and the program flow along a condition

dependent path.

A circle or node represents each process in a CDFG. A directed arrow towards the circle

represents the data input (or set of inputs) and a directed arrow from the circle

represents a data output (or set of outputs).a box may represent a condition.



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SYNCHRONOUS DATA FLOW GRAPH (SDFG) MODEL

When there are a number of tokens (inputs) required for a computation to generate

more tokens (outputs) in a single firing, the data flow is said to be synchronous.

Let an arc represent a buffer in physical memory. The arc can contain one or more initial

tokens with the delays.

Vertices or circles in the graph are called actors. Actors do the computations.

An edge between the vertices represents a queue of output values from one vertex and

a queue of input values to another vertex. Edges carry the values from one actor to

another.



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Let X and Y be two sets of instructions that once fired or started, do not need any

further inputs from source during computation. Let X generate the output values a,b,c. Y

gets input values a,c,I,j and let I have a delay (dot).

The dot on the arc represents the initial token(s) in an SDFG model. The initial token

may also represent a delay. If there are more than one initial token the number of initial

tokens are mentioned on the dot.

SDFG model program translates into a sequential model program.

STATE MACHINE PROGRAMMING MODELS FOR EVENT-CONTROLLED

PROGRAM FLOW

State machine model, there are states and state transition functions, which produce the

states.

A state transition function is a function which changes a state to its next state.

FINITE STATE MACHINE (FSM) MODEL

Fig shows states of timer using finite states machine model.

FSM model states that there is finite number of possible states in a system and a system

can only exist in one of these states at an instance.

There can be transition of the present state to the next state, which depends on the

inputs and state transition function.

A set of outputs represents a state in the Moore model and a set of outputs represents

a state transition in Mealy model.



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When modeling a process as FSM, the software designer specifies the following for each

state:

o The state one of the finite number of states.

o Finite set of inputs with their values for the state.

o Finite actions

o State transition function.

Steps that model or represent the states and interstate transitions in FSM data path are

as follows:

o Transition due to an event.

o A state can receive multiple inputs from another state.

o A state can generate multiple outputs or tokens.

FSM STATE TABLE

It can be designed for representation of every state in its rows. The following columns are

made for each row.

Present state name or identification.

Action(s) at the state until some event(s).

Events which cause state transition function.

Output(s) from the state output function(s).

Next state.

Expected time interval for finishing a transition.

THE STATES, STATE TRANSITIONS AND FINITE NUMBER OF STATE TRANSITIONS

IN A KEY ‘5’ IN MOBILE PHONE T9 KEYPAD



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MODELING OF MULTIPROCESSOR SYSTEMS

MULTIPROCESSOR SYSTEMS

A large complex program can be partitioned into the tasks or sets of instructions and the

ISRs. They can be run concurrently on different processors and by some mechanism the

tasks can communicate with each other.

The problem is how to partition them, how to schedule over available processor and

resources for optimum performance.

Following are the problems in modeling the processing the instructions in a

multiprocessor system.

o Partitioning processes, instruction set, instructions.

o Concurrent processing of processes on each processor.

o Static scheduling of compiler.

o Scheduling of concurrent processing instructions in each superscalar unit and

pipeline in the processor.

o Hardware scheduling issue.

o Static scheduling issue.

o Synchronizing issues.

o Dynamic scheduling issues.

o Scheduling of the instructions.

Processors process concurrently as follows:



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o One way of concurrent processing is to schedule each task so that it is executed

on different processors and synchronize the task by some interprocessor

communication mechanism.

o Second way, when an SMID or MIMD or VLIW instruction has different data, each

task is processed on different processors for different data.

o An alternate way is that a task instruction is executed on the same processor or

different instructions of a task can be done on different processors.

MODEL OF UNFOLDING SDFGs INTO HOMOGENEOUS SDFGs

An SDFG models the delays as well as the number of inputs and outputs.

The edges directed to a circles are assumed to have a physical memory buffer and till

the buffer has the data, the computation do not fire.

When there is only one token at the input and one at the output, the SDFG is called

homogeneous SDFG (HSDFG).



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Fig (a) shows a modeling of computations by an SDFG.

Fig (b) shows an HSDFG representation after unfolding the SDFG in fig (a).

An SDFG can be unfolded into one or more HSDFGs. So it will have more number of

vertices and edges as only one token is permitted at a vertex in a HSDFG. Two vertices

can be connected by two or more edges in HSDFG.

HSDFG is used for:

o For indefinitely long sequence, SDFG based modeling and the consequently

unfolding into the HSDFG helps.

o Applied to computations of a fast fourier transform (FFT) or coding voice data.

o It can effectively model an IPC.

o A SDF model program translates number of parallel concurrent or sequential

model program using HSDFG when precedence is considered.

MODEL OF UNFOLDING HSDFGs INTO APEGs

Acrylic precedence is a precedence of vertices in a directed graph such that there are no

delays at the arcs. If initial tokens (delays) are taken off from a HSDF graph, an acrylic

precedence expansion graph (APEG) is obtained.

APEGs are important for scheduling in multiprocessor systems.

The execution is smooth along the arc with no interprocess communication time.

Simplest to schedule such that there is no precedence constraints.



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Fig © above shows a corresponding APEG.

APPLICATIONS OF THE GRAPHS TO MULTIPROCESSOR SYSTEMS:

PARTITIONING AND SCHEDULING

When there are multiple processors in parallel, the partitioning is done as follows:

There are minimum number of IPCs so that the total time of IPC delays minimized.

There is load balancing,

The performance cost minimizes.

Each task of function Executing on an assigned processor.

Each task or function executing on the different processors at the different periods .



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Instructions of Four Different Tasks Partitioned and Scheduled on Two processors.

Instructions of Four Different Tasks Partitioned and Scheduled on Two processors

differently in different periods.



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INTERPROCESS COMMUNICATION AND SYNCHRONIZATION OF PROCESS, THREADS

AND TASKS

MULTIPLE PROCESSES IN AN APPLICATION

PROCESS

It is a computational unit that processes on a CPU and whose state changes under the control

of kernel of an OS. Application program can be said to consist of a number of processes. And

each process runs under control of an OS.

A process consists of sequentially executable program and state-control by an OS.

The state during running of a process is represented by the information of process state

(created, running, blocked, finished),

process structure- data, objects, resources, PCB.

A process runs on scheduling by OS.

PROCESS CONTROL BLOCK (PCB)

Data structure having the information using which the OS controls the process state. The PCB

stores in the protected memory addresses at kernel.

It contains the following information:

Process ID

Allocated program memory address blocks in physical memory and in secondary

memory for the process codes.

Allocated process specific data address blocks.

Allocated process heap address.

Allocated process stack address.

Allocated addresses of the CPU register process state signal mask.

Signals dispatch table.

OS allocated resources.

Security restrictions and permissions.



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MULTIPLE THREADS IN AN APPLICATION

A thread is a process or subprocess within a process that has its own PC, its own SP and stack,

its own priority parameter for its scheduling by thread-scheduler.

A thread consists of sequentially executable program under state control by an OS.

The state information of a thread is represented by thread state (started, running,

blocked, finished). Thread structure- its data, objects, subset of the process resources,

thread stack.

A thread is a lightweight entity.

TASKS

Task is defined as an embedded program computational unit that runs on a CPU under the

state control of kernel of an OS. It is a term used for process in the RTOSes for embedded

systems.

A task consists of a sequentially executable program under a state control by an OS.

The state information of a task is represented by the task state (running, blocked or

finished). Task structure- its data, objects, resources, TCB.

TASK STATES

Task has state, which includes its status at a given instance in the system. It can be one of the

following state: idle, ready, running, blocked, deleted.

Task can be considered to be in one of the five states.



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Idle (created) state: task is created and memory is allocated to its structure. But its not

ready and schedulable by the kernel.

Ready (active) state: created task is ready and is schedulable by the kernel but not ready

due to some other priority task.

Running state: executing the servicing codes and getting the system resources at this

instance.

Blocked (waiting) state: executin=on the servicing codes suspends after saving the

needed parameters into its context.

Deleted (finished) state: the created task has memory de allocated to its structure. It

frees the memory.

Eg: task_send_card_info states

TASK AND DATA



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Fig shows task and its data including its context and TCB.

Each task has an ID. ID is of one byte called as the index of the task. OS assigns it a value

between 0 and 255.

Each task may have a priority parameter.

Each task has independent values for the following at an instant :

o PC (Program Counter)

o SP (Stack Pointer)

CONTEXT: Each task has a context. This reflects the CPU state just before the OS blocks one

task and initiates another task into the running state. Context continuously upgrades during

running of the task and is saved when switching to other task.

CONTEXT SWITCH: CPU control switches to other process or task only after saving the registers

and pointers. The context must retrieve on transfer of program control of the CPU back to the

running of the same task again. It happens each time the scheduler blocks one task and runs

other task.

TASK CONTROL BLOCK: each task has a TCB. TCB is a memory block. It is a data structure

having the information using which the OS controls the task state. It stores in the protected

memory area of the kernel. It stores the following information:

PC, memory map, signal dispatch table, signal mask, task ID, CPU state, kernel stack.



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TCB data structure may vary from one OS to another and is same as PCB.

CLEAR-CUT DISTINCTION BETWEEN FUNCTIONS, ISRs AND TASKS BY

THEIR CHARACTERISTICS

TASK CODING IN ENDLESS EVENT-WAITING LOOP

Each task may be coded such that it is in endless event waiting loop to start with. An event

loop is one that keeps on waiting for an event to occur. On the start event, the loop starts

from the first instruction of the loop. Execution of service codes then occur. At the end, task

returns to start event waiting loop.

DISTINCTION BETWEEN FUNCTION, ISR AND TASK

FUNCTION ISR TASK

1.USES: for running specific set of codes for performing a specific set of actions as per the arguments passed to it.

for running on an event specific set of codes for performing a specific set of actions for servicing the interrupt call.

for running codes on context switching to it by OS and the codes can be in endless loop for the event (s).

2. CALLING SOURCE: call from another function or process or thread or task.

interrupt-call for running an ISR can be from hardware or software at any instance.

A call to run the task is from the system (RTOS). RTOS can let another higher priority task execute after blocking the present one. It is the RTOS (kernel) only that controls the task scheduling.

3. CONTEXT SAVE: run by change in program counter instantaneous value. There is a stack. On the top of which the program counter value (for the code left without running) and other values (called functions’ context) save.

Each ISR is an event-driven function code. The code run by change in program counter instantaneous value. ISR has a stack for the program counter instantaneous value and other values that must save. All ISRs can have common

Each task has a distinct task stack at distinct memory block for the context (program counter instantaneous value and other CPU register values in task control block) that must save. Each task has a distinct process structure (TCB) for



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All function have a common stack in order to support the nesting.

stack in case the OS supports nesting.

it at distinct memory block.

4. RESPONSE AND SYNCHRONIZATION: nesting of one another, a hardware mechanism for sequential nested mode synchronization between the functions directly without control of scheduler or OS.

a hardware mechanism for responding to an interrupt for the interrupt source calls, according to the given OS kernel feature a synchronizing mechanism for the ISRs, and that can be nesting support by the OS.

According to the given OS kernel feature, there is a task responding and synchronizing mechanism. The kernel functions are used for task synchronisation because only the OS kernel calls a task to run at a time. When a task runs and when it blocks is fully under the control of the OS.

5.STRUCTURE: can be the subunit of a process or thread or task or ISR or subunit of another function.

Can be considered as a function, which runs on an event at the interrupting source. A pending interrupt is scheduled to run using an interrupt handling mechanism in the OS, the mechanism can be priority based scheduling. The system, during running of an ISR, can let another higher priority ISR run.

is independent and can be considered as a function, which is called to run by the OS scheduler using a context switching and task scheduling mechanism of the OS. The system, during running of a task, can let another higher priority task run. The kernel manages the tasks scheduling .

6. GLOBAL VARIABLES USE: can change the global variables. The interrupts must be disabled and after finishing use of global

When using a global variable in it, the interrupts must be disabled and after finishing use of global variable the interrupts are

When using a global variable, either the interrupts are disabled and after finishing use of global variable the interrupts are enabled or



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variable the interrupts are enabled.

enabled (analogous to case of a function).

use of the semaphores or lock functions in critical sections, which can use global variables and memory buffers.

7. POSTING AND SENDING PARAMETERS: can get the parameters and messages through the arguments passed to it or global variables the references to which are made by it. Function returns the results of the operations.

using IPC functions can send (post) the signals, tokens or messages. ISR can’t use the mutex protection of the critical sections by wait for the signals, tokens or messages.

can send (post) the signals and messages. can wait for the signals and messages using the IPC functions, can use the mutex or lock protection of the code section by wait for the token or lock at the section beginning and messages and post the token or unlock at the section end.



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UNIT 6

REAL-TIME OPERATING SYSTEMS

OS SERVICES

GOAL

Facilitating easy sharing of resources as per schedule and allocations: No processing

task or thread uses any resource until it has been allocated by the OS at a given

instance.

Facilitating easy implementation of the application program with the given system-

hardware through the system software.

Optimally scheduling the processes on one (or more CPUs if available) by providing an

appropriate context switching mechanism.

Maximizing the system performance to let different processes (or tasks or threads)

share the resources most efficiently with protection and without any security breach.

Providing management functions for the processes (tasks or threads), memory, file,

physical and virtual devices and I/Os and for other functions for which it is designed.

Providing management and organisation functions for the I/Os, devices and files and file

-like devices.

Providing interoperability of the application on different networks.

Providing a common set of interfaces that integrates various devices and applications

through standard and open systems.

Providing easy interfacing and management functions for the network protocols and

network.

Providing portability of the application on different hardware configurations.

USER AND SUPERVISORY MODE STRUCTURE



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At every clock tick of the system-clock, there is system interrupt. On each system interrupt,

the system time updates, the system context switches to the supervisory mode from user

mode. After completing the supervisory functions in the OS, the system context switches back

to user mode.

User mode:

o User process is permitted to run and use only a subset of functions and

instructions in OS. It is done by sending a message to the waiting process

associated in the OS kernel space or by system call (calling an OS function).

o The use of hardware resources including memory is not permitted without OS

making the call to the OS functions, called system call.

o That protected memory space is also called kernel space. Hence execution of user

functions calls is slower than the execution of the OS functions.

Supervisory mode:

o Also called kernel mode.

o OS runs in protected mode the privileged functions and instructions in protected

mode that are the privileged ones and the OS (more specifically, the kernel) is

only one permitted to access the hardware resources and protected area

memory.

o Kernel space functions and processes execute faster than the user space functions

and processes.

STRUCTURE:

Software Application Programming Interface (API)

System software other than the one provided at the OS

OS Interface

OS

Hardware–OS Interface

Hardware



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KERNEL

Process, memory and IO managers are essential components of a kernel. Kernel may include

file and device management functions as part of the kernel in a given OS.

KERNEL SERVICES:

o Creation to deletion of Processes

o Process structure maintenance

o Processing resource requests

o Scheduling Processes

o Inter process Communication (IPC) (communication between Tasks, ISRs, OS

functions)

o Allocation and de-allocation between Tasks, ISRs, OS functions

o File Management

o Device Management,

o Device Drivers

o I/O Management

o Interrupts Control (by handling ISR) Mechanism

PROCESS MANAGEMENT

PROCESS CREATION

Means defining the resources for the process and address spaces (memory blocks) for the

created process, its stack, its data and its heap and placing the process initial information at a

PCB.

At the reset of the processor in a computer system, an OS is initialized first─ enabling

the use of the OS functions, which includes the function to create the processes.

Using OS process creation function, a process, which can be called initial process, is

created.

OS started and that calls the initial process to run.

When the initial process runs, it creates subsequent processes.

Processes can be created hierarchically.

PCB STRUCTURE:



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Context

Process stack pointer

Current state [Is it created, activated or spawned? Is it running? Is it blocked?]

Addresses that are allocated and that are presently in use

Pointer for the parent process

Pointer to a list of daughter processes.

Pointer to a list of resources, which are usable (consumed) only once. For examples,

input data, memory buffer or pipe, mailbox message, semaphore

Pointer to a list of resources, which are usable (consumed) only once

Pointer to queue of messages.

Pointer to Access-permissions descriptor

ID

MANAGEMENT OF CREATED PROCESS

A process is considered a unit in which sequential running is feasible only under the

control of an OS, with each process having an independent control block.

Process manager is a unit of the OS that is the entity responsible for controlling a

process execution. Process management enables process creation, activation, running,

blocking, resumption, deactivation and deletion. It facilitates multitasking and

multithreading.

A process does the following sequential execution of the states: created, ready or

active, spawn, running, bocked or suspended, resumed, finished and ready after finish,

deleted.

Process manager functions:

o makes it feasible to let for a process to sequentially execute or block when

needing a resource and to resume when it becomes available.

o implements the logical link to the resource manager for resources management

(including scheduling of process on the CPU).

o allows specific resources sharing between specified processes only.

o allocates the resources as per the resource allocation- mechanism of the system.

o manages the processes and resources of the given system.

TIMER FUNCTIONS



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Real time clock is a system clock which on each tick SysClkIntr interrupts. Based on each

SysClkIntr interrupts─ there are number of OS timer functions.

OS_TICK_PER_SEC : to set the system clock ticks and hence SysClkIntr interrupts per

sec.

OSTickInit ( ) : to initiate system clock ticks.

OSTimeDelay ( ) : to delay the process making call by a fixed number of system clock

ticks specified in argument.

OSTimeDelay-Resume ( ) : to resume a delayed process specified in the argument.

OSTimeSet ( ) : to set the counts of system clock ticks.

OSTimeGet ( ) : to read the counts of system clock ticks to find the time interval from

the previous read or write of the counts.

OSSemPend (semVal, twait, *semErr) : to wait for a semaphore release.

OSMboxPend (semVal, twait, *mboxErr) : to wait for a message in mailbox (wait for

message pointed not Null).

EVENT FUNCTIONS

In case of IPC there is a wait for only one event (semaphore or mailbox-message posting

event).

Provisioning of event functions in an OS offers an advantage that there can be wait for

more than one event and the events can also be from the different tasks or ISRs.

Some OS supports and some do not support event functions.

There is a event register which has a set of 8 or 16 or 32 flag-bits. Event register is for

defining the information of occurrences of the events in an event register.

A subset of flags defines an event-group. For example, a 16-bit register can be divided

into four groups. Group 0 is from bit 0 to bit 3, group 1 from bit 4 to bit 7, Group 2 is

from bit 8 to bit 11 and group 3 from bit 12 to bit 15.

OSEventQuery ( )─ to query an event register to find the event register existence and its

contents.

OSEventDelete ( ) ─ delete the event register.

SET (event_flag) to set one of the bits at the event register.

CLEAR (eventFlag) clears the flag in the event register.



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WAIT_ALL function : task waits for the occurrences of setting all the event flags in a

group.

MEMORY MANAGEMENT

MEMORY ALLOCATION

When a process is created, the memory manager allocates the memory addresses (blocks) to it

by mapping the process-address space. Threads of a process share the memory space of the

process.

MEMORY MANAGEMENT AFTER INITIAL ALLOCATION

Memory manager of the OS has to be secure, robust and well protected.

No memory leaks and stack overflows.

Memory leaks means attempts to write in the memory block not allocated to a process

or data structure.

Stack overflow means that the stack exceeding the allocated memory block(s).

RTOS COS-II:

o Memory partitioning.

o A task must create a memory partition or several memory partitions by using

function OSMemCreate ( ).

o Then the task is permitted to use the partition or partitions.

o A partition has several memory blocks.

o OSMemGet ( ) : to provide a task a memory block or blocks from the partition.

o OSMemPut ( ) : to release a memory block or blocks to the partition.

Memory Managing Strategy for a system:

o Fixed-blocks allocation

o Dynamic -blocks Allocation

o Dynamic Page-Allocation

o Dynamic Data memory Allocation

o Dynamic address-relocation

o Multiprocessor Memory Allocation

o Memory Protection to OS functions

o Memory protection among the tasks.



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Memory manager functions:

o use of memory address space by a process,

o specific mechanisms to share the memory space and

o specific mechanisms to restrict sharing of a given memory space

o optimization of the access periods of a memory by using an hierarchy of memory.

DEVICE, FILE AND IO SUBSYSTEMS MANAGEMENT

DEVICE MANAGEMENT

There are a number of device driver ISRs for each device in a system.

Device manager is a software that manages the device drivers of each device.

An OS device manager provides and executes the modules for managing the devices and

their driver ISRs.

o It manages the physical as well as virtual devices like the pipes and sockets

through a common strategy.

o Device management has three standard approaches to three types of device

drivers:

Programmed I/Os by polling from each device its the service need from

each device.

Interrupt(s) from the device drivers device-ISR and

Device uses DMA operation used by the devices to access the memory.

o Device manager functions:

Device Detection and Addition

Device Deletion

Device Allocation and Registration

Detaching and Deregistration

Restricting Device to a specific process

Device Sharing

Device control

Device Access Management

Device Buffer Management

Device Queue, Circular-queue or blocks of queues Management

Device drivers updating and upload of new device-functions

Backup and restoration.



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The device types are: character devices, block devices.

Set of Command Functions for the Device Management:

o Create and open

o write

o read

o ioctl

o close and delete

ioctl Command for Device:

o Accessing specific partition information

o Defining commands and control functions of device registers

o IO channel control.

Three arguments in ioctl ( )

o First Argument: Defines the chosen device and its function.

o Second Argument: Defines the control option or uses option for the IO device.

o Third Argument: Values needed by the defined function are at the third argument

.

Device Driver ISR functions:

o intlock ( ) to disable device-interrupts systems.

o intUnlock ( ) to enable device-interrupts.

o intConnect ( ) to connect a C function to an interrupt vector.

o Interrupt vector address for a device ISR points to its specified C function.

o intContext ( ) finds whether interrupt is called when an ISR was in execution.

Unix OS , device driver functions:

o Facilitates that for devices and files have an analogous implementation as far as

possible.

o open ( ), close ( ), read ( ), write ( ) functions analogous to a file open, close, read

and write functions.

o in-kernel commands:

select ( ) to check whther read/write will succeed and then select.

ioctl ( )

stop ( ) to cancel the output activity from the device.



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strategy ( ) to permit a block read or write or character read or write.

FILE SYSTEM ORGANIZATION AND IMPLEMENTATION

file is a named entity on a magnetic disc, or optical disc, or system memory or memory

stick. Contains the data, characters and text.

OSes differing abstractions of a file:

o A file may be a named entity that is a structured record named entity as on a disk,

which has having random access in the system.

o May be a structured record on a RAM analogous to a disk and may also be either

called separately called as ‘RAM disk’ or as a ‘file’ itself.

o May be an unstructured record of bits or bytes.

o A file device may be a pipe -like device.

Set of Command Functions in the POSIX File System:

o open ( )

o write ( )

o read ( )

o lseek (List seek) or set the file pointer in the byte stream.

o fcntl ( )

o close ( )

Unix has a structured file system with an unstructured hardware interface. File devices

are block devices in UNIX. Linux permits the use of a block devices as a char devices also.

Kernel interface is identical for the char and block devices in Linux and not in UNIX.

There are two types of file systems in BSD Unix:

o Block file system

o Byte stream file system.

Data structure of File descriptor in a Typical File System:

o Identity

o Creator or Owner

o State

o Locks and Protection fields

o file Info

o Sharing Permission

o Count



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o Storing Media Details

I/O SUBSYSTEM

They are the subsystems of OS device management system.

I/O instructions depend on the hardware platform.

Two types of IO operations:

o Synchronous and asynchronous.

Synchronous IO operations: Are at a certain fixed data transfer rate. Therefore, a task

(process) blocks tills till completion of the IO.

Asynchronous IO operations: Variable data transfer rates. Permits that a process of high

priority to run and should not block during the IOs.

I/O Subsystem in a Typical I/O System at in an OS:

o Application

o IO Basic functions

o IO device driver functions

o Device Hardware or Port or IO Interface card.

INTERRUPT ROUTINES IN RTOS ENVIRONMENT AND HANDLING OF

INTERRUPT SOURCE CALLS

In a system ISRs should function as follows:

ISRs should have higher priorities over the OS functions and the application tasks.

An ISR does not also wait for mutex.

There are three alternative systems for the OSes to respond to the hardware source

calls from the interrupts.

1. DIRECT CALL TO AN ISR BY AN INTERRUPTING SOURCE AND ISR SENDING

AN ISR ENTER MESSAGE TO OS



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1. On an interrupt, the process running at the CPU is interrupted. ISR corresponding

to that source starts executing.

2. A hardware source calls an ISR directly. The ISR just sends an ISR enter message to

the RTOS. ISR enter message is to inform the RTOS that an ISR has taken control

of the CPU.

3. ISR code can send into a mailbox or message queue but the task waiting for a

mailbox or message queue

4. But does not start before the return from the ISR. When ISR finishes, it sends Exit

message to OS.

2. RTOS FIRST INTERRUPTING ON AN INTERRUPT, THEN RTOS CALLING THE

CORRESPONDING ISR.

1. On interrupt of a task, say, k-th task, the RTOS first gets itself the hardware

source call

2. and initiates the corresponding ISR after saving the present processor status

(or context).

3. Then the ISR during execution then can post one or more outputs



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4. for the events and messages into the mailboxes or queues.

The ISR must be short and it must simply puts post the messages for another task.

This task runs the remaining codes whenever it is scheduled. RTOS schedules only

the tasks (processes) and switches the contexts between the tasks only. ISR executes

only during a temporary suspension of a task.

3. RTOS FIRST INTERRUPTING ON AN INTERRUPT, THEN RTOS INITIATING THE

ISR AND THEN AN ISR

An RTOS can provide for two levels of interrupt service routines, a fast level ISR,

FLISR and a slow level ISR (SLISR).

The FLISR can also be called hardware interrupt ISR and the SLISR as software

interrupt ISR.

FLISR is called just the ISR in RTOS. The use of FLISR reduces the interrupt latency

(waiting period) and jitter.

Fig shows 7 steps on the interrupt:

1. On interrupt, the RTOS first gets the hardware source call

2. and initiates the corresponding ISR after finishing the critical section and

reaching the preemption point and then saving the processor status (or

context).

3. The ISR executes the device and platform dependent code.



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4. The ISR at the start can mask or disable further pre-emption from the same or

other hardware sources. The ISR during execution then can send one or more

outputs for the events and messages into the mailboxes or queues for the ISTs.

5. The IST executes the device and platform independent code. The ISR just

before the end, unmasks or enables further pre-emption from the same or

other hardware sources.

6. There are ISRs, ISTs, RTOS and tasks in memory blocks other than the

interrupted task. Any interrupt source causes the RTOS to get notice of that,

then completes the critical code till the pre emption point and calls the ISR. ISR

executes afer context saving on stack. The ISR can post messages into the FIFO

for IST after recognizing interrupt source and its priority. The ISTs in the FIFO

that have received the messages from the ISRs executes as per their priorities

on return from ISR.

7. When no ISR or IST is pending execution in the FIFO, the interrupted task runs

on return.

REAL-TIME OPERATING SYSTEM

An RTOS is multitasking OS for the applications needing meeting of time deadlines and

functioning in real-time constraints.

SERVICES:

Basic OS functions : process management, resource management, device management,

subsystem management.

Process priorities management –priority allocation : user level priorities allocation. Real

time priorities are higher than dynamically allocated priorities.

Process management –preemption : the RTOS kernel preempts a lower priority process

when higher priority process is to be executed.

Process priorities management –priority inheritance : it enebles a shared resource in

low priority task be used by a higher priority task first.

Process predictability : a predictable timing behaviour of the system and a predictable

task synchronization with minimum jitter.

Memory management –protection : in RTOS threads of application program can run in

kernel space. The real time performance becomes high.



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Memory management –MMU : memory management is by either disabling the use of

MMU and virtual memory or by using memory locks.

Memory allocation : in RTOS, its fast when there are fixed length memory allocations.

RTOS scheduling and interrupt latency control functions : use of timers, system clock.

Timer functions and time management : time allocation and de allocation to attain

efficieny in given timing constraints.

Asynchronous IO functions : IOs without blocking a task.

IPC synchronization functions : synchronization of tasks with IPCs.

Spin locks : for critical section handling.

Time slicing : of the execution of process with equal priority.

Hard and soft real time operability : hard and soft real time operations.


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