Embedded Bus – i2c

David E. Culler

Lab 2

Feb 2, 2015

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/

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What’s a bus ?

• An efficient means of connecting together several devices so they can interact and transfer information.

• The method of HW composition in computer systems

• N devices, N2 interactions, 1 set of wires• Defined set of Bus Transactions

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P

M M i/o i/o

Modern Computer Systems

network

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Mainstream Systems

• I/O devices you recognize are supported by I/O Controllers• Processors accesses them by reading and writing IO registers as if they were

memory– Write commands and arguments, read status and results

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L3 Cache

(shared)

Registers

Core

Core

Secondary Storage

(Disk)

Processor

MainMemory(DRAM)

Registers

L1 Cache

L1 Cache

L2 Cache

L2 Cache

Secondary Storage

(SSD)

I/O Controllers

Read / Write

Read / Write wires

interrupts

DMA transfer

Example Device-Transfer Rates in Mb/s (Sun Enterprise 6000)

• Device Rates vary over 12 orders of magnitude !!!– System better be able to handle this wide range– Better not have high overhead/byte for fast devices!– Better not waste time waiting for slow devices

10m

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Bus Transaction

• Master => Slave• Arbitration

– Master requests access to bus (if multi-master)• Command (Rd, Wt), Address

– Slave identified by address ack’s request• Data transfer

• Many variants– Synchronous/Asynchronous– Split-Phase– …

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What about embedded systems?• Many simple devices• Extremely constrained interfaces• Serial busses => transaction over a wire or two

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i2c

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i2C• Invented by Philips as chip-chip interconnect for TV sets• 2 signal lines, Vcc and Gnd

– SDA (serial data) and SCL (serial clock)– Both bi-directional (actively pulled down)

• 7-bit slave address• Data in 8-bit bytes – 100 kbps – 2.4 mbps

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I2c transaction

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i2C Signaling• Start/Stop closely tied to physical structure

– SDA falling/rising when SCK is high• Data must remain stable while sck is high, may change while low• Slow slave and stretch clock• Multi-master arbitration by detection of failure to drive

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Transferring Data To/From Controller• Programmed I/O:

– Each byte transferred via processor in/out or load/store– Pro: Simple hardware, easy to program– Con: Consumes processor cycles proportional to data size

• Direct Memory Access:– Give controller access to memory bus– Ask it to transfer data blocks to/from memory directly

• Sample interaction with DMA controller (from OSC):

addrlen

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In embedded ?

• PIO => bit banging the pins to generate a waveform

• DMA– Not just for high performance– Allows MCU to do other things during SLOOOOOW

transfers– Even to go to sleep

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