MIPS Processor

2

MIPS

• MIPS architecture– Developed by John Hennessy and his colleagues at

Stanford and in the 1980’s.– Used in many commercial systems, including Silicon

Graphics, Nintendo, Sony and Cisco

• MIPS is a general-purpose register, load-store, fixed-instruction-length architecture.

Microprocessor without Interlocking Pipeline Stages

3

MIPS Overview

• All instructions are typically of one size

• Few instruction formats

• Arithmetic instructions are register to register– Operands are read from registers

– Result is stored in a register

• General purpose registers– Typically 32 registers

• Memory access only via load and store instructions– Load and store: bytes, half words, words, and double words

• Few simple addressing modes

4

Key ISA decisions

instruction length are all instructions the same length?

how many registers?where do operands reside?

e.g., can you add contents of memory to a register?

instruction format which bits designate what?

operands how many? how big? how are memory addresses computed?

operations what operations are provided?

5

Registers

• 32 General Purpose Registers (GPRs)– 32-bit registers are used in MIPS32

– Register 0 is always zero

– Any value written to R0 is discarded

• Special-purpose program counter, PC

6

Instruction Length

• Fixed-length Instructions– 32-bit instructions – Operations on 32-bit data

• Three instruction formats:– R-Type: register operands– I-Type: immediate operand– J-Type: for jumping

7

Instruction Formats

• Register (R-Type)– Register-to-register instructions

• Immediate (I-Type)– 16-bit immediate constant is part of instruction

• Jump (J-Type)– Used by jump instructions

Op: operation code specifies the format of the instruction

Op6 Rs5 Rt5 Rd5 funct6shamt5

Op6 Rs5 Rt5 immediate16

Op6 immediate26

8

R-Type Format

• op: operation code (opcode)– Specifies the operation of the instruction– Also specifies to CPU the format of the instruction

• funct: function code – extends the opcode– Up to 26 = 64 functions can be defined for the same opcode– MIPS uses opcode 000000 to define R-type instructions

• 3 Register Operands (common to many instructions)– rs, rt: first and second source operands– rd: destination operand– shamt or sa: shift amount used by shift instructions, else 0

Register-type

9

R-TypeExamples

0 17 18 16 0 32

Field Values

0 11 13 8 0 34

op rs rt rd shamt funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Note the order of registers in the assembly code:

add rd, rs, rt 000000 10001 10010 10000 00000 100000

op rs rt rd shamt funct

000000 01011 01101 01000 00000 100010

Machine Code

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

(0x02328020)

(0x016D4022)

Assembly Code

add $16, $17, $18

sub $8, $11, $13

10

I-Type Format

• 3 operands:– rs, rt: register operands; rs source, rt now the destination register– imm: 16-bit two’s complement immediate

• Other fields:– op: specifies operation of the instruction– Simplicity favors regularity: all instructions have opcode– Operation is completely determined by the opcode

Immediate-type

op rs rt imm6 bits 5 bits 5 bits 16 bits

I-Type

11

I-Type

Assembly Code

8 17 16 5

Field Valuesop rs rt imm

6 bits 5 bits 5 bits 16 bits

addi $s0, $s1, 5

addi $t0, $s3, -12

lw $t2, 32($0)

sw $s1, 4($t1)

8 19 8 -12

35 0 10 32

43 9 17 4

Examples

(0x22300005)

(0x2268FFF4)

(0x8C0A0020)

(0xAD310004)

001000 10001 10000 0000 0000 0000 0101

op rs rt imm

Machine Code

6 bits 5 bits 5 bits 16 bits

001000 10011 01000 1111 1111 1111 0100

100011 00000 01010 0000 0000 0010 0000

101011 01001 10001 0000 0000 0000 0100

Note the differing order of registers in the assembly and machine codes:

addi rt, rs, imm

lw rt, imm(rs)

sw rt, imm(rs)

addi $18, $17, 5

addi $8, $19, -12

lw $10, 32($0)

sw $17, 4($9)

12

I-Type

• The second type of I-format instruction we need to consider is the branch instruction.

• Operation:– Compare contents of two registers, rs and rt – if they are equal, branch forward/backward the number of

instructions given by the offset

Branch Instruction

1 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0

31 25 20 15 0

beq = 4 bne = 5

Source 2 Source 1 Relative branch distance in words

op rs rt operand / offset

I 1

13

J-Type Format

• J-type format is used for unconditional jump instruction:j label # jump to label . . .label:

• 26-bit immediate value is stored in the instruction– Immediate constant specifies address of target instruction

• Program Counter (PC) is modified as follows:

– Next PC =

– Upper 4 most significant bits of PC are unchanged

Jump-type

Op6 immediate26

immediate26 PC4 00least-significant 2

bits are 00

14

Instruction Categories

• Arithmetic and Logic– Arithmetic, logical, and shift instructions

• Data Transfer– Load and store instructions that access memory

• Jump and Branch– Flow-control instructions that alter the sequential

sequence

15

Instruction Categories

• Only a subset of the MIPS instructions are considered– ALU instructions (R-type): add, sub, and, or, xor– Immediate instructions (I-type): addi, andi, ori– Load and Store (I-type): lw, sw– Branch (I-type): beq, bne– Jump (J-type): j

• Sufficient to illustrate design of datapath and control

16

Register Transfer Level (RTL)

• RTL is a description of data flow between registers

• RTL gives a meaning to the instructions

• All instructions are fetched from memory at address PC

Instruction RTL DescriptionADD Reg(Rd) ← Reg(Rs) + Reg(Rt); PC ← PC + 4

SUB Reg(Rd) ← Reg(Rs) – Reg(Rt); PC ← PC + 4

ORI Reg(Rt) ← Reg(Rs) | zero_ext(Im16); PC ← PC + 4

LW Reg(Rt) ← MEM[Reg(Rs) + sign_ext(Im16)]; PC ← PC + 4

SW MEM[Reg(Rs) + sign_ext(Im16)] ← Reg(Rt); PC ← PC + 4

BEQ if (Reg(Rs) == Reg(Rt))PC ← PC + 4 + 4 × sign_extend(Im16)

else PC ← PC + 4

17

Instructions are Executed in Steps

• R-type Fetch instruction: Instruction ← MEM[PC]Fetch operands: data1 ← Reg(Rs), data2 ← Reg(Rt)Execute operation:ALU_result ← func(data1, data2)Write ALU result: Reg(Rd) ← ALU_resultNext PC address: PC ← PC + 4

• I-type Fetch instruction: Instruction ← MEM[PC]Fetch operands: data1 ← Reg(Rs), data2 ← Extend(imm16)Execute operation:ALU_result ← op(data1, data2)Write ALU result: Reg(Rt) ← ALU_resultNext PC address: PC ← PC + 4

• BEQ Fetch instruction: Instruction ← MEM[PC]Fetch operands: data1 ← Reg(Rs), data2 ← Reg(Rt)Equality: zero ← subtract(data1, data2) Branch: if (zero) PC ← PC + 4 + 4×sign_ext(imm16)else PC ← PC + 4

18

Instruction Execution – cont’d

• LW Fetch instruction: Instruction ← MEM[PC]Fetch base register: base ← Reg(Rs)Calculate address: address ← base + sign_extend(imm16)Read memory: data ← MEM[address]Write register Rt: Reg(Rt) ← dataNext PC address: PC ← PC + 4

• SW Fetch instruction: Instruction ← MEM[PC]Fetch registers: base ← Reg(Rs), data ← Reg(Rt)Calculate address: address ← base + sign_extend(imm16)Write memory: MEM[address] ← dataNext PC address: PC ← PC + 4

• Jump Fetch instruction: Instruction ← MEM[PC]Target PC address: target ← PC[31:28] + Imm26 x 4 Jump: PC ← target

19

Word-Addressable Memory

• Each 32-bit data word has a unique address

Data

00000003 4 0 F 3 0 7 8 8

0 1 E E 2 8 4 2

F 2 F 1 A C 0 7

A B C D E F 7 8

00000002

00000001

00000000

Word Address

Word 3

Word 2

Word 1

Word 0

Memory

Up to 232 bytes = 230 words

4 bytes per word

. . .

. . .

20

Byte-Addressable Memory

• Each data byte has a unique address

• Each 32-bit word has 4 bytes, so the word address increments by 4

MIPS is byte-addressed, not word-addressed

Word Address Data

0000000C

00000008

00000004

00000000

width = 4 bytes

4 0 F 3 0 7 8 8

0 1 E E 2 8 4 2

F 2 F 1 A C 0 7

A B C D E F 7 8

Word 3

Word 2

Word 1

Word 0

Data

00000003 4 0 F 3 0 7 8 8

0 1 E E 2 8 4 2

F 2 F 1 A C 0 7

A B C D E F 7 8

00000002

00000001

00000000

Word Address

Word 3

Word 2

Word 1

Word 0

Word addressablememory byte addressable

memory

21

Reading Byte-Addressable Memory

• Address of a memory word must now be multiplied by 4. • For example,

– the address of memory word 2 is 2 × 4 = 8– the address of memory word 10 is 10 × 4 = 40 (0x28)

• Load a word of data at memory address 4 into $19.• $19 holds the value 0xF2F1AC07 after the instruction completes.

MIPS assembly codelw $19, 4($0) # read word at address 4 into $s3

Word Address Data

0000000C

00000008

00000004

00000000

width = 4 bytes

4 0 F 3 0 7 8 8

0 1 E E 2 8 4 2

F 2 F 1 A C 0 7

A B C D E F 7 8

Word 3

Word 2

Word 1

Word 0

22

MIPS addressing modes

register

add $1, $2, $3

immediate

addi $1, $2, #35

base + displacement

lw $1, 24($2)

OP rs rt rd sa funct

OP rs rt immediate

rt

rs

immediatevalue

register indirect disp = 0direct (rs) = 0

rd

displacementrt

rs

rs

rt

23

Requirements of the Instruction Set

• Memory– Instruction memory where instructions are stored– Data memory where data is stored

• Registers– 32 × 32-bit general purpose registers, R0 is always zero– Read source register Rs– Read source register Rt– Write destination register Rt or Rd

• Program counter PC register and Adder to increment PC

• Sign and Zero extender for immediate constant

• ALU for executing instructions

24

Datapath Components

• Combinational Elements– ALU, Adder

– Immediate extender

– Multiplexers

• Storage Elements– Instruction memory

– Data memory

– PC register

– Register file

• Clocking methodology– Timing of reads and writes

DataMemory

Address

Data_inData_out

MemRead MemWrite

32

32

32

32

Address

Instruction

InstructionMemory

32

mux

0

1

select

Extend 3216

ExtOp

Registers

RA

RB

BusA

RegWrite

BusB

RW

5

5

5

32

32

32

BusW

PC

32 32

ALU

ALU control

ALU result

zero

32

32

32

25

ALU (Arithmetic Logical Unit)

• Inputs: – 2 32-bit numbers– srcA and srcB

• Outputs– result of arithmetic/logical operation

plus Zero detection for result

• Control– 3 bits to decide the particular operation

ALUresult

ALU

ALUcontrol3

Zero

ALUcontrol Function

000 AND

001 OR

010 add

110 subtract

111 slt

32

32

32

26

ALU (Arithmetic Logical Unit)Implementation

ALUcontrol Function

000 AND

001 OR

010 add

110 subtract

111 slt

27

Details of the Extender

• Two types of extensions– Zero-extension for unsigned constants– Sign-extension for signed constants

• Control signal ExtOp indicates type of extension• Extender Implementation: wiring and one AND gate

ExtOp = 0 Upper16 = 0

ExtOp = 1

Upper16 = sign bit

..

.

ExtOp

Upper16 bits

Lower16 bits

..

.

Imm16

28

Register Element

• Register

– Similar to the D-type Flip-Flop

• n-bit input and output

• Write Enable:

– Enable / disable writing of register

– Negated (0): Data_Out will not change

– Asserted (1): Data_Out will become Data_In after clock edge

• Edge triggered Clocking

– Register output is modified at clock edge

Register

Data_In

ClockWrite

Enable

n bits

Data_Out n bits

29

MIPS Register File

• Register File consists of 32 × 32-bit registers– BusA and BusB: 32-bit output buses for reading 2 registers– BusW: 32-bit input bus for writing a register when RegWrite is 1– Two registers read and one written in a cycle

• Registers are selected by:– RA selects register to be read on BusA– RB selects register to be read on BusB– RW selects the register to be written

• Clock input– The clock input is used ONLY during write operation– During read, register file behaves as a combinational logic block

• RA or RB valid => BusA or BusB valid after access time

RegisterFile RA

RB

BusA

RegWrite

BusBRW

5

5

5

32

32

32

BusWClock

30

Details of the Register File

n-to-1decoder

Register 0

Register 1

Register n – 1C

C

D

DRegister n

C

C

D

D

Register number

Write

Register data

0

1

n – 1

n

Mux

Register 0

Register 1

Register n – 1

Register n

Mux

Read data 1

Read data 2

Read registernumber 1

Read registernumber 2

Read ports are implemented with a pair of multiplexors – 5- bit multiplexors for 32 registers

Write port is implemented usinga decoder – a 5-to-32 decoder for32 registers. Clock, C is relevant to write as register state may change only at clock edge

31

Details of the Register File

BusA

R1

R2

R31

...

BusW

Dec

oderRW

5

Clock RegWrite

...

R0 is not used

BusB

"0" "0"RADecoder

5 RBDecoder

5

32

32

32

32

32

32

32

32

32

Tri-statebuffer

32

Instruction and Data Memories

• Instruction memory needs only provide read access– Because datapath does not write instructions– Behaves as combinational logic for read– Address selects Instruction after access time

• Data Memory is used for load and store– MemRead: enables output on Data_out

• Address selects the word to put on Data_out

– MemWrite: enables writing of Data_in• Address selects the memory word to be written• The Clock synchronizes the write operation

MemWriteMemRead

DataMemory

Address

Data_in

Data_out 32

32

32

Clock

32Address Instruction

InstructionMemory

32

33

Clocking Methodology

• Use edge-triggered clocking– All state changes occur on the same clock edge

– Data must be valid and stable before arrival of clock edge

• Edge-triggered clocking allows a register to be read and written during same clock cycle

Defines when data can be written and read

Combinational logic

Reg

iste

r 1

Reg

iste

r 2

clock

rising edge falling edge

34

Determining the Clock Cycle

• With edge-triggered clocking, clock cycle must be long enough to accommodate path from one register through combinational logic to another register

Must satisfy timing constraints: Ts and Th

Tcycle ≥ Tclk-q + Tmax_comb + Ts

Combinational logic

Reg

iste

r 1

Reg

iste

r 2

clock

writing edge

Tclk-q Tmax_comb Ts Th

Tclk-q : clock to output delay through register

Tmax_comb : longest delay through combinational logic

Ts : setup time that input to a register must be stable before arrival of clock edge

Th: hold time that input to a register must hold after arrival of clock edge

Hold time (Th) is normally satisfied since Tclk-q > Th

35

Implementing MIPS

• High-level abstract view of fetch/execute implementation– use the program counter (PC) to read instruction address– fetch the instruction from memory and increment PC– use fields of the instruction to select registers to read– execute depending on the instruction– repeat…

Fetch-Execute Cycle

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

36

Datapath

• How can you read and update the PC?– Each instruction occupies 4 bytes

so increment PC by 4 each clock cycle to reach the next instruction

– PC read during the first half of the clock period and it is updated with PC+4 at the next rising clock edge

Instruction Fetch

Clk

Time

PC 100 104 108 112

In 104 108 112 116

37

Animating the DatapathInstruction Fetch

Instruction <- MEM[PC]PC <- PC + 4

RDMemory

ADDR

PC

Instruction

4

ADD

38

R-type datapath

• The R-format instructions– all take data from the two source registers– perform an ALU operation on that data

• ALUoperation signal depends on op and funct

– then write the data back to a third register

39

Animating the r-type Datapath

add rd, rs, rt

R[rd] <- R[rs] + R[rt];

5 5 5

Data1

Data2

Read1 Read2 Write

WriteData

RegWrite

Register File

op rs rt rd functshamt

Operation

ALU Zero

Instruction

3

40

Load/Store Datapath

• load word (lw) and store word (sw) – A base address is given in register rs – 16-bit immediate added to rs to obtain required memory location– register rt holds the data to be written to or read from memory

41

Animating the lw Datapath

• R[rt] <- MEM[R[rs] + s_extend(offset)];

lw rt, offset(rs)

op rs rt offset/immediate

5 5

16

RegWrite

RegisterFile

Operation

ALU

3

EXTND

16 32

Zero

ReadDataWrite

Data

MemRead

MemoryADDR

MemWrite

5

Data1

Data2

Read1 Read2 Write

WriteData

42

Animating the sw Datapath

• MEM[R[rs] + sign_extend(offset)] <- R[rt]

sw rt, offset(rs)

op rs rt offset/immediate

5 5

16

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

ReadData

WriteData

MemRead

MemoryADDR

MemWrite

5

Data1

Data2

Read1 Read2 Write

WriteData

43

Combining datapathsHow do we allow different datapaths for different instructions?

R-type Store

44

Combining datapaths

• Use a mux!

How do we allow different datapaths for different instructions?

ALUscr

45

Combining datapaths

• How do we allow different datapaths for different instructions??

R-type StoreALUscr

46

Animating the Combined DatapathR-type Instruction

add rd,rs,rt

5 516

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction32

MUX

MUXALUSrc

MemtoReg

Data1

Data2

Read1 Read2 Write

WriteData

47

Animating the Combined DatapathLoad Instruction

lw rt,offset(rs)

5 516

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction32

MUX

MUXALUSrc

MemtoReg

Data1

Data2

Read1 Read2 Write

WriteData

48

Animating the Combined DatapathStore Instruction

sw rt,offset(rs)

5 516

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction32

MUX

MUXALUSrc

MemtoReg

Data1

Data2

Read1 Read2 Write

WriteData

49

Branch Datapath

• ALU performs a subtraction operation• sets zero status signal if rs and rt equal• zero output used by branch control logic to determine if

the branch should be taken

• Effective target address for branch calculated by• sign-extending the address/immediate field (offset)• then shifting the result two bits to the left (x4) to get the

offset in bytes• update PC with calculated value (nPC = PC+EA)

beq rs, rt, imm16 We need to compare Rs and Rt

op rs rt immediate

016212631

6 bits 16 bits5 bits5 bits

50

Datapath: Branch Instruction

No shift hardware required:simply connect wires from input to output, each shifted left 2 bits; shift left by 2 results in a multiply by 4

51

Animating the beq Datapath

• if (R[rs] == R[rt]) then PC <- PC+4 + (sign_extend(offset))*4

beq rs, rt, offset

op rs rt offset/immediate

5 5

16

RegWrite

Register File

Operation

ALU

EXTND

16 32

Zero

ADD

<<2

PC +4 from instruction datapath

Data1

Data2

Read1 Read2 Write

WriteData

52

Complete Datapathcontrol signals in blue

4

Shiftleft 2

PCAdd

Add

0

Mux

1

PCSrc

Readaddress

Writeaddress

Writedata

Datamemory

Readdata

MemWrite

MemRead

1

Mux

0

MemToRegReadaddress

Instructionmemory

Instruction[31-0]

I [15 - 0]

I [25 - 21]

I [20 - 16]

I [15 - 11]

0

Mux

1

RegDst

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 2

Readdata 1

Registers

RegWrite

Signextend

0

Mux

1

ALUSrc

Result

ZeroALU

ALUOp

53

Datapath Executing add

add rd, rs, rt

5 516

RD1

RD2

R1 R2 Wr

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction

32

MUX

ALUSrc

MemtoReg

ADD

<<2

RD

InstructionMemory

ADDR

PC

4

ADD

ADD

MUX

MUX

PCSrc

54

Datapath Executing lw

lw rt,offset(rs)

5 516

RD1

RD2

R1 R2 Wr

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction

32

MUX

ALUSrc

MemtoReg

ADD

<<2

RD

InstructionMemory

ADDR

PC

4

ADD

ADD

MUX

MUX

PCSrc

55

Datapath Executing sw

sw rt,offset(rs)

5 516

RD1

RD2

R1 R2 Wr

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction

32

MUX

ALUSrc

MemtoReg

ADD

<<2

RD

InstructionMemory

ADDR

PC

4

ADD

ADD

MUX

MUX

PCSrc

56

Datapath Executing beq

beq r1,r2,offset

5 516

RD1

RD2

R1 R2 Wr

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction

32

MUX

ALUSrc

MemtoReg

ADD

<<2

RD

InstructionMemory

ADDR

PC

4

ADD

ADD

MUX

MUX

PCSrc

57

MIPS Datapath and Control

58

Input:– 6-bit opcode field from instruction

Output:– 9 control signals for datapath– ALUOp for ALU Control

Main Control and ALU Control

ALUControl

MainControl

Datapath 32

Address

Instruction

InstructionMemory

ALU

Op6

RegD

st

RegW

rite

ExtO

p

ALU

Src

Mem

Read

Mem

Writ

eM

emto

Reg

Beq

ALUOp

ALUCtrl

func

t6

J

Input: 6-bit function field from instruction

ALUOp from main control

Output: ALUCtrl signal for ALU

59

Control Unit: ALU Decoder

ALUOp1:0 Meaning

00 Add

01 Subtract

10 Look at Funct

11 Not Used

ALUOp1:0 Funct ALUControl2:0

00 X 010 (Add)

X1 X 110 (Subtract)

1X 100000 (add) 010 (Add)

1X 100010 (sub) 110 (Subtract)

1X 100100 (and) 000 (And)

1X 100101 (or) 001 (Or)

60

Signal Effect when ‘0’ Effect when ‘1’

RegDst Destination register = Rt Destination register = Rd

RegWrite None Destination register is written with the data value on BusW

ExtOp 16-bit immediate is zero-extended 16-bit immediate is sign-extended

ALUSrc Second ALU operand comes from the second register file output (BusB)

Second ALU operand comes from the extended 16-bit immediate

MemRead None Data memory is readData_out ← Memory[address]

MemWrite None Data memory is writtenMemory[address] ← Data_in

MemtoReg BusW = ALU result BusW = Data_out from Memory

Beq PC ← PC + 4 PC ← Branch target addressIf branch is taken

J PC ← PC + 4 PC ← Jump target address

ALUOp This multi-bit signal specifies the ALU operation as a function of the opcode

Main Control Signals

61

Control Unit: Main Decoder

Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemRead MemtoReg ALUOp1:0 Jump

R-type 000000 1 1 0 0 0 0 0 10 0

lw 100011 1 0 1 0 0 1 1 00 0

sw 101011 0 X 1 0 1 0 X 00 0

beq 000100 0 X 0 1 0 0 X 01 0

addi 001000 1 0 1 0 0 0 0 00 0

j 000100 0 X X X 0 0 X XX 1

62

Control logicCombinational Implementation

R-format Iw sw beq

Op0

Op1

Op2

Op3

Op4

Op5

Inputs

Outputs

RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOpO

63

Extended Functionality: j

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1PC'

Instr25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

0

1

25:0 <<2

27:0 31:28

PCJump

Jump

target ← PC[31:28] + Imm26 x 4