1

Frequency Synthesizers for Communication Systems

Part of this material came from courtesy of Ari Valero

Analog and Mixed-Signal Center

A M S C

ELEN 665 (Edgar Sánchez-Sinencio)

2

Outline

• Introduction• Linear model • Charge Pump PLL• Performance Metrics• Design Methodology

3

What is a PLL?

• From a communications point of view, a phase-locked loop is an optimum phase estimator

• For an input r(t)=Asin(ωt + φ), the PLL provides an estimate Asin(ωt + φML)

How does it work?- Inject sinusoidal signal into the reference input- The internal oscillator locks to the reference- Frequency and phase differences between the reference

and internal sinusoid = k or 0- Internal sinusoid then represents a filtered version of the

reference sinusoid

4

Where is it used?• Frequency Synthesis

– Reference frequency for modulation and demodulation

– Clock reference– Radio, Television

• Clock Recovery– Serial interfaces (Computers, optical networks)

• FM demodulation– Radio

5

What does it look like?Phase

Detector

fin f

outLoopFilter VCO

• Phase Detector (PD). Nonlinear block that provides the phase difference between the input and oscillating signal

• Loop Filter (LPF). Eliminates high order harmonics of PD output and helps to stabilize the loop

• Voltage Controlled Oscillator (VCO). Nonlinear device that generates a sinusoidal signal whose frequency is controlled by its DC input.

• Feedback interconnection. The output of the VCO is fed to the Phase Detector to generate a phase error signal. This phase error signal controls the oscillation frequency of the VCO.

6

How can we implement a Frequency Synthesizer with a PLL?

PhaseDetector

FrequencyDivider

fin foutLoopFilter VCO

If a frequency divider is introduced in the feedback interconnection, the frequency of the reference input is multiplied by the feedback factor at the output of

the PLL

inout fNf ⋅=

N Integer -> Integer-N Frequency SynthesizerN Fractional -> Fractional-N Frequency Synthesizer

From a fixed reference frequency (fin) a large set of output frequencies (fout)

can be generated

7

Linear Model

The following phase domain model provides a way to study the

characteristics of operation of the loop

A PLL depends on nonlinear operations to work properly

To analyze its behavior we need to limit the analysis to the locked state

φΔ= PDPFD KV

divin φφφ −=Δ

)()( tVKtf ctrlVCOVCO =

∫=t

ctrlVCOVCO dttVKt0

)()(φ

sK

sVssG VCO

ctrl

VCOVCO =

Φ=

)()()(

The output of the phase detector is:

Where the phase difference is:

The output of the VCO is:

Integrating both sides

In s-domain the VCO transfer function becomes:

Kpd

1N

φin φoutG(s)

KVCO

sφdiv

Kpd(φin-φdiv)

−

+

The Loop Filter transfer function:

)(sG

The loop is considered locked when the phase and frequency of the

feedback (divided VCO output) is exactly equal to the average phase

and frequency of the input

8

)()(

)()()(

sGKKNssGKKN

sssH

VCOPD

VCOPD

in

outout +

=ΦΦ

=

)()(

)()(

)(sGKKNs

sGKN

ss

sHVCOPD

VCOout

+=

ΦΦ

=Δ

Δφ

φ

The order of a PLL is defined by the number of poles in the open

and closed loop transfer functions and the type of a PLL indicates the

number of perfect (lossless) integrators in the loop

The closed loop transfer function:

The transfer function from phase error to output:

PLL Transfer Function

Hold Range: the frequency range over which the PLL is able to statically maintain phase tracking: ∆ωH = KPDKVCOG(0).

Lock Range: the frequency range within which the PLL locks within one single-beat note between the reference frequency and output frequency: ∆ωL ≈ ±KPDKVCOG(∞).

The Pull-In and Pull-Out Range: The pull-in range, ∆ωP, is defined as the frequency range in which the PLL will always become locked. The pull-out range, ∆ωPO, is defined as the limit of dynamic stability for the PLL. No simple relationships for these.

9

Type – I PLL

τττ

NKKssKKsH

VCOPD

VCOPDout //

/)( 22 ++=

VCOPD

VCOPD

in

outout KKNs

KKNsssH

+=

ΦΦ

=)()()(1

VCOPD

VCOPDn

KKNNKK

τξ

τω

21

=

=

11)()( 2 +

==τs

sGsG

1)(1

)()(21

23 ++

+==

τττ

ss

sGsG22

2

3 22)(

nn

nnout ss

ssHωξω

ωξω++

+=

⎟⎟⎠

⎞⎜⎜⎝

⎛++

+=

+=

VCOPD

VCOPD

VCOPDn

KKN

NKK

NKK

221

21

)(21

)(

τττ

ξ

ττω

1)()( 1 == sGsG

For a Type-I PLL with different Loop Filters G(s) we have the following responses

C1

R2

R1

Vin Vout

τ1=R1C1τ2=R2C1

10

Type – I PLL

10 -2 10 -1 100-40

-30

-20

-10

0

10

Mag

nitu

de (d

B)

10 -2 10 -1 100-200

-150

-100

-50

0

Frequency [Hz]

Phas

e (D

egre

e)

|Hout1(s)|

|Hout2(s)|

|Hout3(s)|

Hout1(s)

Hout2(s)

Hout3(s)

A drawback of type-I phase-locked loops is that it is not

possible to set independently the loop

bandwidth ωn, the damping factor ξ and the loop gain

KPDKVCO

Comparison of the closed loop transfer function of the PLL for the three previous loop filters

11

Charge Pump PLL (Type-II)Advantages:• Increased locking range• Speed up in capture process• Phase Frequency Detector (PFD)

– Charge Pump (CP) combination creates extra pole at zero frequency

• This pole provides infinite gain at DC, which results in zero phase error in ideal locked state

PFDfin fout

VCO

1N

C1

R1

C2

Charge Pump

Loop Filter

fdiv

VDD

UP

DWN

Iin Vvco

A type-II PLL is the most commonly used for frequency synthesizer applications, it is

also known as charge-pump PLL

Disadvantages:• Sampled operation introduces

spurious tones at the VCO output• Loop bandwidth limited by stability

considerations

Note: This PLL is also known as Digital PLL since the phase comparison and frequency division are performed digitally

12

Phase-Frequency Detector• Compares edges of reference

and divided clocks.• If reference clock leads the

divided clock, the UP signal is asserted.

• If the divided clock leads the reference clock , the DWN signal is asserted.

• In an ideal PFD no pulses are present at the output in the locked state.

• Duty cycle of inputs is not relevant to the circuit operation.

• The width of the UP/DWN pulses is proportional to the phase difference between the clock inputs.

VDD

UP

DWN

D Q

CLR

D Q

CLR

"1"

"1"

Div

In

Out

fREF

UP

DWN

fDIV Typical PFD implementation

Conceptual PFD-CP

13

up=0dn=1

up=0dn=0

up=1dn=0

refref

div div

div ref

-0.1 -0.05 0 0.05 0.1-1

0

1

Phase error (2πrad)

Ave

rage

Cha

rge

Pum

p C

urre

nt

(μA)

State machine of PFDPhase response of PFD with dead zone

• In practical PFD the delay of the gates creates non-idealities in the phase input/output characteristic.

• The PFD can no longer resolve very small phase errors, and a dead zone is created.

• To solve this problem, extra delay is introduced in the feedbackpath of reset signal.

14

tontref

t

UP

DWN

• In locked state, narrow pulses are generated in both UP/DWN outputs.

• The width of these pulses determines the amount of noise introduced to the VCO output by the charge-pump.

• Timing mismatch between the UP/DWN pulses is a source of spurious tones.

Output of PFD for locked state

15

Charge Pump• The Charge-Pump converts

the phase error information provided by the PFD into a voltage that controls the VCO frequency.

• If the UP input is asserted, S1 is closed and charge is injected into capacitor C1, increasing voltage Vout

• If the DWN input is asserted, S2 is closed and charge is extracted from capacitor C1,decreasing voltage Vout

C1

VDD

UP

DWN

D Q

CLR

D Q

CLR

"1"

"1"

Div

In

VoutS1

S2

Icp

Icp

t

UP

DWN

Vout

Total CP current

Icp

16

Charge PumpCalculating the Detector Gain:

πφ2Ttup⋅Δ

=

φπΔ==

2cpup

cppd

ITt

II

π2cp

pd

IK =

Capacitor C1 is the main integrating capacitor; it generates the pole at zero frequency. Resistor R1 introduces a stabilizing zero. Capacitor C2 is added to the loop filter to reduce the glitches on the VCO control voltage

The time the UP/DWN signals are asserted is:

Where T is the reference period and Δφ is the phase difference measured by the PFD.

The average current provided by the charge pump for a given Δφ is:

Which gives an overall phase detector gain Kpd of:

17

• Current mismatch– Mismatch between source and sink

currents in the charge pump introduces a finite phase error.

• Current leakage– When the source/sink currents are off,

leakage currents can flow and modify the VCO control voltage of the VCO by charging/discharging the loop filter. Spurs are introduced.

• Charge sharing– Parasitic capacitances from the switches

share charge with the loop filter when the nodes they are connected to have a large change in their voltage.

• Charge injection– Occurs when switches are turned off

and the charge in their channels is injected/extracted to the loop filter. Spurs are introduced

Non-ideal effects of charge pumps

Δton

Δicp

ileak

18

Loop Filter Characteristics• The PFD-CP and C1 combination introduces a pole at

zero frequency.

• This pole, along with the zero generated by the VCO generates -40dB/decade loop gain at low frequency.

• If the loop gain crosses 0dB with a slope of -40dB, then the circuit is unstable.

• In order to stabilize the circuit, resistor R1 is introduced in series with C1 to create a zero.

• The zero at ωz reduces the slope of the loop gain to-20dB/decade and stabilizes the circuit.

• Capacitor C2 is added to reduce ripples in the VCO control voltage. Adds a second pole ωp2 to the loop filter.

• An extra (third) pole can be added to further eliminate VCO ripple, at the expense of phase margin degradation (stability)

21

21

211

211CR

CCCC

Rp ≈

+

=ω

C1

R1

C2

Iin

Vvco

11

1CRz =ω

19

Loop Filter

[ ])(1)(

2112111

111 CCRsCRCRs

CsRRIVsZin

VCO

+++

==

102 103 104 105 106 10750

60

70

80

90

100

110

120

130

140

Frequency [Hz]|Z

(s)|

[dB

ohm

]

[ ])(1

2

)()(

2112111

111 CCRsCRCRs

CsRRNIK

NsZKKsH

cpVCO

VCOPD

in

divol

+++

=

==

π

φφ

⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟

⎠

⎞⎜⎜⎝

⎛= −−

2

11 tantanp

c

z

cm ω

ωωωφ1

2

12 +=⋅=

CC

zpzc ωωωω

Transimpedance of loop filter

The phase margin

The transimpedance of loop filter is:

And the open loop transfer function of the PLL

The crossover frequency (0dB gain in the Hol(s))

20

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

+

−⎟⎟⎠

⎞⎜⎜⎝

⎛+=

⎟⎟⎠

⎞⎜⎜⎝

⎛−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛=

−−

−−

1

1tan1tan

tantan

2

1

1

2

11

2

121

CCC

Cm

p

z

z

pm

φ

ωω

ωω

φ

2

12

2

1

1

1

CC

CC

cp

cz

+=

+=

ωω

ωω

NRKI

CCCR

NKI vcocpvcocp

c1

21

11 ≈

+=ω

The phase margin, zero and pole frequency can be written as a function of the capacitor ratio C1/C2

With these values, the crossover frequency as a function of PLL parameters can be obtained.

This form of the equation assumes the crossover frequency is aligned with the maximum of the phase margin

This equation shows that the loop bandwidth is not a function of C1, but a function of R1, Kvco, Icp and N.

In general, the crossover frequency Wc is equal to the loop bandwidth of the PLL.

21

Plotting the open loop response of the PLL helps to determine graphically the crossover frequency and phase margin

102 103 104 105 10610

7-100

-50

0

50

100PLL Open Loop Response

Mag

nitu

de[d

B]

102

103

104

105

106

107

-180

-160

-140

-120

-100

Pha

se

f(Hz)

Deg

ree

PM

ωc

ωz

ωp2

The ratios between ωc/ωz and

ωp2/ωc determine the phase

margin and damping factor of the

PLL.

Thus, the transient characteristics

of the loop are set by them.

22

Performance MetricsThe design of frequency synthesizers for RF systems involves complying to a large set of specifications, such as:

– Tuning Range and Frequency Resolution– Phase Noise– Spurious Signals– Settling Time

Communication standards usually do not include particular block specifications. It is up to the system/circuit designer to obtain the proper circuit specifications for each building block

23

Frequency Resolution and Accuracy

The frequency resolution of the synthesizer is set by the required channel spacing of the intended application

± 5 kHz200 kHz1.710 – 1.7851.805 – 1.880

DCS1800

± 60 kHz20 MHz2.400 – 2.479IEEE 802.11g

± 60 kHz5 MHz2.400 – 2.479IEEE 802.11b

± 60 kHz20 MHz5.150 – 5.3505.750 – 5.850

IEEE 802.11a

± 75 kHz1 MHz2.400 – 2.479Bluetooth

Frequency AccuracyFrequency ResolutionTuning range(GHz)

Standard

The frequency accuracy is related with the maximum offset that the synthesized frequency can have, with respect to the desired center frequency

The frequency resolution affects the selection of synthesizer architecture (Integer / Fractional)

The frequency accuracy defines a boundary for settling time calculation

24

Phase Noise

£(Δω)

dBc/

Hz

0

spur[dBc]

carrier

Δωf

Power

ω0ω0−ωm ω0+ωm

Phase noise is a measure of the spectral purity of a signal and is one of the most important parameters for characterization of the synthesizer

Phase noise degrades the quality of the data in a communication system

( ) ( ))(sin)(1)( 0 tttatv θω +⋅+=

Assume the PLL output is a sinusoidal tone at ω 0

with amplitude and phase variation a(t) and θ(t) respectively

θ(t) has a random part and a deterministic part

θ(t)=θ r(t)+ θd⋅sin(ωdt)

The random part, θ r(t), accounts for phase noise and the deterministic part, θd⋅sin(ωdt), for spurious tones

25

Phase Noise (continued..)Assuming the phase variations are a single tone in the phase, θ(t)= θm⋅sin(ωmt), and the root mean square (rms) value of θ(t) is much smaller than 1 radian, the output of the oscillator becomes:

( ) ( )[ ]ttAtAtv mmm

osc )(sin)(sin2

)sin()( 000 ωωωωθω −+++⋅≈

the output spectrum of the oscillator contains a narrowband FM signal with a modulation index θm and a strong component at the fundamental frequency ω0

The oscillator output voltage power spectral density (PSD) is related to the phase noise PSD

⎥⎦⎤

⎢⎣⎡ −+−+−= )(

21)(

21)(

2)( 000

2

ωωωωωωδω θθ SSASV

)(2

)(2

mmS ωωδθωθ −=

The phase noise skirt is directly translated to noise side lobes at both sides of the carrier frequency

26

Phase Noise (continued..){ }ωΔ£Phase noise is defined as the ratio of the noise power, in a

bandwidth of 1 Hz at a certain offset frequency Δω from ω0, to the carrier power Pcarrier

{ } ( )carrier

noise

PP ωω Δ

=Δat band Hz1log10£

The actual phase noise at an offset ωm is:

{ } ][ 2

)(log102

)(log10£ 20 dBcSA

S mmV ⎟⎠⎞

⎜⎝⎛=

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛ +=Δ

ωωωω θ

The units dBc/Hz refer to the ratio between the noise and the carrier in dB in a bandwidth of 1 Hz.

27

Phase Noise (continued..)The phase noise at the output of the VCO comes from

•Reference clock•Phase-Frequency Detector•Charge Pump•Loop Filter•Frequency Divider•VCO Active Devices Noise

Due to this noise, the output of the VCO is no longer a single frequency tone, but a smeared version

Sometimes the energy is concentrated at frequencies other than the desired frequency, appearing as a spike above the skirt. This energy is due to a spurious tone.

28

Effect of Phase Noise in Received Signal

Unwanted ChannelsDesiredChannel

Rec

eive

d Si

gnal

Syn.

Out

put

Rec

eive

r O

utpu

t

Noise

Desired signal

Phase Noise

Spurious tone

Desired Tone

fRF

fLO

fIF = fRF - fLO

Phase Noise and Spurious Tones are mixed with adjacent channels and degrade the desired downconverted signal.

The unwanted channels may be much larger than the desired channel (as much as 40dB for Bluetooth), setting stringent requirements for phase noise and spurious signals.

29

Phase Noise SpecificationThe total noise, Pnoise, in a channel with bandwidth fBW, blocker power Pblk at an offset frequency Δω from the desired channel and a phase noise £{Δω} is

{ } )dBc/Hz(£)dBHz()dBm()dBm( ωΔ++= BWblknoise fPP

The equation assumes that the phase noise is constant (white) in the channel bandwidth

The signal-to-noise ratio (SNR) of the downconverted signal is:

)dBm()dBm(SNR(dB) noiseIF PP −=

{ }[ ])dBHz()dBc/Hz(£)dBm()dBm(SNR(dB) BWblksig fPP +Δ+−= ω

For a minimum received signal Psig_min, maximum blocker signal Pblk_max and minimum required SNR, the phase noise specification can be determined as:

{ } )dB(SNR)dBHz()dBm()dBm()dBc/Hz(£ max_min_ −−−<Δ BWblksig fPPω

30

Phase Noise Numerical Example

For Bluetooth the carrier-to-interferer ratio at a 3MHz offset is 40dB, the SNR is 16dB, the channel bandwidth is 1MHz. With these values the phase noise can be calculated

{ }{ } HzdBcMHz

dBHzedBMHz/1163£

16)61log(1040)dBc/Hz(3£−<

−−−<

A margin has to be added to the obtained value since there are more contributions to the degradation of the signal to noise ratio (SNR), generally this margin is related to the overall noise figure of the system and can be as large as 4dB

31

Close-in Phase NoiseThe close-in phase noise is the portion of the phase noise located very close to the oscillator center frequency

It is usually dominated by the noise of the reference signal and is typically constant over the loop bandwidth (ωn)

)dB(SNR)dBHz)(4log(10)dBc/Hz(£i −−< nω

The term 4ωn accounts for the double sided noise around the fundamental tone of the oscillator and the contribution to the phase noise of the reference at frequencies higher than the loop bandwidth

ωn-ωn

32

Spurious SignalsThe periodic phase variation at the output of the oscillator generates spurious tones (also named spurs)

Spurs are generated due to the sampled nature of the charge-pump PLL.

The spur specification is calculated in a similar fashion as the phase noise, but now the noise is concentrated in a single frequency, instead of being smeared in the channel bandwidth.

( ) )dB(SNR)dBm()dBm()dBc(spur max_min_ −−<Δ blksig PPω

( )( ) dBcMHzMHz

462spur)dB(16)dBm(30)dBc(2spur

−<−−<

For Bluetooth the carrier-to-interferer ratio at a 2MHz offset is 30dB, the SNR is 16dB and the spur results in:

33

Effect of non-idealities on spurious signals

( ) ( )[ ]ttAtAtv mmm

sposc )(sin)(sin2

)sin()( 000 ωωωωθω −+++⋅≈

Recall that the oscillator output modulated by a sinewave of baseband frequency fm generates a pair of frequency components – the spurious signals, at a distance ± fm from the carrier frequency f0

The previous equation also shows that the amplitude of the spurious signals Asp is related to the amplitude of the carrier signal A and to the peak phase deviation θm by

2m

sp AA θ=

To calculate the magnitude of the spurious tones we need to determine the maximum phase variation as a function of the amplitude at the tuning line of the VCO, Am

34

spurious signals continued . .

ref

mvcorefmvcom

AKdAKω

ττωθτ

== ∫max0

)cos(

The amplitude of the undesired spurious tone in decibel with respect to the magnitude of the carrier can be obtained

⎟⎟⎠

⎞⎜⎜⎝

⎛=

⎟⎠⎞

⎜⎝⎛=⎥

⎦

⎤⎢⎣

⎡

ref

mvco

m

dBc

sp

AK

AA

ω

θ

2log20

2log20

The maximum tuning line ripple Am for a given spurious specification [Asp/A] dBc is:

20m 10

2 A

dBc

sp

AA

vco

ref

K

⎥⎦

⎤⎢⎣

⎡

=ω

35

There are two main effects which can generate reference spurious:

1. Leakage current in loop filter and charge-pump

If the charge-pump current Iout is considered as a periodic pulse train, the Fourier series representation is

∑∞

=

+=1

)2cos(2)(n

refleakleakout tnfIItI π

)(2 refleakm jZIA ω= ⎟⎟

⎠

⎞

⎜⎜

⎝

⎛=⎥

⎦

⎤⎢⎣

⎡

ref

vcorefleak

dBc

sp

fKfjZI

AA

ππ

2)2(

log20

The relative amplitude of the spurious signals does not depend on the absolute bandwidth of the loop filter or on the charge-pump current Icp.

It is only a function of the transimpedance of the loop filter Z(s), the VCO gain Kvco and the absolute magnitude of the leakage current Ileak.

The amplitude of the ripple signal generated by the leakage current at the reference frequency Am is

36

2. Mismatch in the charge-pump Up and Down current sources

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛=⎥

⎦

⎤⎢⎣

⎡

ref

vcorefout

dBc

sp

fKfjZI

AA

ππ

4)2(

log20

Similar calculations can be performed to obtain the magnitude of the spurious tone as a function of the mismatch of charge-pump currents

The Fourier series of the current waveform must be obtained and the fundamental tone of Iout obtained.

The previous results are very important, since they allow the designer to estimate the spurious tone magnitude during the initial design of the charge-pump and without the need of close loop simulations

37

Phase Noise in a PLLθIN(s)

Kpd Z(s)

IPD(s) VLF(s)

Kvco/s

θVCO(s)

θOUT(s)

1/N

θDIV(s)

( )( )sZKKsNsZKKN

sssH

vcopd

vcopd

IN

OUTLP +⋅

⋅==

)()()(

θθ

( )sZKKsNsN

sssH

vcopdVCO

OUTVCO +⋅

⋅==

)()()(

θθ

( )sZKKsNKN

sVssH

vcopd

vco

LF

OUTLF +⋅

⋅==

)()()( θ

At very low frequencies N⋅s << KpdKvcoZ(s)and HLP(s) ≈ N

For frequencies above the loop bandwidth, N⋅s << KpdKvcoZ(s) and lims→∞ HVCO(s) = N

bandpass characteristic and presents peaking at frequencies around the loop bandwidth

38

• VCO highpass• REF lowpass

39

Settling time

)()( ∞−≥ outout ftfε

DEFINITION: The time required for the PLL to change its output frequency from fout(0) to fout(∞) within a frequency error smaller or equal to ε

( )⎭⎬⎫

⎩⎨⎧

⎟⎠⎞

⎜⎝⎛ Δ+=Δ+= refrefout fNNNfNNf 1

Applying a change in the reference frequency from fref to and leaving the divider ratio N unchanged also provides the same VCO output frequency (N+ΔN)fref

ssKsG fτ+

=1)(

C1

R1Iin Vout

The output frequency of the VCO

The filter used for the analysis contains one pole at the origin and one zero that stabilizes the loop

( )22

2

22)(

nn

nn

sssNsH

ωζωωζω+++

=

The closed loop transfer function is:

40

Settling time (continued . . . )

( )( )mmvcofpd

NKKK

φφτζ

cos2sin

2==

( )mcvcofpd

n NKKK

φωω cos==

)()()( sHsN

Nffsfsf refrefoutout ⋅

Δ=−=Δ

( ))2(

2)( 22

2

nn

nnrefout sss

sNfsfωζω

ωζω++

+Δ=Δ

The steady state frequency can be found using the final value theorem

The PLL responds to the input frequency step as

refref

srefoutout NfsHsN

Nfsfff Δ=⎥

⎦

⎤⎢⎣

⎡⋅

Δ=−∞=∞Δ → )(lim)()( 0

and the lock time can be calculated as:

{ }

ε

ε

<∞Δ−⎭⎬⎫

⎩⎨⎧

⋅Δ

=

<∞Δ−Δ=

−

−

)()(

)()(

1

1

outref

lock

outoutlock

fsHsN

NfLt

fsfLt

where

41

Overdamped 1Damped Critically 1

dUnderdampe 10

>=

<<

ξξ

ξ ( )

( )⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

>⎟⎠⎞

⎜⎝⎛ −±−±−

=−

<−±−

=

1 1

1 1 1

2

2

2,1

ζζζωζω

ζζωζζζω

ω

nn

n

n

j

j

Decomposing the transfer function of Δfout(s) in partial fractions we obtain the general form

⎪⎪⎪⎪⎪

⎩

⎪⎪⎪⎪⎪

⎨

⎧

>−

−

Δ−

+−−

Δ

+Δ

=−

Δ+

+

Δ−+

Δ

<−−

Δ−

+−−

Δ

+Δ

=Δ

1 1212

0 )(

1 1212

)(

2

2

2

1

2

1

2

2

2

2

1

2

1

ζω

ωζ

ω

ωωζ

ω

ζωω

ω

ωωζ

ω

ωωζ

ω

sj

Nf

sj

Nf

sNf

sNf

sNf

sNf

ζs

j

Nf

sj

Nf

sNf

sf

n

ref

n

ref

ref

n

nref

n

refref

n

ref

n

ref

ref

out

Settling time (continued . . . )Depending on the value of the damping factor ξ, there are three different cases

The poles of the transfer function for each case are

42

Applying the inverse Laplace transformation

( )

⎪⎪⎪⎪

⎩

⎪⎪⎪⎪

⎨

⎧

>⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

+−+Δ

=−Δ

<⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

−+Δ

=Δ

−−

−

−−

1 12

1

0 )1(-1

1 12

1

)(

2

21

2

21

21

21

ζωζ

ωω

ζω

ωζ

ωω

ωω

ω

ωω

n

tt

ref

nt

ref

n

tt

ref

out

eeNf

teNf

ζj

eeNf

tf n

⎪⎪⎪⎪

⎩

⎪⎪⎪⎪

⎨

⎧

>⎟⎟

⎠

⎞

⎜⎜

⎝

⎛−

−+−Δ

=−Δ

<⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ −−−

−Δ

=

−

−

−−

1 )1(sinh1

-)1cosh(

0 )1(

1 1

tan1sin1

2

2

2

212

2

ζζωζζζω

ζω

ζζ

ζωζ

ε

ζω

ω

ζω

tteNf

teNf

ζteNf

nnt

ref

nt

ref

n

t

ref

n

n

n

Substituting in the equation for tlock (page40), the frequency error ε becomes:

Settling time (continued . . . )

43

( )( )

⎪⎪⎪⎪⎪

⎩

⎪⎪⎪⎪⎪

⎨

⎧

>−

+−Δ

−−

=

<⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

Δ

=

1 12

1ln

11

0 y numericall Solved

1 1

ln

2

2

2

2

ζξε

ξξ

ωξξ

ζζωζε

ref

n

n

ref

lock

Nf

ζ

Nf

t

Settling time (concluded . . . )

Solving for tlock we obtain expresions for the settling time for a given frequency step and error

44

Plot of the normalized lock-time τωn as a function of

the damping factor ξ for several values of ε

rNfΔ

.

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 25

10

15

20

25

30

35

40

45

Damping Factor ζ

Nor

mal

ized

lock

-tim

e τω

n

E=102

E=103

E=104

E=105

ΔNfrεE=

45

Design Procedure• Choose a phase margin• Calculate the damping factor required to obtain the desired phase margin (Fig. 2.19a) • Based on the damping factor, settling time and settling accuracy determine the minimum loop bandwidth ωc,min• Determine C1/C2 ratio based on the phase margin • Calculate C2,min based on leakage current Ileak (1nA), charge pump mismatch Iout (2nA) and spurious

suppression • Calculate C1,min • Compute the position of the zero ωz• Calculate the value of resistor R1 • Determine the charge pump current

46

Examples of circuit implementations

Vdd

Vdd

35 μA

UP

DWN

Iout

VbiasN

VbiasP

Cascode current mirrors minimize the current mismatch.

But reduce linear range of output voltage.

Charge Pump

Design Considerations:

• Source and sink current matching.

• Source and sink speed matching.

• Leakage current minimization.• Reference Spurs.• Compliance voltage.

47

Loop Filter

C1

R1

C2Vo

Icp

+

-

• Trade offs– Settling Time– Close-in Phase Noise– Total Capacitance (area)– Charge Pump Current– Phase Noise Contribution of

R1

48

Vc

Vb

Ib

• Trade offs– Phase Noise– Tuning Range– Power Consumption

Voltage Controlled Oscillator

49

Programmable Divider

%(N+1)/N %P

%S

fIN fOUT

ChannelSelection

Reset

SwallowCounter

PrescalerProgramCounter

• Popular scheme for integer-N FS• Program Counter can be also

programmed• Fast response of Swallow

Counter

inout fSNPf )( +=NSPSN )()1( −++

SP >

50

Prescaler• Critical block in design of FS along with VCO (High frequency of

operation)• Usually consumes a lot of power• Two main architectures

– Synchronous– Asynchronous

• Frequency dividers– Digital

• Pure digital (TSPC logic)• Quasi – digital (Current Mode Flip - Flops)

– Analog• Injection – locked frequency dividers

51

Synchronous Prescaler 3/4 2 2

MC

fin fout

MCi

Q

QSET

CLR

D

Q

QSET

CLR

D

MCi

Vout

CLK

• Input Flip – Flops run at maximum speed

• Feedback gates need minimum delay

• Feedback reduces speed by aprox. 30%

52

CMOS Flip - Flop

• Current Mode Logic (CML). Low voltage swing• Input differential pair followed by latch• Speed limited by RC product of output nodes

Vdd

A

CLK CLK

Vb

Vbias

Q

Q

CLK CLK

B

53

Phase Switching Prescaler

• Architecture

Phase switching prescaler for reduced power consumption

compared with traditional architectures.

fin /4fin

÷ 2IQIQ

f in /2

5GHz

2.5GHz 1.25

GHz

To Mixers LO Port

625MHz

÷ 2IQIQ

PhaseSelection

÷ 2

ModulusControl

÷ 2fout

IQIQ

÷ 2

PhaseSelection

fin /8

/2 /

2

/2

/2

/2

I

QI

Q

p0p2p4p6

p1p3p5p7

ModulusControl

Mux

15/16 Dual Modulus

54

fin /4

1.25GHz 625

MHz

IQIQ

PhaseSelection

÷ 2

ModulusControl

÷ 2fout

IQIQ

÷ 2

PhaseSelection

fin /8

/2

/2

p0p2p4p6

p1p3p5p7

ModulusControl

Mux

Phase Switching Prescaler

1 2 3 4 5 6 7 1 2 3 4 5 6 7 8

1 2 3 4 1 2 3 4

1 2 3

fout

Mux

p7

p6

p5

Phase switching principle

Every rising edge of fout the multiplexer selects a phase that lags 45° the current phase, effectively swallowing an input pulse (dividing by N+1)

55

÷ 2IQIQ

D Q

Q

D Q

QCLK

I QImplementation: High Frequency D Flip-flop in bipolar technology

Vdd

CLK CLK

D

Q

Q

Vbias

R R

D

Ibias

56

Recent Advances in Frequency Synthesizers Design

a)

• The research focuses in:– New Architectures– Linearization techniques (spur reduction)– Digital PLL– Fast Settling– New and improved VCO– Reduced power frequency dividers– Low voltage – low power PLLs

57

Dual Loop Architectures

PFDfref1 fout

1N

Charge Pump

VDD

UP

DWN

VCO1

LPF PFDfref2

1N

Charge Pump

Loop FilterBW2

VDD

UP

DWN

VCO2

LPF

N=16

100MHz 800kHz

ChannelSelection

Loop FilterBW1

1XX=4SSB

Mixer

PFDfref1 fout

1N

Charge Pump

VDD

UP

DWN

VCO1

LPF

fref2 = 205MHz

1.6MHz

Loop FilterBW1

1X

X=32

PFDfref2

1N

Charge Pump

Loop FilterBW2

VDD

UP

DWN

VCO2

LPF

11.3 - 17.45 MHz

ChannelSelection

865.2 - 889.9 MHz

W. Yan and H. C. Luong, “A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers”, IEEE JSSC, vol. 36, pp: 204-216, February 2001.

T. Kan and H. C. Luong, “A 2-V 1.8-GHz Fully Integrated CMOS Frequency Synthesizer for DCS-1800 Wireless Systems”, VLSI Circuits, pp: 234 - 237, 2000.

58

Nested Loop PLL and Stabilization Technique

PFDfref1

1N2

Charge Pump

VDD

UP

DWN

IFVCO

LPF

Loop FilterBW1

ChannelSelection

foutPFD

1N1

Charge Pump

Loop FilterBW2

VDD

UP

DWN

RFVCO

LPF

foutPFD

1N

UP

DWN

VCO

CP1

CP1ΔT

Vcont

C1

fref

Ip1

Ip2

A.N. Hafez and M.I. Elmasry, “A Fully-Integrated Low Phase-Noise Nested-Loop PLL for Frequency Synthesis”, CICC, pp: 589 – 592, 2000.

T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers”, VLSI Symposium, pp: 39 - 42, 2001