Electronics_Ch15.pdf

CHAPTER 15 ADVANCED MOS AND BIPOLAR LOGIC CIRCUITS

Chapter Outline15.1 Pseudo-NMOS Logic Circuits15.2 Pass-Transistor Logic Circuits15.3 Dynamic MOS Logic Circuits15.4 Emitter-Coupled Logic (ECL)15.5 BiCMOS Digital Circuits

NTUEE Electronics III 15-1

15.1 PSEUDO-NMOS LOGIC CIRCUITS

NMOS Inverter Circuits A simple inverter circuit is composed of a NMOS and a load The load can be realized by a resistor or another NMOS device

Resistive LoadNMOS Inverter

Enhancement LoadNMOS Inverter

Depletion LoadNMOS Inverter


Pseudo-NMOS Inverters Use a PMOS transistor as the load Does not suffer from body effect Directly compatible with complementary CMOS circuits Area and delay penalties arising from the fan-in in

complementary CMOS gate are reduced

Pseudo-NMOS Inverter

15.1 PSEUDO-NMOS LOGIC CIRCUITS

Static Characteristics Load curve represents a much lower saturation current kn is usually greater than kp by a factor of 4 to 10 A ratioed type logic with r kn/kp

The logic is typically operated in two extremely cases: vI = 0: vO = VOH = VDD

vI = VDD: vO = VOL > 0 (nonzero VOL for pseudo-NMOS) The VTC can be derived based on iDN and iDP:

n)(saturatio for )(21 2

tIOtInDN VvvVvki


2

(triode) for 21)( 2

tIOOOtInDN VvvvvVvki

n)(saturatio for )(21 2

tOtDDpDP VvVVki

(triode) for )(21))(( 2

tOODDODDtDDpDP VvvVvVVVki

Derivation of the VTC Assume Vtn = |Vtp| = Vt for the derivations Region I (Segment AB):

Region II (Segment BC):

Region III (Segment CD):

R i IV (S t DE)

DDOHO VVv

22 )()( tItDDtO VvrVVVv

22 )(

21))((

21)( ODDODDtDDOOtI vVvVVVvvVvr


Region IV (Segment DE):

Static Characteristics:

DDOH VV )/11)(( nptDDOL kkVVV

)1/)(/(

pnpn

tDDtIL kkkk

VVVV)(/3

2tDD

pntIH VV

kkVV

OLILL VVNM IHOHH VVNM

1/

pn

tDDtM kk

VVVV

22 )(1)()( tDDtItIO VVr

VvVvv

Dynamic Operation Determine tPLH:

The analysis is identical to the CMOS inverter and the output capacitance C is charged by PMOS

Determine tPHL: The discharge current is iDN iDP while iDP is typically negligible as r is large

for a large value of r and tPHL is much larger than tPLH

DDp

pPLH Vk

Ct

where

2

347/2

DD

t

DD

tp V

VVV

DDn

nPHL Vk

Ct where

21311

431/2

DD

t

DD

tn V

VVV

rr


n p for a large value of r and tPHL is much larger than tPLH

Design of Pseudo-NMOS Inverter Determine ratio r = kn / kp

The larger the value of r, the lower VOL is A larger r increases the asymmetry in the dynamic response Usually, r is selected in the range of 4 to 10

Determine (W/L)n and (W/L)p

A small (W/L) to keep the gate area and the value of C small A small (W/L) to keeps Isat of QP and static power dissipation low A large (W/L) to obtain a small propagation delay tP and fast response

Gate Circuits Design of gate circuits refers to a standard pseudo-NMOS inverter The approach to determine the PDN is identical to that of a complementary CMOS gate The sizing of the PDN has to be taken into account to meet VOL and delay requirement


Concluding Remarks In pseudo-NMOS, NOR gates are preferred over NAND gates in order to use minimum-size devices Pseudo-NMOS is particularly suited for applications in which the output remains high most of the time

The static power dissipation can be reasonably low The output transitions that matter would presumably be high-to-low ones where the propagation delay

can be made as short as necessary

15.2 PASS-TRANSISTOR LOGIC CIRCUITS

Design of Pass-Transistor Logic (PTL) Circuits Using series and parallel combinations of switches The switches are controlled by input logic variables to connect the input and output nodes Can be implemented by a single NMOS transistor or CMOS transmission gate Every circuit node has at all times a low-resistance path to VDD or ground


ABCY )( CBAY

Operation with NMOS Transistor as the Switch Pass-transistor with output high (“poor 1”)

The output node refers to the source terminal of the NMOS Q is in saturation during the charging process and Vt increases with vO due to body effect tPLH increases as the charging current reduces by higher Vt due to body effect VOH = VDD Vt leads to a reduction in the gate noise immunity


Pass-transistor with output low (“good 0”) The input node refers to the source terminal of the NMOS No body effect The output node can be discharged completely VOL = 0

Restoring the Output Level The circuit-based approach by adding a feedback loop with QR

The PMOS QR turns on by vO2 (= “0”) to restore the signal loss at vO1 = “1” The PMOS QR is turn off by vO2 (= “1”) when vO1 = “0” Operation is more involved than it appears due to the positive feedback QR has to be a “weak PMOS transistor” in order not to play a major role in the circuit operation

The alternative approach by process technology The signal loss is due to the threshold voltage of the NMOS devices Threshold adjustment by ion implantation to during fabrication make zero-threshold devices S bth h ld d ti b i ifi t f th h ld d i


Subthreshold conduction becomes significant for zero-threshold devices

The Use of CMOS Transmission Gates as Switches PMOS and NMOS are in parallel with complementary control signals Both NMOS and PMOS provide charging/discharging current Good logic level with VOH = VDD and VOL = 0 The complexity, silicon area and load capacitance are increased Body effect has to be taken into account to evaluate iDN and iDP


The Equivalent Resistance of the Transmission Gate The equivalent resistance of QN:

For vO VDD Vtn:

For vO VDD Vtn:

The equivalent resistance of QP: For vO |Vtp |:

2)(21

OtnDDnDN vVVki 2)(

21

OtnDDn

ODDNeq

vVVk

vVR

0DNi NeqR

and

and

2|)|(1 VVk d ODD vVR


For vO |Vtp |:

Empirical formula for the equivalent resistance:

2|)|(21

tpDDpDP VVki and2|)|(

21

tpDDp

ODDPeq

VVkR

2)(

21)|)(|( ODDODDtpDDpDP vVvVVVki and

2)(21)|)(|( ODDODDtpDDp

ODDPeq

vVvVVVk

vVR

)()/(

5.12 k

LWR

nTG

Calculation of Propagation Delay in the Signal Path The signal path containing multiple transmission gates can be modeled by resistors and capacitors


The model is in a form of an RC ladder network The propagation delay is given by Elmore delay formula as

*Elmore delay formula is given by

)])(()[(69.0 122111 TGPinTGPTGoutP RRCCRCCt

...])()([69.0 321321211 RRRCRRCRCtP

Pass-Transistor Logic Circuit Examples


Final Remarks Advantages of CMOS transmission gate over pass-transistor logic with NMOS devices

Logic level: good “1” and “0” No level restoring technique needed

Disadvantages of CMOS transmission gate over pass-transistor logic with NMOS devices Silicon area and complexity: an additional input requires one NMOS and one PMOS devices Complementary control signal required Propagation delay: more capacitive loading from the MOSFETs

15.3 DYNAMIC LOGIC CIRCUITS

Principle of Dynamic Logic Circuits Rely on the storage of signal voltage on parasitic capacitances at certain circuit nodes The circuits need to be periodically refreshed Maintain the low device count of pseudo-NMOS while reducing the static power dissipation to zero

Operation of Dynamic Logic Circuits Precharge phase: Qp on and Qe off charge the output node to VDD

Evaluation phase: Qp off and Qe on selectively discharge the output node through PDN


Nonideal Effects Noise margin:

Since VIL ≈ VIH ≈ Vtn , the resulting noise margins are NML ≈ Vtn and NMH ≈ VDD Vtn

Asymmetric noise immunity (poor NML) Output voltage decay due to leakage effects:

Leakage current will slowly discharge the output node when PDN is off The leakage is from the reversed-biased junctions and possibly the subthreshold conduction

Charge sharing: Some of the internal nodes in PDN will share the charge in CL even the PDN path is off Can be solved by adding a permanently turn-on transistor QL at the cost of static power dissipation


Can be solved by adding a permanently turn on transistor QL at the cost of static power dissipation

Domino CMOS Logic Problem with cascading dynamic logic gates: errors cuased by undesirable premature discharge

t

t

Y1

Y2

Precharge Evaluation

VM

Premature discharge


Domino CMOS logic: A dynamic logic with a static CMOS inverter connected to its output The output Y is 0 in the precharge phase and at the beginning of the

evaluation phase Alleviate the premature discharge problem for the following stages

A cascade of Domino CMOS logic: Each stage has to wait for the rising edge from the preceding stage The rising edge propagates through a cascade of gates


Concluding Remarks Advantages of Domino logic: small silicon area, high-speed operation, and zero static power dissipation Disadvantages of Domino logic:

Asymmetric noise margin Leakage issue Charge sharing Dead time: unavailability of output during precharge phase

15.4 EMITTER-COUPLED LOGIC (ECL)

Basic Principle High speed is achieved by operating all transistor out of saturation to avoid storage time delays By keeping the logic signal swings relatively small (~0.8V) to reduce the charging/discharging time One of the inputs is connected to a reference voltage VR

When vI is greater than VR by about 4VT vO1 = VCC IRC and vO2 = VCC

When vI is smaller than VR by about 4VT vO1 = VCC and vO2 = VCC IRC. Important features of ECL:

The differential nature of the circuit makes it less susceptible to picked-up noise The current drawn from the power supply remains constant during switching no current spikes. The output signal levels are both referenced to VCC and can be made particularly stable with VCC = 0V


The output signal levels are both referenced to VCC and can be made particularly stable with VCC 0V Some means has to be provided to make the output signal levels compatible with those at the input The availability of complementary output considerably simplifies logic design with ECL

The Basic Gate Circuit Bias network:

The network generates a reference voltage VR of 1.32V at room temperature VR is made to change with T in a predetermined manner so as to keep the noise margins constant VR is also made relatively insensitive to variations in the power supply voltage VEE


Differential input stage: Paralleling input transistors (QA and QB) are used to implement OR and NOR functions Current in RE remains approximately constant over the normal range of operation Use resistors to connect each input terminal to the negative supply can leave unused inputs open

Emitter-follower output stage: On-chip loads are not included as the gate drives a transmission line terminated at the other end in

most of high-speed logic Emitter followers shift the level by one vBE drop the shifted levels are centered around VR

Provide low output resistance and large current driving capability Separate power-supply prevents coupling of power-supply spikes from the output to the gate circuit


ECL Families ECL 100K: tP ≈ 0.75ns and PD ≈ 40mW PDP = 30pJ ECL 10K: tP ≈ 2ns and PD ≈ 25mW PDP = 50pJ A variant of ECL (current-mode logic) has become popular in VLSI applications

Voltage Transfer Characteristics Definition of unity-gain: QA (or QR) is conducting 1% (or 99%) of IE

Assuming the vBE = 0.75V at a emitter current of 1 mA for an ECL transistorOR Transfer Curve


mVVVVII

TQBEQBE

AQE

RQEAR

11599ln||99||

VVIL 435.1115.032.1

VVIH 205.1115.032.1

mAR

VVVI

E

EEQBERE

R 4779.0

2.575.032.1|

VVOL 73.175.0245.04

VVOH 88.0

VVVNM OLILL 335.0)77.1(435.1

VVVNM IHOHH 325.0)205.1(88.0 for vI < VIL:

NOR Transfer Curve

V6671750220174

mVVVVII

TQBEQBE

AQE

RQEAR

11599ln||99||

VVIL 435.1115.032.1

VVIH 205.1115.032.1

for vI < VIL: VOH = 0.88V

for vI = VIH:

mAR

VVVI

E

EEQBEIHE

A 17.4779.0

2.575.0205.1|


VvO 667.175.022.017.4

VVVNM OLILL 323.0)758.1(435.1

VVVNM IHOHH 325.0)205.1(88.0

for vI = VOH:

VVOL 758.175.022.058.4

mAR

VVVI

E

EEQBEOHE

A 58.4779.0

2.575.088.0|

Manufacturers’ Specifications VILmax = 1.475 V VIHmin = 1.105 V VOLmax = 1.630 V VOHmin = 0.980 V

Fan-Out IIL = (1.77+5.2)/50 = 69 A IIH = (0.88+5.2)/50 + 4/101 = 126 A Input currents are small and output resistance is small fan-out of ECL is not limited by logic-level The fan-out is limited by considerations of circuit speed

Operating Speed The speed is measured by the delay of its basic gate and by the rise and fall times of the output waveforms


p y y g y p Using emitter follower as the output stage, the ECL gate exhibit shorter rise time than its fall time

Signal Transmission ECL is particularly sensitive to ringing because the signal levels are so small One solution is to keep the wires very “short” with respect to the signal rise/fall time

the reflections return while the input is still rising/falling If greater lengths are needed, then transmission lines must be used

the reflection is suppressed with proper termination

Power Dissipation Gate power dissipation of unterminated ECL remain relatively constant independent of the logic state No current spikes are introduced on the supply line The need for supply-line bypassing in ECL is not as great as in TTL

Thermal Effects The reference voltage VR is 1.32V at room temperature VR is made to change with T in a predetermined manner so as to keep the noise margins almost constant A demonstration of the high degree of design optimization of this gate circuit

Wired-OR Capability


p y The emitter follower output stage of the ECL family allows wired-OR for logic design The OR function is implemented by wiring the output of several gates in parallel

15.5 BICMOS DIGITAL CIRCUITS

The BiCMOS Circuits BiCMOS Technology combines Bipolar and CMOS Circuits on one IC chip CMOS (low-power, high input impedance, wide noise margins) + Bipolar (high current-driving capability) Particularly useful for logic with large fan-out (large capacitive load)

The Simple BiCMOS Inverter Cascading each of the QN and QP devices of the MCOS inverter with an npn transistor Input high:

QN turns on and the drain current flows into the base of Q2 as the base current The initial discharge current ≈ iDN + iDN vO drops Q i d t i d ith i 0 d t V ( 0 7V) V V


QN in deep triode with iD = 0 as vO drops to VBEon (≈ 0.7V) VOL = VBEon

Input low: QP turns on and the drain current flows into the base of Q1 as the base current The initial discharge current ≈ ( iDP vO increases QP in deep triode with iDP=0 as vO drops to VBEon (≈ 0.7V) VOH = VDD VBEon

Q1 and Q2 are operating in nonsaturation mode and will not turn on simultaneously Reduced noise margin due to smaller logic swing No base discharge path to speed up the turn-off of Q1 and Q2 long turn-off delays.

BiCMOS Inverter with “Bleeder Resistors” Resistor R1 and R2 are added to provide base discharge paths for Q1 and Q2 turn-off Input high:

QN turns on and QP turns off provides discharging current through QN and Q2

vO is discharged below VBEon through QN and R2 improved noise margin Pulling vO from VBEon to ground is rather slow due to the high impedance path (QN and R2)

Input low: QN turns off and QP turns on provides charging current through QP and Q1

A dc current path exist from VDD to ground through QP and R1 when Q1 is off vO can only be charged up to VDD VDS P VBE by Q1


vO can only be charged up to VDD VDS,P VBEon by Q1

R1 and R2 take some of the drain currents of QP and QN away from the bases of Q1 and Q2 and thus slightlyreduce the output charging/discharging currents of the gate

R1 and R2 are typically implemented by MOSFET QR1 and QR2

QR1 conducts only when vI is high R1 to discharge Q1

QR2 conducts only when vI is low R2 to discharge Q2

BiCMOS Inverter “R-circuit” R1 is connected to the output node rather than returning to ground: The problem of static power dissipation is now solved R1 now functions as a pull-up resistor, pulling the output node voltage up to VDD


Dynamic Operation The detailed analysis of the dynamic operation is rather complex The propagation delay is estimated by the time required to charge and discharge a load capacitance C Such an approximation is justified in cases where C is relatively large Usually the case for application of BiCMOS inverters

iii

RVi

VVLWki

RDB

BEonR

tPDDP

pD

/

||21

1

1 1

2


iCVt

iii

DDPLH

RB

2/

)1(1

iCVt

iii

iii

RVi

VVVLWki

DDPHL

DB

RDB

BEonR

tnBEonDDN

nD

2/

/21

2

2 2

2

BiCMOS Logic Gates BiCMOS logic gates can be implemented following the same approach as the inverters The bipolar portion simply functions as an output stage QN and QP are replaced by pull-down network and pull-up network


Electronics_Ch15.pdf

Documents

Transcript of Electronics_Ch15.pdf