Electronic Circuit Analysis Laboratory · Introduction to DOS and BIOS Interrupts Cont.. 22 No DOS...

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C.Lokanath ReddyAssistant Professor

[email protected]

Department of Electronics and Communication Engineering

MICROPROCESSORS & INTERFACING (A1423)Unit-IV

Interrupts and Programmable Interrupt Controllers

VARDHAMAN COLLEGE OF ENGINEERING(AUTONOMOUS)

Shamshabad, Hyderabad - 501218

Microprocessors & Interfacing (A1423)

UNIT-IV

C.LOKANATH REDDY2

Interrupts and Programmable Interrupt Controller

8086 Interrupts and Interrupt Responses

Introduction to DOS and BIOS interrupts

8259A Priority Interrupt Controller

Software Interrupt Applications

The 8086 Maximum Mode

Direct Memory Access Data Transfer

Interfacing and Refreshing Dynamic RAMs

8254 Software-Programmable Timer/Counter

mailto:[email protected]

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8086 Interrupts and Interrupt Responses

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The dictionary meaning of the word ‘interrupt’ is to

break the sequence of operation.

While the CPU is executing a program, an ‘interrupt’

breaks the normal sequence of execution of

instructions, diverts its execution to some other

program called Interrupt Service Routine (ISR).

After executing ISR, the control is transferred back

again to the main program which was being executed

at the time of interruption.


8086 Interrupts and Interrupt Responses Cont..

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An 8086 interrupt can come from any one of three

sources.

1. One source is an external signal applied to the

Nonmaskable interrupt (NMI) input pin or to the

interrupt (INTR) input pin. An interrupt caused by a

signal applied to one of these inputs is referred to as

a HARDWARE INTERRUPT.

2. A second source of an interrupt is execution of the

Interrupt instruction, INT. This is referred to as a

SOFTWARE INTERRUPT.

3. The third source of an interrupt is some error

condition produced in the execution of an instruction

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At the end of each instruction cycle, 8086 checks to

see if any interrupts have been requested.

If an interrupt has been requested, the 8086 responds

to interrupt by stepping through the following series of

major steps:

1. It decrements the stack pointer by 2 pushes the flag

register on the stack.

2. It disables the 8086 INTR interrupt input by clearing

the interrupt flag(IF) in the flag register.

3. It resets the trap flag(TF) in the flag register.

4. It decrements the stack pointer by 2 and pushes the

current code segment register contents on the stack.



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5. It decrements the stack pointer again by 2 and

pushes the current instruction pointer contents on

the stack.

6. It does an indirect far jump to start of the procedure

by loading the CS and IP values for the start of the

interrupt service routine.

An IRET instruction at the end of the interrupt

service routine returns execution to main program.

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The 8086 gets the new values of CS and IP register from

four memory addresses.

When it responds to an interrupt, the 8086 goes to

memory locations to get the CS an IP values to start of

the interrupt service routine.

In an 8086 system the first 1 Kb of memory from 00000H

to 003FF is reserved for storing the starting addresses of

interrupt service routines.

This block of memory is often called the INTERRUPT

VECTOR TABLE or the INTERRUPT POINTER TABLE.

Since 4 bytes are required to store the CS and IP values

for each interrupt service procedure, the table can hold

the starting addresses for 256 interrupt service routines.

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Each interrupt type is given a number between 0 to 255 and the address of each interrupt is found by multiplying the type by 4 e.g. for type 11, interrupt address is 11×4=4410=0002CH

Only the first five types have explicit definitions. The next 27 interrupt types, from 5 to 31, are

reserved by Intel for use in future microprocessors. The upper 224 interrupt types, from 32 to 255,

available for user for hardware or software interrupts.

When 8086 responds to an interrupt, it automatically goes to specified location in the interrupt vector table to get the starting address of interrupt service routine.

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8086 Interrupts Types

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1. Divide by Zero Interrupt (Type 0):When the quotient from either a DIV or IDIV instruction is too large to fit in the result register; 8086 will automatically execute type 0 interrupt.

2. Single Step Interrupt (Type 1):The type 1 interrupt is single step trap. In the single step mode, system will execute one instruction and wait for further direction from user. The user can examine the contents of registers and memory locations and if they are correct, user can tell the system to execute the next instruction. This feature is useful for debugging assembly language programs.


8086 Interrupts Types Cont..

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3. Non Maskable Interrupt (Type 2):As the name suggests, this interrupt cannot be disabled by any software instruction. This interrupt is activated by low to high transition on 8086 NMI input pin. In response, 8086 will do a type 2 interrupt.

4. Breakpoint Interrupt (Type 3):The type 3 interrupt is used to implement breakpoint function in the system. The type 3 interrupt is produced by execution of the INT 3 instruction. Breakpoint function is often used as a debugging aids in cases where single stepping provides more details than wanted.

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5. Overflow Interrupt (Type 4):

The type 4 interrupt is used to check overflow

condition after any signed air thematic operation in

the system. The 8086 overflow flag, OF, will be

represented in the destination register or memory

location.



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Software Interrupts (Type 0-255):

The 8086 INT instruction can be used to cause 8086

to do one of the 256 possible interrupt types.

The interrupt type is specified by the number as a

part of the instruction.

You can use an INT 2 instruction to send execution

to NMI interrupt service routine.

This allows you to test the NMI routine without

needing to apply an external signal to the NMI input

of the 8086.

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Maskable Interrupt (INTR):

The 8086 INTR input can be used to interrupt a

program execution.

This interrupt is implemented by using two pins

INTR and INTA


Introduction to DOS and BIOS Interrupts

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In IBM PC, part of the operating system is located in

the permanent memory(ROM) and part is loaded

during power up.

The part located in ROM is referred to as ROM-

BIOS(Basic Input/ Output System).

The other part which is loaded in RAM during power-

up from hard disk is known as DOS(Disk Operating

System).

BIOS is located in a 8 Kbyte ROM at the top of

memory, the address range being from FE000H to

FFFFFH.

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Introduction to DOS and BIOS Interrupts Cont..

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The programs with ROM-BIOS provide the mostdirect, lowest level interaction with the various devicesin the system.

The ROM-BIOS contains routines for1. Power-on self test2. System configuration analysis3. Time of the day4. Print screen5. Boot strap loader6. I/O support program for

a. Asynchronous communicationb. Keyboardc. Printerd. Display



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Most of these programs are accessible to ALP throughsoftware interrupt instruction(INT).

The design goal for the ROM-BIOS programs is to providea device-independent interface to the various physicaldevices in the system.

Using ROM-BIOS one can output characters to variousphysical devices like the printer or display, one can readcharacter from keyboard.

But still few things are not possible with ROM-BIOS1. It is not possible to provide ability to load and execute

programs directly.2. It is not possible to store data on the diskette organized

as logical files.3. ROM-BIOS has no command-interpreter to allows to

copy files, print files, delete files.

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It is the DOS that provides these services.

When we turn our computer on, we expect to see

message or a prompt.

We expect to be able to look at the diskette directory

to see what data files or programs the diskette

contains.

We expect to run a program by typing name.

We want to copy programs from one diskette to

another, print programs and delete programs.

All these services are provided by group of programs

called DOS.



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The services provided by DOS can be grouped into

following categories.

1. Character Device I/O: This group include routines

that input or output characters to character oriented

devices such as printer, the display monitor and the

keyboard.

2. File Management: This group include routines that

manage logical files, allowing you to create, read,

write and delete files.

3. Memory Management: This group include routines

allows us to change, allocate and deallocate

memory.

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4. Directory Management: This group include routines that

permit us to create, change search and delete

directories.

5. Executive Functions: This group include routines that

allow us to load and execute programs, to retrieve error

codes from completed programs and execute commands

6. Command Interpreter: this routine is in action whenever a

prompt is present on the screen. It interprets commands

and executes DOS functions, utility programs, application

programs depending upon the command.

7. Utility Programs: These programs facility to copy, delete,

provides the DISKCOPY, DIR and many other DOS

commands.



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No DOS BIOS

1. DOS is loaded from the bootable

diskette.

BIOS is located in an 8 Kbyte ROM.

2. DOS program offer different

degree of flexibility, portability

and hardware independence.

The programs with in the ROM-BIOS

provide the most direct, lowest level

interaction with the various devices

in the system. Using these programs

require hardware knowledge.

3. DOS has ability to load and

execute programs directly.

ROM-BIOS does not have ability to

load and execute programs directly.

4. DOS can store data on the

diskette organized as a logical

files.

ROM-BIOS cannot store data on the

diskette organized as a logical files.

5. DOS has command interpreter to

allow us to copy files, print files

and delete files.

ROM-BIOS has no command

interpreter to allow us to copy files,

print files and delete files.

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The MS-DOS API is an API which originated with 86-

DOS and is used in MS-DOS/PC DOS and other DOS-

compatible operating systems. Most calls to the DOS API

are invoked using software interrupt 21H (INT 21H).

By calling INT 21h with a sub function number in the

AH processor register and other parameters in other

registers, one invokes various DOS services.

DOS services include keyboard input, video output, disk

file access, executing programs, memory allocation, and

various other things.



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AH Description AH Description

01 Read character from STDIN 02 Write character to STDOUT

05 Write character to printer 06 Console Input/ Output

07Direct char read (STDIN), no

echo08

Char read from STDIN, no

echo

09 Write string to STDOUT 0A Buffered input

0B Get STDIN status 0C Flush buffer for STDIN

0D Disk reset 0E Select default drive

19 Get current default drive 25 Set interrupt vector

2A Get system date 2B Set system date

2C Get system time 2D Set system time

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AH Description AH Description

2E Set verify flag 30 Get DOS version

35 Get Interrupt vector

36 Get free disk space 39 Create subdirectory

3A Remove subdirectory 3B Set working directory

3C Create file 3D Open file

3E Close file 3F Read file

40 Write file 41 Delete file

42 Seek file 43 Get/Set file attributes

47 Get current directory 4C Exit program

4D Get return code 54 Get verify flag

56 Rename file 57 Get/Set file date


Software Interrupt Applications

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The software interrupt instruction INT N can be used to testany type of interrupt procedure. For example to test a type64 interrupt procedure without the need for externalhardware, we can execute the instruction INT 64.

Another important use of software interrupts is to call BasicInput Output System, or BIOS, procedures in an IBM PC-type computer.

These procedures in the system ROMs perform specificinput or output functions, such as reading a character fromthe keyboard, writing some characters to the CRT, orreading some information from a disk.

To call one of these procedures, you load any requiredparameters in some specified registers and execute an INTN instruction. N in this case is the interrupt type whichvectors to the desired procedure.

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Software Interrupt Applications Cont..

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Suppose that, as part of an assembly language program

that you are writing to run on an IBM PC type computer,

you want to send some characters to the printer.

The header for the INT 17H procedure from the IBM PC

BIOS listing. The DX, AH, and AL registers are used to

pass the required parameters to the procedure.

The procedure is used for two different operations:

initializing the printer port and sending a character to the

printer.



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The operation performed by the procedure is determined

by the number passed to the procedure in the AH

register. AH=1 means initialize the printer port, AH=0

means print the characters in AL, and AH=2 means read

the printer status and returned in AH.

If an attempt to print a character was not successful for

some reason, such as the printer not being turned on, not

being selected, or being busy, 01 is returned in AH.

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The main advantage of calling procedures with software

interrupts is that you don't need to worry about the

absolute address where the procedure actually resides or

about trying to link the procedure into your program.

So at last every microcomputer system uses a variety of

interrupts and this is all about 8086 interrupts and

applications.


8259A Priority Interrupt Controller

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Interrupts can be used for a variety of applications.

Each of these interrupt applications require a separate

interrupt input.

If we are working with an 8086, we get only two interrupt

inputs INTR and NMI.

For applications where we have multiple interrupt

sources, we use external device called a priority interrupt

controller ( PIC)

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8259A Priority Interrupt Controller Cont..

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Features of 82591. It can manage eight priority interrupts. This is equivalent

to provide eight interrupt pins on the processor in place ofINTR pin.

2. It is possible to locate vector table for these additionalinterrupts any where in the memory map.

3. By cascading 8259s it is possible to get 64 priorityinterrupts.

4. Interrupt mask register makes it possible to maskindividual interrupt request.

5. With the help of 8259A user can get information ofpending interrupts, in-service interrupts and maskedinterrupts.

6. The 8259A is designed to minimize the software and realtime overhead in handling multilevel priority interrupts.

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8259A includes eight blocks

1. Data Bus Buffer

2. Read/ Write Logic

3. Control Logic

4. Three Registers(IRR, ISR and IMR)

5. Priority Resolver

6. Cascade Buffer

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1. Data Bus BufferThe data bus allows the 8086 to send control words to

8259A and read a status word from the 8259A. The 8-bit databus also allows the 8259A to send interrupt types to 8086.

2. Read/ Write LogicThe RD and WR inputs control the data flow on the data

bus when the device is selected by asserting its chip selectinput low.

3. Control LogicThis block has an input and output line. If 8259A is properly

enabled the interrupt request will cause 8259A to assert its INToutput pin high. If this pin is connected to the INTR pin of 8086and if 8086 interrupt flag is set, then this high signal cause the8086 respond INTR.



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4. Interrupt Request Register (IRR)The IRR is used to store all the interrupt levels which

are requesting service. The eight interrupt inputs setcorresponding bits of Interrupt Request Register.

5. Interrupt Service Register (ISR)The ISR stores all the levels that are currently being

serviced.

6. Interrupt Mask Register (IMR)The IMR stores the masking bits of the interrupt lines

to be masked. This register can be programmed by anOCW. An interrupt which is masked by software will notbe recognized and serviced even if it set correspondingbits in the IRR.

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7. Priority ResolverThe priority resolver determines the priorities of the

bits set in the IRR. The bit corresponding to the highestpriority interrupt input is set in the ISR during the INTAinput.

8. Cascade Buffer ComparatorThis section generates control signals necessary for

cascade operations. It also generates Buffer-Enablesignals. The 8259A can be cascaded with other 8259s inorder to expand the interrupt handling capacity to 64levels. In such case, the former is called a master, andthe latter are called slaves. The 8259 can set up as amaster or a slave by the /SP EN



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Interrupt sequence:1. One or more of the interrupt request lines (IR0-IR7) are

raised high, setting the corresponding IRR bits.

2. The priority resolver checks three registers: the IRR forinterrupt requests, the IMR for masking bits and the ISRfor the interrupt request being served. It resolves priorityand sets the INT high when appropriate.

3. The CPU acknowledges the INT and responds with INTApulse.

4. Upon receiving an INTA from the CPU, the highestpriority ISR bit is set and the corresponding IRR bit isreset. The 8259A does not drive data bus during thiscycle.

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Interrupt sequence:

5. A selection of priority modes is available to theprogrammer so that the manner in which requestsare processed by the 8259A can be configured tomatch his system requirements. The priority modescan be changed dynamically at any time during themain program.

6. The 8086 will initiate a second INTA pulse. Duringthis pulse 8259A releases interrupt type onto theDATA bus where it is read by CPU.

7. This completes the interrupt cycle. In the AEOI modethe ISR bit is reset at the end of the second INTApulse. Otherwise the ISR bit remains set until anappropriate EOI command is issued at the end ofinterrupt subroutine.



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Programming the 8259A:

The 8259A requires two types of command words.

1. Initialization Command Words(ICWs)2. Operational Command Words(OCWs)

The 8259A can be initialized with four ICWs; thefirst two are compulsory and the other two are optionalbased on the modes being used.

After initialization, the 8259A can be set up tooperate in various mode by using three different OCWs

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Flow chart:



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Initialization Command Word 1 (ICW1):

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Initialization Command Word 1 (ICW1):A write command issued to 8259A with A0=0 and

D4=1 is interpreted as ICW1, which starts theinitialization sequence.It specifies1. Single or multiple 8259As in the system.2. 4 or 8 bit interval between the interrupt vector

locations.3. The address bit A7-A5 to CALL instruction.4. Edge triggered or level triggered interrupts.5. ICW4 is needed or not.



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A write command following ICW1, with A0=1 is

interpreted as ICW2. This is used to load high order byte

of the interrupt vector address of all interrupts.

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Initialization Command Word 3 (ICW3):ICW3 is required only if there is more than one

8259A in the system and if they are cascaded. An ICW3operation loads a slave register in the 8259.

For master each bit in ICW3 is used whether ithas a slave 8259 attached to it on its corresponding IRinput.

For slave, bits D0-D2 of ICW3 are used to assigna slave identification code to the 8259A



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Initialization Command Word 4 (ICW4):It is loaded only if the D0 bit of ICW1 is set.



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It specifies1. Whether to use special fully nested mode or non

special fully nested mode.2. Whether to use buffered mode or non buffered

mode.3. Whether to use automatic EOI or normal EOI.4. CPU used, 8086/8088 or 80810.

After initialization the 8259A is ready toprocess the interrupt request. However during operationit might be necessary to change the mode of processingthe interrupts.

Operation Command Words(OCWs) are used forthis purpose

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Operation Command Word 1 (OCW1):A write command to the 8259 with A0=1 (after

ICW2) is interpreted as OCW1. OCW1 is used forenabling or disabling the recognition of specific interruptrequests by programming the IMR.



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Operation Command Word 2 (OCW2):A write command to the 8259 with A0=1 and

D4D3=00 is interpreted as OCW2.

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Operation Command Word 3 (OCW3):OCW3 is used to read the status of registers, and

to set or reset the Special Mask and Polled modes



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Priority Modes and Other Features:

The various modes of operation of the 8259 are:

a) Fully Nested Mode

b) Special Fully Nested Mode

c) Rotating Priority Mode

d) Special Masked Mode

e) Polled Mode

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a) Fully Nested Mode(FNM):

After initialization, 8259A operates in fully nested mode so it

is called default mode.The 8259A continues to operate in the Fully Nested Modeuntil the mode is changed through operation commandwords.In this mode, IR0 has highest priority and IR7 has lowestpriority.When the interrupt is acknowledged, it sets thecorresponding bit in ISR.The vector address corresponding to this interrupt is thensent.The bit in ISR remain set until an EOI command is issuedby the microprocessor at the end of the interrupt serviceroutine.



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But if AEOI(Automatic End of Interrupt) bit is set, the

bit in the ISR resets at the trailing edge of the last INTA.

End of Interrupt(EOI):

The IS bit can be reset by an End of Interrupt

command issued by the CPU, usually just before exiting

from the interrupt routine.

In the Fully Nested Mode, the highest level in the ISR

would necessarily correspond to the last interrupt

acknowledged and serviced. In such case a non-

specific EOI command may be issued by the CPU.

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However if the Fully Nested Mode, is not used, the 8259

may not be able to determine the last interrupt

acknowledged. In such case, a specific EOI command will

have to be issued by the CPU.

It should be noted that in the cascaded mode, the EOI

command must be issued twice, once for the master and

once for the slave.

Automatic End of Interrupt(AEOI):

If the AEOI mode is set, the 8259 will perform a non-

specific EOI on its own on the trailing edge of the third INTA

pulse.

The AEOI mode can only be used for a master 8259 not for

a slave.



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b) Special Fully Nested Mode(SFNM):

In the FNM, on the acknowledgment of an interrupt further

interrupts from the same level are disabled.

However in large systems which use cascaded 8259s and

where the interrupt levels within each slave have to be

considered.

An interrupt input to slave, in turn causes the slave to place

an interrupt request to the master on one of the master’s

inputs.

Further interrupts to slave will cause the slave to place

request to the master on the same input to the master, but

these will not be recognized because further interrupts on the

same input level are disabled by the master.

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The Special Fully Nested Mode avoid this problem.

The SFNM is set up during ICW4 during initialization.

It is similar to the FNM except for following differences:

i. When an interrupt request from slave is being serviced, the slave

is allowed to place further requests(these requests are of higher

priority than the request currently serviced). These interrupts are

recognized by the master and it initiates interrupt requests to

CPU.

ii.Before exiting from the interrupt service routine, a non-specific

EOI must be sent to slave and its ISR must be read to determine

if it was the only interrupt to the slave. If the ISR is empty, a non-

specific EOI command can be sent to the master. If it is not

empty, it implies that the same IR level input to the master is to be

serviced again due to more than one interrupt being presented to

the slave, and an EOI must not be sent to the master.



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(C) Rotating Priority Mode:

The Rotating Priority Mode can be set in

i. Automatic Rotation

ii. Specific Rotation

Automatic Rotation:

In this mode, a device after being serviced, receives the

lowest priority. Assuming that IR3 has just been

serviced, it will receive the seventh priority.

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Specific Rotation:

In Automatic Rotation mode, the interrupt request last

serviced is assigned the lowest priority where as in the

specific Rotation mode the lowest priority can be

assigned to any interrupt (IR0-IR7) thus fixes all other

priorities.

If the lowest priority is assigned to IR2, the other

priorities are



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(d) Special Mask Mode:

If any interrupt is in service then the corresponding bit is set

in ISR and the lower priority interrupts are inhibited.

Some applications may require an interrupt service routine

to dynamically alter the system priority structure during its

execution under software control for example the routine

may wish to inhibit lower priority requests for a portion of its

execution but enable some of them for another portion. In

these cases we have to go for SPECIAL MASK MODE.

In this mode it inhibits further interrupts at that level and

enables interrupts from all other levels( lower as well as

higher) that are not masked. Thus any interrupt may be

selectively enabled by loading the mask register.

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(e) Poll Mode:

In this mode the INT output is not used.

The microprocessor checks the status of interrupt

requests by issuing poll command.

The microprocessor reads content of 8259A after

issuing poll command.

During this read operation the 8259A provides polled

word and sets ISR bit of highest priority active interrupt

request FORMAT.



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(e) Poll Mode:

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Problem: Write the initialization instructions for

8259A interrupt controller to meet the following

specifications:

a) Interrupt type 32 b)Edge triggered, single and

ICW4 needed. c) Mask interrupts IR1 and IR3

Solution: when used with 8086, bit D2, D5, D6 and D7

are don’t care, so we make them 0’s for simplicity.



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ICW2: In an 8086 system ICW2 is used to tell the

8259A the type number to send in response to an

interrupt signal on the IR0 input.

For an IR1 input the 8259A will send 00100001 binary

(33 decimal) and so on for the other IR inputs

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ICW3: Since we are not using a slave in our example,

we don’t need to send an ICW3.

ICW4: For our example, the only reason to send an

ICW4 is to let the 8259A know that it is operating in an

8086 system. We do this by making bit D0 of the ICW4

ONE.

OCW1: An OCW4 must be sent to an 8259A to mask

any IR inputs.



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Program:

MOV AL,13H;edge triggered, single, ICW4 needed

OUT 40H,AL; Send ICW1

MOV AL,20H; type 32 is first 8259A interrupt type

OUT 41H,AL; send ICW2

MOV AL,01H; ICW4, 8086 mode

OUT 41H,AL; send ICW4

MOV AL,0AH; OCW1 to mask IR1 and IR3

OUT 41H,AL; send OCW1

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Direct Memory Access-8257

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In microprocessor based system data transfer can be

controlled by either software or hard ware.

In software controlled data transfer method

programmer executes a series of instructions to carry

out data transfer.


Direct Memory Access-8257 Cont..

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In hardware controlled data transfer technique

external device is used to control data transfer.

External device generates address and control signals

required to control data transfer and allows peripheral

device to directly access the memory.

This technique is referred to as DIRECT MEMORY

ACCESS.

The external device which controls the data transfer is

referred to as DMA CONTROLLER.



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Features of 8257

1. It is a programmable, 4-channel direct memory access

controller. Each channel can be programmed individually.

Therefore we can interface 4 input/output devices with 8257.

2. Each channel includes a 16-bit DMA address register and a 14-

bit counter. DMA address register gives the address of memory

location and counter specifies the number of DMA cycles to be

performed. As counter is 14-bit each channel can transfer

214(16 kb) without intervention of microprocessor.

3. It maintains the DMA cycle count for each channel and

activates a control signal TC(terminal count) to indicate the

peripheral that the programmed number of DMA cycles are

complete.

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Features of 8257

4. It provides another control signal MARK to indicate

peripheral that the current DMA cycle is the 128th

cycle since the previous MARK output.

5. It has the priority logic that resolves the peripheral

requests. The priority logic can be programmed to

work in two modes, either in fixed mode or rotating

priority mode.

6. It provides inhibit logic which can be used to inhibit

individual channels.

7. It allows data transfer in two modes: burst mode and

cycle steal(single byte) mode.



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Features of 8257

8. It can execute three DMA cycles: DMA read, DMA

write and DMA verify.

9. Auto load feature of 8257 permits repeat block or

block chaining operations.

10. It operates in two modes: slave and master.

11. It can be interfaced with all Intel microprocessors.

12. It can transfer one byte of data in four clock cycles.

Thus giving high transfer rate.

13. When DMA is in master mode, AEN signal provided

by 8257 allows to isolate CPU buffers, latches and

other devices from system bus.

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Data Bus Buffer:

It is a bi-directional, eight bit buffer which interfaces

the 8257 to the system bus.

In the slave mode, it is used to transfer data

between microprocessor and internal registers of

8257.

In master mode it is used to send higher byte

address (A8-A15) on the data bus.

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Read/Write Logic:

When the CPU is programming or reading one of the

internal registers of 8257(slave mode), the Read/Write

logic accepts the I/O Read or I/O write signal,

decodes the least significant four address bits(A0-A3)

and either writes the contents of data bus into the

address register or places the contents of address

register onto the data bus.

During DMA cycles(master mode) the Read/Write logic

generates the I/O read and memory write(DMA write

cycle) or I/O write and memory read(DMA read cycle

signals which control the data transfer between

peripheral and memory devices.

IOWIOR



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DMA Channels:

The 8257 provides four identical channels labeled

CH0 to CH3. each channel has two sixteen bit

registers:

i) A DMA address register

ii) A terminal count register

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DMA Address Register:

It specifies the address of first memory location to be

accessed.

It is necessary to load valid memory address in the

DMA address register before channel is enabled.



80

Terminal Count Register:

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Terminal Count Register:

The value loaded into lower order 14 bits(C13-C0) of

the terminal count register specifies the number of

DMA cycles minus one before the terminal

count(TC) output is activated.

The most significant 2 bits of the terminal count

register specifies the type of DMA operation to be

performed.

It is necessary to load count for DMA cycles and

operational code for valid DMA cycle in the terminal

count register before channel is enabled.



82

Control Logic:

It controls the sequence of operations during all

DMA cycles(DMA write, DMA read, DMA verify) by

generating the appropriate control signals and the

16-bit address that specifies the memory location to

be accessed.

It consists of two registers

1. Mode Set Register is programmed by CPU to

configure 8257

2. Status Register is read by CPU to check which

channels have reached terminal count condition and

status of update flag.

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1. Mode Set Register:

Least significant four bits of Mode Set Register

allows to enable each of the four DMA channels.

Most significant four bits allows four different options

for the 8257.



84

2. Status Register:

The TC status bit, if one indicates terminal count has

been reached for that channel.

The TC bit remains set until the status register is

read or the 8257 is reset.

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85

The update flag bit, if one indicates CPU that 8257 is

executing update cycle.

In update cycle 8257 loads parameters in channel3

to channel2.

Priority Resolver:

It resolves the peripherals requests.

It can be programmed to work in two modes

1. Fixed Mode

2. Rotating Priority Mode



86

Operating Modes of 8257

1. In rotating priority mode, the priority of the channels

has a circular sequence. In this channel being

serviced gets the lowest priority and the channel

next to its gets the highest priority.

2. In the fixed priority channel0 has the highest priority

and channel3 has lowest priority.

3. The extended write option provides alternative

timing for the I/O and memory write signals which

allows the devices to return an early READY and

prevents the unnecessary occurrence of wait states

in 8257.

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87

Operating Modes of 8257

4. If the TC STOP, bit is set, a channel is disabled after the

terminal count output goes high thus automatically

preventing further DMA operations on that channel.

5. Auto Load Mode when enabled, permits block chaining

operations, without immediate software intervention

between blocks. During the update cycle, it is necessary

to prevent the CPU from inadvertently skipping a data

block by overwriting a starting address or terminal count

in the channel3 registers before those parameters are

properly auto-loaded into channel2.


Interfacing and Refreshing Dynamic RAMs

88

For small systems we need only a few kilobytes of

RAM, we usually use static RAM devices because

they are very easy to interface to.

For large systems we want several hundred

kilobytes or mega bytes of memory, we use dynamic

RAMs, often called DRAMs.

Static RAMs store each bit in an internal flip flop

which requires four to six transistors.

In DRAMs a data bit is stored as a charge or no

charge on a tiny capacitor.

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Interfacing and Refreshing Dynamic RAMs Cont..

89

All that is needed in addition to the capacitor is a

single transistor switch to access the capacitor when

a bit is written to it or read from it.

The result of this is that DRAMs require much less

power per bit, many more bits can be stored in a

given chip.

This makes cost per bit of storage much less.

The disadvantage of DRAMs is that each stored bit

must be refreshed every 2 to 8 ms because the

charge stored on the tiny capacitors tends to change

due to leakage.



90

When activated by external signal, the refresh

circuitry in the device checks the voltage level stored

on each capacitor.

If the voltage is greater than Vcc/2, then that location

is charged to Vcc.

If the voltage is less than Vcc/2, then that location is

discharged to 0V.

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91

When activated by external signal, the refresh

circuitry in the device checks the voltage level stored

on each capacitor.

If the voltage is greater than Vcc/2, then that location

is charged to Vcc.

If the voltage is less than Vcc/2, then that location is

discharged to 0V.



92

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93

The system contains two 16Kbyte dynamic RAM

units.

All the address and data lines are assumed to be

available from an 8086 system.

The pin controls output data buffers of the

memory chips.

The CE pins are active high chip selects of memory

chips.

The refresh cycle starts, if refresh output of the

refresh timer goes high, and CE also tends to

go to high.

OE

OE



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The high CE enables the memory chip for

refreshing, while high prevents the data from

appearing on the data bus.

The 16K×1- bit dynamic RAM has an internal array

of 128×128 cells, requiring 7 bits for row addresses.

The lower order seven lines A0-A6 are multiplexed

with refresh counter output A10-A16.

Note: Now according to the basic rules of address

decoding, 14 address lines should be required to

address one of the 16K. The figure shows only 7

inputs A0-A6 .

OE

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95

The trick here is that to save pins, DRAMs usually

multiplex in the address one-half at a time.

To read a word from a bank of dynamic RAMs, a

DRAM controller asserts the write enable pin of the

DRAMs high to enable them for a read operation.

It then sends upper half of the address called the

row address to the 7 address inputs of DRAMs.

The controller then asserts row-address-strobe, RAS

input of the DRAM to low to latch row address in

DRAM.



96

After proper timing interval, the controller removes

the row address and outputs the lower half of the

address, called column address to the 7 address

inputs of DRAMs.

The controller then asserts the column-address-

strobe, CAS inputs of the DRAMs low to latch the

column address in the DRAMs.

After a propagation delay, the data word from the

addressed memory cells will appear on the data

outputs of DRAMs.

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97

The following are the main tasks to interface a bank

of DRAMs to a microprocessor:

1. Multiplex the two halves of the address into each

device with the appropriate RAS and CAS strobes.

2. Provide a read/write control signal to enable data

into or out of the devices.

3. Refresh each row at the proper interval.

4. Ensure that a read or write operation and refresh

operation do not take place at the same time.


8254 Software-Programmable Timer/Counter

98

It is not possible to generate an arbitrary time delay

precisely using delay routines.

Intel’s programmable counter/timer device facilitates

the generation of accurate time delays.

When 8254 is used as a timing and delay generation

peripheral, the microprocessor becomes free from

the tasks related to the counting process and can

execute the programs in memory, while the timer

device may perform the counting tasks.

This minimizes the software ahead on the

microprocessor.

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8254 Software-Programmable Timer/Counter Cont..

99



100

The programmable timer device 8254 contains three

independent 16-bit counters, each with a maximum

count rate of 8MHz.

It is thus possible to generate three totally

independent delays or maintain three independent

counters simultaneously.

All the three counters may be independently

controlled by programming the three internal

command word registers.

The 8-bit bidirectional data buffer interfaces internal

circuit of 8254 to microprocessor system bus.

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101

Data transmitted or received by buffer depend upon

the execution of IN or OUT instruction.

The Read/Write logic controls the direction of the

data buffer whether it is a read or write operation.

Three counters are all 16-bit resettable down

counters, able to operate either in BCD or in

hexadecimal mode.

A0 and A1 pins are the address input pins and are

required internally for addressing the mode control

word registers.



102

A control word register accepts the 8-bit control word

written by microprocessor and stores it for controlling the

complete operation of the specific counter.

You can apply a signal of any frequency dc to 8 MHz to

each of the counter clock inputs labeled CLK.

The GATE input on each counter allows you to start or

stop that counter with an external hardware signal.

If the GATE input is high, then that counter is enabled for

counting.

The output signal from is counter appears on its OUT pin.

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103

ADDRESS PINS

CONTROL WORD REGISTER



104

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Electronic Circuit Analysis Laboratory · Introduction to DOS and BIOS Interrupts Cont.. 22 No DOS...

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Transcript of Electronic Circuit Analysis Laboratory · Introduction to DOS and BIOS Interrupts Cont.. 22 No DOS...