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296 IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

Development of Power Interface With FPGA-Based

Adaptive Control for PEM-FC SystemAlben Cardenas, Member, IEEE, Kodjo Agbossou, Senior Member, IEEE, and Nilson Henao, Student Member, IEEE

AbstractThis paper presents the development of a power in-terface for a fuel cell (FC) system supplying an ac load. The pro-posed system comprises a two stages conditioning system, includ-ing a switched capacitor dcdc boost converter and a full bridgeinsulated-gate bipolar transistor (IGBT) single-phase inverter(dcac converter). A fully digital control structure is proposed tomanage both power converters using the same control device. Thecontrol strategy takes advantage of the parallelism of the field pro-grammablegate arrays (FPGA) technologyto share in real-time thecontrollers information addressing the common problem of low-frequency ripple of FC current when supplying ac loads. The con-trol system has been implemented and evaluated by co-simulation,and by experimentation with a proton exchange membrane fuel

cell (PEM-FC) system. The results show that the proposed systemallows a safe operation of the FC by limiting the current rippleunder 3%. These results also confirm that the transient responseof the conversion system permits to correctly supply the ac load.

Index TermsCurrent ripple, energy conversion, fuel cells(FCs), neural networks, power electronics, programmable logicarrays.

I. INTRODUCTION

FUEL CELLS (FCs) are nowadays proposed as clean en-

ergy sources for stationary and mobile power applications.

Commonly stationary applications of FC are stand-alone and

grid-tied power systems [1], [2]. Power conditioning systems

(PCSs) are employed to interface FC voltage with ac loads. The

PCS includes a dcdc boost converter to adapt the FC dc output

voltage, which is normally below 50 V, to a higher dc voltage,

and a dcac converter in order to produce the ac voltage to

supply the load.

Low-frequency current ripple is a commonly related problem

in the literature, which appears when FC systems are employed

to supply ac loads. Several studies have proven that the cur-

rent ripple affects the FC life duration, as well as the available

output power and its efficiency [3][6]. Those studies on one

hand reveal that an energy-efficient operation of an FC system

imposes that the current ripple must be limited to 20%. On the

Manuscript received February 3, 2014; revised May 30, 2014 and August11, 2014; accepted August 13, 2014. Date of publication September 4, 2014;date of current version February 16, 2015. This work was supported in partby the Laboratoire des Technologies de lEnergie LTE-Hydro-Quebec, theBureau de lefficacite et de linnovation energetiques du Quebec, and theNatural Science and Engineering Research Council of Canada. Paper no. TEC-00075-2014.

The authors are with the Departement de Genie electrique et Genie In-formatique, Hydrogen Research Institute, University of Quebec at Trois-

Rivieres (UQTR), Trois-Rivieres, QC G9A 5H7, Canada (e-mail: [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TEC.2014.2349653

other hand, in order to reduce the impact of the current ripple

on the FC conditions, the ripple must be controlled below 4%.

Current ripple can be reduced by adding intermediary stor-

age systems including capacitors, ultra capacitors or batteries.

However, this option increases the overall cost of the PCS. Alter-

natively, design strategies of voltage and current feedback loops

and power electronics circuitry have been proposed to reduce

the low-frequency ripple of FC current [7][14]. It is to remark,

that most of the strategies, proposed to reduce the current ripple,

have been only analyzed on steady-state operation.

Recently, progress in very large scale integration (VLSI) tech-

nologies have permitted the introduction of field programmable

gate arrays (FPGAs) as new target devices for a wide variety of

applications, including signal processing, information technol-

ogy, telecommunication, and control. FPGAs are semiconductor

devices with high density of programmable resources, includ-

ing memory and logic operators, arranged as configurable logic

blocks (CLBs), which can be reconfigured allowing the parallel

processing of different functions. The FPGA is considered a

promising technology in control and signal processing applica-

tions [15][18], mainly because it permits the implementation

of several applications inside a single device, allowing multi-

threats and multicore processing systems, eliminating the real-

time communication constraints of multiple processors controlsystems.

This paper presents the development and control of a power

electronics interface for an FC power source supplying an ac

load; the developed system includes the power electronics cir-

cuits and the FPGA implementation of the control algorithms

for the PCS. The proposed control algorithms, embedded in

one FPGA device, offer good transient response and a signif-

icant reduction of the FC current ripple. Hardware-in-the-loop

(HIL) co-simulation and experimental results are provided to

corroborate the validity of the proposed system.

This paper is organized as follows. Section II presents the

developed power electronics system. Section III describes theproposed control algorithms. Sections IV and V present the HIL

co-simulation and the experimental results. Section VI provides

some concluding remarks.

II. POWERELECTRONICSINTERFACE FORPROTONEXCHANGE

MEMBRANEFUELCELL(PEM-FC)

Fig. 1 illustrates blocks diagram of the PCS used to interface a

PEM-FC with an ac load. As previously mentioned, FC systems

present low output voltage, normally up to tens of volts, and the

peak ac voltage of hundreds of volts.

The output voltage of the FC system (Hydrogenics HyPM XR

8 FC power module) used in this study varies between 20 and

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CARDENASet al.: DEV ELO PMEN T O F P OWER INTE RFAC E WITH FP GA-BA SED ADAP TIVE CONT ROL FOR P EM-FC S YS TEM 2 97

Fig. 1. Block diagram of FC interface.

Fig. 2. Minimal dcdc gain for different FC voltage.

40 V according to its operational characteristics (output power,

temperature, etc.) [19]. The development of high-gain boost

dcdc converters is essential to integrate green power sources

with low output voltage, like the renewables and FCs, into

the utility grid or to directly supply high-voltage loads

[20][28].

The minimum input voltage Vdc for a the single-phaseinvertercan be defined by

VDC L >

2

Vac

|cos(R )

| (1)

where Vac is the root-mean-square (rms) ac voltage and R is therated phase angle. This relation must be satisfied to maintain the

sinusoidal current waveform [29]. Normally, Vdc is set higherthan

2 Vac , above 170 V for a 120-V single-phase inverter.

So the minimum gain of the dcdc converter can vary according

to the FC voltage as illustrated in Fig. 2.

The dcdc converters without intermediary storage system

employ a high-voltage capacitor (HVC). This capacitor must be

well chosen to allow enough energy storage to ensure a proper

operation of the inverter. The inverter input voltage is supplied

by this capacitor and must be kept within the low and high

operating limits VDC L and VDC H , respectively. The dischargingtime (D ) of the HVC from the high to the low dc voltage limitsVD CH andVDC L can be computed by

D > (1/2)CHV C

V2D CH V2DC L

PFC Pac PL (2)

wherePFC is the power coming from the FC,Pac is the powerof the ac load, and PL corresponds to the conversion losses. Thedifference between thePFC and the Pac + PL corresponds tothe discharging power.

The discharging times computed for different discharging

power, different VDC H values, VD CL = 180 V, and CHV C =2650F are plotted in Fig. 3. The results show that, ifVD CH

is 195 V and the discharging power is higher than 500 W, the

Fig. 3. Discharging time for different discharging power and different VD C H ,VD C L = 180 V andCH VC = 2650F.

Fig. 4. Comparison of discharging time for CH VC = 2650F and CH VC =6000F. Different discharging power, differentVD C H , andVD C L = 180V.

dc voltage falls below VD CL within one electric cycle. On theother hand, if VDC H is 220 V and the discharging power isthe same, the dc voltage falls below VDC L within 2.7 electriccycles.

A comparison of the discharging times for CHV C = 2650 FandCHV C = 6000F is presented in Fig. 4. It is observed thatthe discharging times obtained using 2650 F at VDC H = 220 Vare similar to the ones using 6000F at VD CH = 200V.

In this study, the PEM-FC is interfaced by means of a high-

gain, low-ripple dcdc switched capacitor boost converter as

proposed in [20][23] and a developed insulated-gate bipo-

lar transistor (IGBT) inverter as illustrated in Fig. 5. The

main characteristics of the conversion system are presented

in Table I.

The basic operation of the switched capacitor boost converter

(SCBC) has been discussed in detail in [23], where the authors

demonstrate that this converter topology is well adapted whenrequiring low input current ripple, low output voltage ripple,

and high voltage gain, as required in our case. The static gain of

the SCBC can be computed using the duty cycle (D) by

G= 2

1 D . (3)

The control of the dcdc and dcac power electronics con-

verters when the system operates as autonomous power source

must allow a good transient response and a steady-state behav-

ior according to the standards [30]; moreover, as mentioned ear-

lier, the low-frequency ripple of FC current must be controlled

to be below 4%. In particular, the 120-Hz oscillation must be


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Fig. 5. General diagram of the developed power electronics interface for PEM-FC system.

TABLE I

SYSTEMCHARACTERISTICS

Description Value

PEM-FC

HydrogenicsHyPMXR8

Rated power 8 kW

DC output voltage 2035 V

DCDC converter

Type One-Stage Switched Capacitor Boost

Converter

Working input voltage range 2035 V

Maximum output voltage 250 V

Input capacitor (LVC) 1000 F

Input inductors (L1,L2 ) 1.4 mH

Switched capacitors (SC1, SC2) 1000 F

Output capacitor (C3) 10 FFilter inductor (L3) 0.8 mH

Filter capacitor (HVC) 2650 F

Switching frequency 6 kHz

Power switching devices: Ultrafast diode

IGBT

FFH60UP40S APT75GN120LG

DCAC Converter

Bridge Type IGBT Power Module (PS21A7A)

Rated voltage/current 600 V/30 A

Nominal dc-source voltage 200 V

Operating voltage/frequency 120 V/60 Hz

Switching frequency 10 kHz

Filter and Line Impedance

Filter inductor (L D 1 +L D 2) 1.6 mH

Filter capacitor (Cf) 20 F

Coupling Inductor(Lo) 1 mH

Line impedance (L, R) 1.17 H, 17.6 m

In this study, the output power of the FC system is limited to 3 kW. Line impedance corresponds to load connection cable.

limited. This ripple limitation is necessary to prevent damage or

premature degradation of the FC.

III. PROPOSEDVOLTAGE ANDCURRENTCONTROL

The control of power electronics interface is divided in two

parts, the first one is the ac voltage control and the second one

is the dc voltage and current control.

Fig. 6. Simplified diagram of the control structure of dcac converter basedon VF-ADALINE with FLL [31].

A. AC Voltage Control

The ac voltage control implemented in this study is based

on the ADALINE&FLL [31]. This control scheme offers good

transient and steady-state behavior and has been previously eval-

uated with linear and nonlinear loads. A simplified diagram of

the control structure is presented in Fig. 6.

In this voltage control structure, the instantaneous signal er-

ror (S) is computed as the difference between the reference


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and the measured signal (4), and compensated by means of a

proportional controller with gainKPa c (5)

S(k) = VRE F (k) VC(k) (4)CS(k) = KPa c S(k). (5)

The error of the orthogonal components of voltage (W0 and

W1 ) is compensated by means of a proportional and integral(PI) controller with gainsKPd c and KId c .

CW0 (k) = KPd c W0 (k) + KId ck

= 0

W0 () (6)

CW1 (k) = KPd c W1 (k) + KId ck

= 0

W1 (). (7)

The compensation signal [see (8)] is then the result of the

partial compensations of (5), (6), and (7)

CT(k) =CS(k) +CW0 (k)

sin(2

f

k

TS)

+CW1 (k)cos(2 f k TS) (8)where the sines and cosines signals are generated by the VF-

DDS. The modulating signalVPW M can be obtained from thereference voltage and the signal compensation using the follow-

ing:

VPW M (k) =VRE F (k) + CT(k). (9)

B. DC Voltage and Current Control

This section focuses on the control stage, which is devoted to

maintain the output voltage of the dcdc converter at a desired

value (input voltage of the inverter) in order to guarantee a

correct operation of whole system, even if the FC voltage and

the load power change.

The voltage control of the dcdc converter can be obtained

by means of two modified PI controllers as illustrated in Fig. 7.

The first one acts as a voltage controller (10), and the second

one as current controller (11). The rms current absorbed by the

ac load Irm s is estimated by means of the VF-ADALINE&FLL,and it is fed back and used to anticipate the current set point for

the dcdc converter

IFC R = (VD CR VD CM )

KPV +KIV

s

+ Irm s Gdc

(10)

D= (IFC R IFC M )

KPI +KII

s

(11)

whereGdc is the actual dc gain of system computed by usingthe actual FC and dc-link voltages using

Gdc = VDC M

VFC. (12)

As illustrated in Fig. 7, the feedback variables, like the dc-

link voltage (Vdc ), the load current (Irm s ), and the FC currentand voltage (IFC ,VFC ), are filtered by means of the auxiliaryADALINE low-pass filter bank (ADALINE-LPF). This filter

bank is synchronized with the ac load frequency by means

Fig. 7. Proposed control structure of dcdc and dcac converters for the acvoltage control of an FC system.

of the ADALINE&FLL permitting to eliminate the harmonic

components present on the measured signals and improving the

transient and the steady-state controller behavior. The estimatedsignal using the ADALINE-LPF can be represented by

y(k) =W(k)T X(k) (13)where Xis the input pattern vector considering a numberNof

harmonics and defined by

X(k) =

1sin(2 f k TS)cos(2 f k TS)

.

.sin(2

N

f

k

TS)

cos(2 N f k TS)

(14)

whereTs is the sampling period of the direct digital synthesisblock (DDS);Wis the weight vector, which is updated consid-

ering the estimation errore(k) and the learning factor using

W(k+ 1) =W(k) +

N e(k) X(k) . (15)

The mean or dc signal can be the computed by

ydc (k) =W(0, k) X(0, k) (16)eliminating the ac components present on the measured signal,

which are directly related with the harmonics of the ac load

current.


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The proposed method, as other proposed techniques, permits

to reduce the ripple of the FC current by subtracting the low-

frequency components of the feedback voltage signal; however,

the accurate load frequency tracking and the harmonics de-

composition are special characteristics of the ADALINE-LPF

allowing a much better reduction of the ripple present on the

feedback signals and without negative impact on the dynamic

performance of the controller. In contrast to classic solutions as

using proportional-resonant (PR) controllers or bandpass filters

(BPFs), tuned at a fixed frequency [7], [11], the adaptive prop-

erty of the method proposed in this study permits to operate

the system at a fixed load frequency or at a variable frequency;

consequently, it can be widely used for a stand-alone microgrid

or connected to the main grid mode.

It is to highlightthat classic solutionsonly consider the120 Hz

(or 100 Hz) as the component to be attenuated or eliminated.

Some techniques permit to eliminate the 120 Hz component but

generate otherharmonic components[13]. Additionally, modern

ac loads may introduce other non-negligible harmonic compo-

nents which must be also eliminated of the feedback signals.

C. DC Voltage Droop Scheme

As illustrated in Figs. 3 and 4, the HVC discharging and

charging times are mainly dependent on two parameters: the

capacity and the voltage. Hence, if low-capacity and fixed

Vdc are employed, the capacitor voltage regulation can belargely affected by the load fluctuations if the FC transient re-

sponse is not fast enough. A dc voltage droop scheme is pro-

posed to improve the transient response of converter without

increasing the capacity of HVC. This voltage droop scheme

can be defined by

VD CR =VDC N + mdc (PNO M Pac ) (17)where VD CR isthesetpointofVdc ; VDC N is the nominal value ofVdc ; Pac is the measured load ac power; PNO M is the rated powerof the FC (or dcac converter); and mdc is the droop coefficient(in volts per watt). In the dc-droop scheme, the operating voltage

at the rated power corresponds to the nominal value, and higher

operating voltages are set for operating powers under the rated

power. In other words,if thesystem is working at very low power

the dc-link voltage is set at its highest value; consequently, if

the power demand increases the dc-link voltage naturally falls

down. Otherwise, when the system is working at its maximum

power the dc-link voltage is set at its lowest value; thus, if thepower demand falls down the dc-link voltage naturally rises.

The controllers gains can be obtained offline from the trans-

fer function of the system by means of the SISO design or

PID tuner graphical user interfaces (GUIs) of MATLAB soft-

ware (MATLAB-SISOTool or MATLAB-PIDTool); tuning of

PI controller can be also obtained online by automatic tuning

techniques [32].

IV. HIL CO-SIMULATIONRESULTS

The proposed control system of FC power electronic inter-

face has been implemented and evaluated by HIL co-simulation

using the Xilinx Virtex-5 XC5VLX110T FPGA as target device

TABLE I IMAINCHARACTERISTICS OFMEASUREMENTSYSTEM

Description (Units) Value

Measurement and Control System

Sample time of measurement system ( s) 10

FPGA clock period (ns) 10

ADALINE-FLLNumber of analyzed harmonics 32

DDS sample time T0 ( s) 1

Number of implemented WVU T0 3

WVU T0 learning factor 0.1

FLL gainG F L L 3.5

FLL sampling period TF L L ( s) 10 s

FLL error threshold M I N 0.1

FLL sliding window period TS W (ms) 20

Fig. 8. HIL co-simulation results of (a) current and (b) voltage ripple whenthe mean FC current is 90 A. Controllers use tuning 1.

[33]. The main characteristics of the measurement system and

the implemented ADALINE-FLL are presented in Table II.

The operation of the FC system has been evaluated for dif-

ferent loading conditions. Fig. 8 shows the plot of FC cur-

rent and dc-link voltage waveforms when the system supply a

3-kW ac load with 120 V/60 Hz voltage. In order to analyze theperformance of the proposed control structure, the ripple factor

of the FC currentis computed by using

=IRipplerm s

IFCmean100% (18)

where IFCme an is the mean value of the FC current andIRipplerm s is the rms value of the FC current ripple. In thesame way, the dc-link voltage ripple factor is also computed.

Two different tunings of the integral gain for the current con-

troller (KI I) have been used. Using the characteristics presentedin Table III, tuning 1 offers faster response than tuning 2. The

HIL co-simulation results of Fig. 8 are obtained using tuning 1,


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TABLE I IISETUP OFCONTROLLERSUSED IN THEHIL CO-SIMULATION

Description Tunning 1 Tunning 2

DC Voltage Controller

DC current controller (KP I,KI I) 0.005,5 0.005,1

DC voltage controller (KP V,KI V ) 1, 0.01 1, 0.01

Vd c nominal 200 V 200 VOperatingVd c (Vm i n Vm a x) 170240 V 170240 V

DC voltage droop (m d c ) 3.3 mV/W 3.3 mV/W

Controller sample time 10 s 10 s

AC Voltage Controller

Signal error controller (KP a c ) 1 1

Orthogonal components controller (KP d c ,KId c ) 0.0432, 42.35 0.0432, 42.35

Controller sample time 250 s 250 s

Switching frequency 6 kHz 6 kHz

Fig. 9. HIL co-simulation results of (a) current and (b) voltage for differentpower of ac load. Controllers use tuning 2.

the ripple factor of FC current and voltage are 2.95% and 2.1%,

respectively.

Fig. 9 shows the results for the transient response of the

FC system using tuning 2; in this test, the inverter is started

at t= 100 ms with an initial ac load of 100 W; also at thetimest = 300ms,t = 800ms, andt = 1.3s, the load power isincreased each time of 500 W. Fig. 9(a) shows the FC current,

and Fig. 9(b) shows the dc-link voltage (at HVC). The effect of

the voltage droop scheme on the dc-link voltage, following the

variations of the output power of the system, is well illustrated in

this figure. These results show a good behavior of the controller.

Fig. 10 shows the results of the ripple factor of the FC current for

different load power and considering the two different tunings

of the integral gain of current controller (KI I). According to

these results, the ripple factor is always under 3% and meet

Fig. 10. HILco-simulation results of currentripple fordifferent ac load power.

TABLE IVCOMPARISON OFFC CURRENTRIPPLE ANDCAPACITORSIZE

Description References [8], [9] This study

Low vol tage capacitor (LVC) 6600 F 1000 F

Switching capacitors (SC1+SC2)

2000 F

HVC 2200 F 2650 FRated power (staticconverters)

1.20 kW 3 kW

LVC+ SC capacitor/power 5.5 F/W 1 F/W

HVC capacitor/power 1.83 F/W 0.88 F/W

Steady-state current ripple 2.0% 2.95% (Tuning 1) 2.05%

(Tuning 2)

the recommended ripple limits (


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TABLE VSUMMARY OFRECENTLYPROPOSEDCURRENTRIPPLEMITIGATION

TECHNIQUES

Year Technique Characteristics

2010 Dual-loop dcdc converter control

with BPF [11]

Experiments show that the technique

permits to reduce the current ripple to

4%. The dcdc converter used in thisstudy consists of a current fed

pushpull converter with auxiliary

circuit (flyback converter).

2010 DC-active filter with a center tap

[12].

With this technique, the ripple current

can be decreased to 20% compared to

the conventional circuit (without

compensation). Experiments show an

input current total harmonic distortion

(THD) over 10%, depending on the

output power.

2013 Waveform contr ol [ 13]. Exper im ents show a 100 Hz curr ent

ripple of 11.9% for a dc current of

1.84 A. A 200 Hz current ripple of

8.9% appears. THD of ac voltage is

slightly increased. Ripple of dc-link

voltage (or FC voltage) is not

presented.

2014 Feed-forward control scheme[14]. The 120 Hz component of inputcurrent is reduced to 0.3%.

Peak-to-peak ripple current is 1.32 A

(3.2% of 14.4 A). DC-link voltage

ripple is 27 V (7.63% of 250 V).

Fig. 11. Real view of the implemented SCBC.

voltage gain (G) for different duty cycle (D). The experimen-tal results of the static gain of the dcdc converter are plotted

in Fig. 13 for the open-loop operation, and in Fig. 14, for the

closed loop. The obtained experimental values are close to those

of the theory obtained by using (3). The experimental gain is

lower than the theoretical value, which can be explained by the

converter losses.

B. Inverter Load Operation

The operation of the FC system has been validated with dif-

ferent ac load conditions. The first test has been carried out by

using optimal tuning of classic PI controllers for the current and

voltage loops obtained by the classic ZieglerNichols rule with

Fig. 12. Real view of the implemented test bench of FC power system.

Fig. 13. Experimental dcdc static gain of converter prototype operating inopen loop.

Fig. 14. Experimental results of static gain of the dcdc converter working inclosed loop at two different operation points, Vdc = 180V andVdc = 200 V.

MATLAB-SISOTool. Fig. 15 presents the results of FC and ac

load currents; it is observed that the current ripple is over 4%

even if, in that case, the power is low (Iac rm s = 4.2A).The proposed controller, illustrated in Fig. 7, has been also

evaluated for different operating powers; the current ripple has

been computed for each case by postprocessing using MATLAB

software from data collected by means of the user interface

(Windows-MATLAB-Xilinx). Fig. 16 presents a summary of

the experimental results of FC current ripple for different ac

load power corresponding to different mean FC current (limited

to 40 A). It is to remark that the ripple factor remains well

under 4% and near to 2% confirming the results obtained by

co-simulation.


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Fig. 15. Experimental results of inverter load operation at low load power(Iac rm s = 4.2 A) (classic control withoptimal controller tuningusing Ziegler-Nichols rule with MATLAB SISOTool).

Fig. 16. Experimental results of current ripple for different ac load power (theproposed control scheme using tuning 2).

Fig. 17 provides the plots of the measured voltages (dc link,

FC, and ac load) and currents (dcdc converter, FC, and ac

load), when the mean FC current is 25.6 A (corresponding to a

sinusoidal load current of 7 A rms); in this case, the computed

FC current ripple is 1.85%. The plots of the measured voltagesand currents when the mean FC current is 39.9 A (corresponding

to a sinusoidal load current of 11 A rms) are shown in Fig. 18;

in this case, the computed FC current ripple is 1.99%.

C. Evaluation of the Conversion Efficiency

The efficiency of the power electronics converter has been

experimentally evaluated for different operating powers; the re-

sults, plotted in Fig. 19, show a mean efficiency of over 94%.

D. Evaluation of Dynamic Performance

The dynamic performance of the proposed strategy has been

experimentally verified confirming that the transient response

of the voltage controller is kept fast enough to maintain the dc-

link voltage and to warrant a correct ac load supply. Figs. 20

and 21 show the experimental results applying a transient load

power by switching ON (see Fig. 20) and OFF (see Fig. 21) a

commercial light bulb. The reference of dc-link voltage was in-

tentionally set to 196 V (


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Fig. 18. Experimental results of inverter load operation at low load power(IFC m e a n = 39.9A). (a) Voltage waveforms and (b) current waveforms withthe proposed control scheme using tuning 2.

Fig. 19. Experimental results of converters efficiency (the proposed controlscheme using tuning 2).

function; the obtained result is 96 ms, which corresponds to a

time constant of 24.6 ms (considering a first-order approxima-

tion and a tacking error of 2%). In the results, it is important to

remark that the system presents a time constant lower than two

electric cycles.

Also, it must be highlighted that in this study the bandwidth

of the voltage control loop was set to 5 Hz, which permits a

good tracking of the reference voltage; most of literature works

use bandwidths lower than 10 Hz (much lower than 120 Hz) for

the voltage control loop, e.g., the strategy of ripple reduction

proposed in [8] and [9] has been evaluated with a bandwidth of

voltage control loop of 1.2, 2, and 4 Hz, and the best results were

obtained when 1.2 Hz was employed. In this study, a higher

bandwidth is possible due to the use of the ADALINE low-

pass filter bank, which permits to reduce the 120 Hz ripple of

the voltage feedback signal without important delay improving

Fig. 20. Experimental results of transient response (a) dc-link voltage regula-tion, and (b) FC current and voltage. Power transient of150 W by switchingOFF a commercial light bulb.

Fig. 21. Experimental results of transient response (a) dc-link voltage regula-tion, and (b) FC current and voltage. Power transient of+150 W by switchingON a commercial light bulb.


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Fig. 22. Experimental results of voltage controller response face to steps onthe reference voltage: (a) dc-link voltage response; and (b) FC current andvoltage.

the transient response and mitigating the steady-state ripple of

the FC current.

VI. CONCLUSIONThe development of a power interface for an FC system sup-

plying an ac load has been presented. The proposed system

includes a prototype of dcdc and dcac converters, and all the

control is implemented in FPGA. The proposed control includes

the ADALINE&FLL structure implemented in hardware, which

is used to control in parallel both the inverter and the SCBC.

Additionally, a dc voltage droop scheme is adopted to improve

the response of the dcdc converter even with the low size of

the HVC.

The proposed system has been experimentally validated

showing manyadvantages compared with classic solutions some

of them are the low current ripple, the fast transient response,and a reduced dc-link capacitor compared to the classic and

recently proposed alternative solutions.

All control blocks have been embedded in a single FPGA

device, working in parallel and sharing in real time the main

variables information. This fact demonstrates the validity and

potential of the proposed system by using modern digital control

systems.

ACKNOWLEDGMENT

The authors would like to thank the Xilinx University Pro-

gram for the hardware, software, and technical support.

REFERENCES

[1] K. Agbossou, M. Kolhe, J. Hamelin, and T. K. Bose, Performance ofa stand-alone renewable energy system based on energy storage as hy-

drogen, IEEE Trans. Energy Convers., vol. 19, no. 3, pp. 633640,Sep. 2004.

[2] A. Cardenas and K. Agbossou, Experimental evaluation of voltage pos-itive feedback based anti-islanding algorithm: Multi-inverter case, IEEETrans. Energy Convers., vol. 27, no. 2, pp. 498506, Jun. 2012.

[3] W. Choi, P. N. Enjeti, J. W. Howze, and G. Joung, An experimental eval-uation of the effects of ripple current generated by the power conditioningstage on a proton exchange membrane fuel cell stack, J. Mater. Eng.Performance, vol. 13, no. 3, pp. 257264, 2004.

[4] M.E. Schenck, J.-S.Lai, andK. Stanton, Fuelcelland powerconditioningsystem interactions, in Proc. 20th Annu. IEEE Appl. Power Electron.

Conf. Expo., 2005, pp. 114120.[5] P. Thounthong, B. Davat, S. Rael, and P. Sethakul, Fuel cell high-

power applications, IEEE Ind. Electron. Mag., vol. 3, no. 1, pp. 3246,Mar. 2009.

[6] R. S. Gemmen, Analysis for the effect of inverter ripple current on fuelcell operation condition, J. Fluids Eng., vol. 125, no. 3, pp. 576585,2003.

[7] S. K. Mazumder, R. K. Burra, and K. Acharya, A ripple-mitigating andenergy-efficient fuel cell power-conditioning system,IEEE Trans. Power

Electron., vol. 22, no. 4, pp. 14371452, Jul. 2007.

[8] C. Liu and J.-S. Lai, Low frequency current ripple reduction techniquewith active control in a fuel cell power system with inverter load, IEEETrans. Power Electron., vol. 22, no. 4, pp. 14291436, Jul. 2007.

[9] C. Liu and J.-S. Lai, Low frequency current ripple reduction techniquewith active control in a fuel cell power system with inverter load, in Proc.

IEEE 36th Power Electron. Spec. Conf., 2005, pp. 29052911.[10] L. Xiaohu, W. Zhan, and L. Hui, A new fuel cell power conditioning

system with extended life time and minimized DC-buscapacitor, in Proc.28thAnnu.IEEE Appl. PowerElectron.Conf. Expo., 2013, pp.19261930.

[11] R. Bojoi, C. Pica, D. Roiu, and A. Tenconi, New DCDC converterwith reduced low-frequency current ripple for fuel cell in single-phasedistributed generation, in Proc. IEEE Int. Conf. Ind. Technol., 2010,pp. 12131218.

[12] J.-I. Itoh and F. Hayashi, Ripple current reduction of a fuel cell for asingle-phase isolated converter using a dc active filter with a center tap,

IEEE Trans. Power Electron., vol. 25, no. 3, pp. 550556, Mar. 2010.[13] G.-R. Zhu, S.-C. Tan,Y. Chen, andC. K.Tse, Mitigation oflow-frequency

current ripple in fuel-cell inverter systems through waveform control,IEEE Trans. Power Electron., vol. 28, no. 2, pp. 779792, Feb. 2013.

[14] J.-H. Kim, K.-Y. Choi, and R.-Y. Kim, A low frequency input currentreduction scheme of a two-stage single-phase inverter with DCDC boostconverter, inProc. 29th Annu. IEEE Appl. Power Electron. Conf. Expo.,2014, pp. 23512358.

[15] E. Monmasson, L. Idkhajine, M. N. Cirstea, I. Bahri, A. Tisan, andM. W. Naouar, FPGAs in industrial control applications, IEEE Trans

Ind. Informat., vol. 7, no. 2, pp. 224243, May 2011.[16] P. Patel and M. Moallem, Reconfigurable system for real-time embedded

control applications,IET Control Theory Appl., vol. 4, no. 11, pp. 25062515, Nov. 2010.

[17] C.Sepulveda, J.Munoz,J. R. Espinoza,M. Figueroa, andC. Baier,FPGAv/s DSP performance comparison for a VSC-based STATCOM control

application, IEEE Trans Ind. Informat., vol. 9, no. 3, pp. 13511360,Aug. 2013.

[18] A. Cardenas, C. Guzman, and K. Agbossou, Development of a FPGAbased real-time power analysis and control for distributed generationinterface, IEEE Trans. Power Syst., vol. 27 no. 3, pp. 13431353,Aug. 2012.

[19] HyPM-XR-8 Installation, Operation and Maintenance Manual , Rev. 2,Hydrogenics Corp., Mississauga, ON, Canada, 2010.

[20] B. Axelrod, Y. Berkovich, and A. Ioinovici, Switched-capacitor/switched-inductor structures for getting transformerless hybrid DCDCPWM converters, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55,no. 2, pp. 687696, Mar. 2008.

[21] B. Axelrod, Y. Berkovich, A. Shenkman, and G. Golan, Diode-capacitorvoltage multipliers combined with boost-converters: Topologies and char-acteristics,IET Power Electron., vol. 5, no. 6, pp. 873884, Jul. 2012.

[22] L. Wuhua, L. Xiaodong, D. Yan, L. Jun, and H. Xiangning, A review ofnon-isolated high step-up DC/DC converters in renewable energy appli-cations, in Proc. 24th Annu. IEEE Appl. Power Electron. Conf. Expo.,2009, pp. 364369.


11/11


[23] R. Gules, L. L. Pfitscher, and L. C. Franco, An interleaved boost DCDC converter with large conversion ratio, in Proc. IEEE Int. Symp. Ind.

Electron, 2003, pp. 411416.[24] X. Hu and C. Gong, A high voltage gain DCDC converter integrating

coupled-inductor and diodecapacitor techniques, IEEE Trans. PowerElectron., vol. 29, no. 2, pp. 789800, Feb. 2014.

[25] K.-I. Hwu and T.-J. Peng, High-voltage-boosting converter with chargepump capacitor and coupling inductor combined with buckboost con-verter,IET Power Electron., vol. 7, no. 1, pp. 177188, 2014.

[26] Y. Tang, T. Wang, and Y. He, A switched-capacitor-based active-networkconverter with high voltage gain,IEEE Trans. Power Electron., vol. 29,no. 6, pp. 29592968, Jun. 2014.

[27] Y.-P. Hsieh, J.-F. Chen, L.-S. Yang, C.-Y. Wu, and W.-S. Liu, High-conversion-ratio bidirectional dcdc converter with coupled inductor,

IEEE Trans. Ind. Electron., vol. 61, no. 1, pp. 210222, Jan. 2014.

[28] W. Li, W. Li, X. Xiang, Y. Hu, and X. He, High step-up interleavedconverter with built-in transformer voltage multiplier cells for sustain-able energy applications, IEEE Trans. Power Electron., vol. 29, no. 6,pp. 28292836, Jun. 2014.

[29] M. Ohshima and E. Masada, The P, Q controllable domain of a singlephase PWM converter to preserve sinusoidal AC current waveform, inProc. 29thAnnu. IEEEPower Electron. Spec.Conf., 1998, pp.16121618.

[30] IEEE Standard for Interconnecting Distributed Resources with ElectricPower Systems, IEEE Standard 1547-2003, Jul. 2003.

[31] C. Guzman, A. Cardenas, and K. Agbossou, Control of voltage source

inverter using FPGA implementation of ADALINE-FLL, in Proc. 38thAnnu. Conf. IEEE Ind. Electron. Soc., 2012, pp. 30373042.

[32] K. H. Ang, G. Chong, and Y. Li, PID control system analysis, de-sign, and technology,IEEE Trans. Control Syst. Technol., vol. 13, no. 4,

pp. 559576, Jul. 2005.[33] Xilinx Inc. (2013, May). Xilinx University Program XUPV5-

LX110T Development System [Online]. Available: http://www.xilinx.com/univ/xupv5-lx110t.htm

Alben Cardenas (S09M12) received the B.S.degree in electronic engineering from the AntonioNarino University, Villavicencio, Colombia, in 2003,and the M.S. and PhD. degrees in electrical engineer-

ing from the Universite du Quebec a Trois-Rivieres(UQTR), Trois-Rivieres, QC, Canada, in 2008 and2012, respectively.

He is currently a Researcher at the Hydrogen Re-search Institute (HRI), and a Lecturer in the Electri-cal and Computer Engineering Department, UQTR.His current research interests include renewable en-

ergy, distributed generation, power electronics, and very large scale integration(VLSI) technologies for energy conversion and power quality applications.

Dr. Cardenas is a Member of the Ordre des Ingenieurs du Quebec, and a

Member of the IEEE Power and Energy Society and the IEEE Industrial Elec-tronics Society.

Kodjo Agbossou (M98SM01) received the B.S.,M.S., and Ph.D. degrees in electronic measurements

from the Universite de Nancy I, Nancy, France, in1987, 1989, and 1992, respectively.

He is currently the Head of the Engineer-ing School, Universite du Quebec a Trois-Rivieres(UQTR), Trois-Rivieres, QC, Canada. Hewasa Post-doctoral Research Fellow in the Electrical Engineer-ing Department, UQTR (19931994), where he wasa Lecturer (19971998). Since 1998, he has been anAssociate Professor, and since 2004, he has been a

Full Professor in the Electrical and Computer Engineering Department, UQTR.He was the Head of the Electrical and Computer Engineering Department. Hewas also the Director of Graduate Studies in Electrical Engineering. He is theauthor or coauthor of more than 180 publications and has 4 patents. His current

research include in the areas of renewable energy, smart grid, integration ofhydrogen production, storage and electrical energy generation system, hybridelectrical vehicle, control, and measurements. He is a member of the HydrogenResearch Institute and Research group Group de reserche en electronique in-dustrielle (GREI), UQTR.

Dr. Agbossou is a Member of the IEEE Power and Energy Society, the In-dustry Applications Societies, the Communications Society, and the IndustrialElectronics Society Technical Committee on Renewable Energy Systems. Hewas the Chair of the IEEE Section Saint Maurice, QC, Canada. He is a Profes-sional Engineer and joined the Ordre des Ingenieurs du Quebec in 1998.

Nilson Henao (S14) received the B.S. degree inelectronics engineering from the Universidad de losLlanos, Villavicencio, Colombia, in 2010, and theM.Sc. degree in electrical engineering from the Uni-

versity of Quebec at Trois-Rivieres (UQTR), Trois-Rivieres, QC, Canada in 2013, where he is currentlyworking toward the Ph.D. degree with the Depart-ment of Electrical and Computer Engineering.

Hiscurrent research interestsinclude fuelcellcon-trol andoptimization, andenergy management forhy-brid electric vehicles. He is currently involved in ma-

chine learning techniques for nonintrusive appliance load monitoring (NIALM)to disaggregate and track device electrical signatures.

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