7/18/2019 Elec2602 2010 Final Exam

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Faculty of Engineering and Information TechnologiesSchool of Electrical and Information Engineering

ELEC2602 Digital Systems DesignSemester 1 2010

Time Allowed: 2 hours

INSTRUCTIONS TO CANDIDATES

• This exam contains four questions. All questions should be attempted. Each question isworth a total of 25 marks.

•  All questions are to be answered in the same book

• Non-programmable calculators are allowed

• This is a closed book examination

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Question 1 Boolean Algebra (25 marks)

The truth table for a full adder is below. Inputs are a, b and cin, and the outputs are coutand s.

a b cin cout s

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

a. (5 marks) Write a Boolean expression for the cout output.

b. (5 marks) Draw a schematic diagram for an implementation of the s output using onlyinverters, three-input AND gates and two-input OR gates.

c. (5 marks) Write a Boolean expression for an implementation of the s output using onlyinversion and NOR operators.

d. (5 marks) Draw a schematic diagram for an implementation of a 4-bit adder using thisfull adder as a subcircuit using an appropriate symbol for the full adder. The inputsshould be labelled cin, a0-a3 and b0-b3. The outputs should be labelled s0-s3 and cout.Marks will be deducted for solutions which are excessively complex or long.

e. (5 marks) If the delay from any input to any output of a full adder is 1 unit of time. Whatis the maximum propagation delay for a 4-bit adder from input to the cout signal? Forwhat inputs does worst-case propagation delay occur? Explain your answer.

Question 2 Latches and Flip-flops (25 marks)

a. (5 marks) Explain using a timing diagram, the difference between synchronous andasynchronous reset in an edge-triggered D-type flip flop.

b. (5 marks) When does metastability occur in flip-flops? Explain using a timing diagram.

c. (5 marks) Draw the schematic for a positive edge-triggered master-slave D flip-flopusing two D-type latches and other logic. Marks will be deducted for solutions which are

excessively complex or long.

d. (10 marks) Draw a schematic diagram of a 4-bit binary counter. The circuit should haveone clock input clk, and four outputs q0, q1, q2 and q3. It should be positive edge-

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triggered and built entirely from D flip-flops and simple logic gates. All flip-flops musthave their clock inputs connected directly to clk.

Question 3 VHDL (25 marks)

a. (5 marks) The entity for a 2-input AND gate is given below. Write the corresponding

architecture in behavioural VHDL. The name of the entity should be “and2”.

library IEEE;use IEEE.STD_LOGIC_1164.all;entity and2 isport (a, b: in std_logic;

y: out std_logic);end and2;

b. (10 marks) Write an architecture-entity pair for a 4-input AND gate using only the “and2”devices in part a. The name of the entity should be “and4”. Make sure you declare“and2” as a component and the description is a structural one (zero marks will beawarded for a behavioural description).

c. (10 marks) Write the architecture-entity pair for a positive edge-triggered 8-bit binarydown counter in VHDL. The counter has a single clock input and produces a singlestd_logic_vector output q. Marks will be deducted for solutions which are excessivelycomplex or long.

Question 4 State Machines (25 marks)

a. (5 marks) A 3-bit Gray code counter advances on positive clock edges and generates

outputs in the sequence: 000, 001, 011, 010, 110, 111, 101, 100. Draw the assignedstate table for a state machine implementing this counter.

b. (10 marks) For the Gray code counter in part a, derive (unoptimised) equations for thenext state as a function of the current state.

c. (10 marks) Consider the following sequence detector. In each clock cycle, one bit isreceived on serial_in. When the three most-recently received bits are “101”, thesequence detector should output a 1 on z. Otherwise, it should output a 0.

Draw a state diagram for a state machine implementation of the sequence detector.Marks will be deducted for solutions which are excessively complex. Clearly state anyassumptions you make.

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