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ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11
ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design
Spring 2014Spring 2014Power and GroundPower and Ground
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
ECE Department, Auburn UniversityECE Department, Auburn University
Auburn, AL 36849Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
ReferencesReferences Q. K. Zhu, Q. K. Zhu, Power Distribution Network Design for VLSIPower Distribution Network Design for VLSI, Hoboken, New , Hoboken, New
Jersey: Wiley, 2004.Jersey: Wiley, 2004. M. Popovich, A. Mezhiba and E. G. Friedman, M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution Power Distribution
Networks with On-Chip Decoupling CapacitorsNetworks with On-Chip Decoupling Capacitors , Springer, 2008., Springer, 2008. C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and
Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), T. Cheng (Editors), Electronic Design AutomationElectronic Design Automation, Morgan-Kaufmann, , Morgan-Kaufmann, 2009. pp. 751-850.2009. pp. 751-850.
J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip VLSI On-Chip Power/Ground Network Optimization Considering Decap Leakage Power/Ground Network Optimization Considering Decap Leakage Currents,” Currents,” Proc. Asia and South Pacific Design Automation Conf.Proc. Asia and South Pacific Design Automation Conf. , , 20052005 , pp. 735-738., pp. 735-738.
Decoupling Capacitors, Decoupling Capacitors, http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/decoupling-capacitors.html
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 22Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Supply VoltageSupply Voltage
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 33
3.0
2.5
2.0
1.5
1.0
0.5
0.00.25 0.18 0.13 0.1
Minimum feature size (μm)
Sup
ply
volta
ge (
V)
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Gate Oxide ThicknessGate Oxide Thickness
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 44
60
50
40
30
20
10
00.25 0.18 0.13 0.1
Minimum feature size (μm)
Gat
e ox
ide
thic
knes
s (A
)
High gate leakage
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Power Supply NoisePower Supply Noise
Transient behavior of supply voltage and ground Transient behavior of supply voltage and ground level.level.
Caused by transient currents:Caused by transient currents: Power droopPower droop Ground bounceGround bounce
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 55Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Power SupplyPower Supply
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 66
+
–
Gat
e 1
Gat
e 2
VDD
Rg
R
C
R
C
V(t)
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Switching TransientsSwitching Transients Only Gate 1 switches (turns on):Only Gate 1 switches (turns on):
V(t) = VDD – Rg VDD exp[– t/C(R+Rg)]/(R+Rg)V(t) = VDD – Rg VDD exp[– t/C(R+Rg)]/(R+Rg)
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 77
V(t
)
VDD
0 time, t
VDD Rg/(R+Rg)
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Multiple Gates SwitchingMultiple Gates Switching
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 88
Gat
e ou
tput
vol
tage
VDD
0 time, t
many
Number of gates switching
1 23
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Decoupling CapacitorDecoupling Capacitor A capacitor to isolate two electrical circuits.A capacitor to isolate two electrical circuits. Illustration: An approximate model:Illustration: An approximate model:
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 99
+
–
VDD = 1Rg
Rd
CdIL
VL(t)
t
i(t)
a
t=0
t=0
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Approximate Load Current, ILApproximate Load Current, IL
0,0, t < 0t < 0
at,at, t < tpt < tp
ILIL ==
a(2tp – t),a(2tp – t), t < 2tpt < 2tp
0,0, t > 2tpt > 2tp
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1010Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Transient Load VoltageTransient Load Voltage
VL(t) = 1 – a Rg [ t – Cd Rg (1 – eVL(t) = 1 – a Rg [ t – Cd Rg (1 – e – t/T – t/T) ], 0 < t < tp) ], 0 < t < tp
TT == Cd (Rg + Rd)Cd (Rg + Rd)
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1111Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Realizing Decoupling CapacitorRealizing Decoupling Capacitor
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1212
GND
S B D
VDD
GND
S B D
VDD
OR
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
CapacitanceCapacitanceCdCd == γ×γ×WLWL×ε×ε×ε×ε00/Tox/Tox
≈≈ 0.26fF, for 70nm BSIM0.26fF, for 70nm BSIM
LL == 38nm,38nm, WW == 200nm200nm
γγ == 1.54621.5462
εε == 44
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1313Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Leakage ResistanceLeakage Resistance
IgateIgate == αα ×× e e – – ββToxTox ××WW
where where αα and and ββ are technology parameters. are technology parameters.
RdRd == VL(t)/IgateVL(t)/Igate
Because V(t) is a function of time, Rd is Because V(t) is a function of time, Rd is difficult to estimate. The decoupling difficult to estimate. The decoupling capacitance is simulated in spice.capacitance is simulated in spice.
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1414Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Power-Ground LayoutPower-Ground Layout
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1515
Vss VssVdd
VssVddVdd
Solder bump pads
M5
M4
Via
Vdd/Vss supply
Vdd/Vssequalization
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Power GridPower Grid
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1616
+
–
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Nodal AnalysisNodal Analysis
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1717
V1
V2
V3
V4
Ci
Vi
BiApply KCL to node i:
4 ∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bik=1
g1g2
g3
g4
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Nodal AnalysisNodal Analysis
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1818
G V – C V’ = B
Where G is conductance matrixV is nodal voltage vectorC is admittance matrixB is vector of currents
V(t) is a function of time, V(0) = VDD
B(t) is a function of time, B(0) ≈ 0 or leakage current
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Wire Width ConsiderationsWire Width Considerations
Increase wire width to reduce resistance:Increase wire width to reduce resistance: Control voltage drop for given currentControl voltage drop for given current Reduce resistive lossReduce resistive loss
Reduce wire width to reduce wiring area.Reduce wire width to reduce wiring area. Minimum width restricted to avoid metal Minimum width restricted to avoid metal
migration (reliability consideration).migration (reliability consideration).
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1919Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
A Minimization ProblemA Minimization Problem
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2020
Minimize total metal area: n n
A = ∑ wi si = ∑ | ρ Ci si2 | / xi
i=1 i=1
Where n = number of branches in power networkwi = metal width of ith branchsi = length of ith branchρ = metal resistivityCi = maximum current in ith branchxi = voltage drop in ith branch
Subject to several conditions.
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Condition 1: Voltage DropCondition 1: Voltage Drop
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2121
Voltage drop on path Pk:
∑ xi ≤ Δvk
i ε Pk
Where Δvk = maximum allowable voltage drop on kth path
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Condition 2: Minimum WidthCondition 2: Minimum Width
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2222
Minimum width allowed by fabrication process:
wi = ρ Ci si / xi ≥ W
Where wi = metal width of ith branchsi = length of ith branchρ = metal resistivityCi = maximum current in ith branchxi = voltage drop in ith branchW = minimum line width
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Condition 3: Metal MigrationCondition 3: Metal Migration
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2323
Do not exceed maximum current to wire-width ratio:
Ci / wi = xi /(ρ si) ≤ σi
Where wi = metal width of ith branchsi = length of ith branchρ = metal resistivityCi = maximum current in ith branchxi = voltage drop in ith branchσi = maximum allowable current density
across ith branch
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Decoupling CapacitanceDecoupling Capacitance
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2424
+
–
VDDRg
Cd I(t)
Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Decoupling CapacitanceDecoupling Capacitance
Initial charge on Cd, QInitial charge on Cd, Q00 = Cd VDD = Cd VDD
I(t): current waveform at a nodeI(t): current waveform at a node T: duration of currentT: duration of current Total charge supplied to load:Total charge supplied to load:
TT
Q = ∫ I(t) dtQ = ∫ I(t) dt
00
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2525Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Decoupling CapacitanceDecoupling Capacitance
Assume that charge is completely supplied by Cd.Assume that charge is completely supplied by Cd. Remaining charge on Cd = Cd VDD – QRemaining charge on Cd = Cd VDD – Q Voltage of supply node = VDD – Q/CdVoltage of supply node = VDD – Q/Cd For a maximum supply noise For a maximum supply noise ΔΔVDDmax,VDDmax,
VDD – (VDD – Q/Cd) ≤ VDD – (VDD – Q/Cd) ≤ ΔΔVDDmaxVDDmax
OrOr CdCd ≥≥ Q /Q / Δ ΔVDDmaxVDDmax
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2626Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
A High-Voltage On-Chip Power A High-Voltage On-Chip Power Distribution Network Distribution Network
June 28, 2013
Master’s Thesiswww.eng.auburn.edu/~vagrawal/THESIS/SHIHAB/Mustafa_Thesis.pdf
Mustafa M. Shihab
Auburn UniversityECE Department
June 2013
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2727Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Power Distribution ‘Grid’:
Source: N. Weste et al., CMOS VLSI design: A Circuits and Systems ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2828Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
2929
Take Away: For a 100 mile long line carrying 1000 MW of energy @ 138 kV power loss = 26.25%@ 345 kV power loss = 4.2%@ 765 kV power loss = 1.1% to 0.5%Source:
“American Electric Power Transmission Facts “, http://bit.ly/11nUMvf
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3030
I2R Loss in On-Chip Power Distribution Network:
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Propose a scheme for delivering power to different parts Propose a scheme for delivering power to different parts of a large integrated circuit, such as cores on a system-of a large integrated circuit, such as cores on a system-on-chip (SoC), at a higher than the regular (Von-chip (SoC), at a higher than the regular (VDDDD) voltage. ) voltage.
The increase in voltage will lower the current on the The increase in voltage will lower the current on the grid, and thereby reduces the Igrid, and thereby reduces the I22R loss in the on-chip R loss in the on-chip power distribution network.power distribution network.
3131ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3232ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3333ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3434
Example: Low-Voltage (VDD) Power Grid with 9 loads
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3535
Example: High-Voltage (3V) Power Grid with 9 loads
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3636
Number of Loads
Load Power
(W)Grid Power
(W)
Total Power
(W)Efficiency
(%)1 1 0.13 1.13 88.504 4 0.67 4.67 85.659 9 1.69 10.69 84.19
16 16 3.57 19.57 81.7625 25 7.02 32.02 78.0864 64 23.76 87.76 72.93
100 100 49.32 149.32 66.97256 256 169.4 425.4 60.18
Supply Voltage: 1V, Load: 1WGrid Resistances: 0.5 Ω (ITRS 2012)
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3737ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3838ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
3939
Number of Loads
Load Power
(W)
Grid Power (W)
Total Power
(W)
H-V PDN Efficiency
(%)1 1 0.01 1.01 98.584 4 0.07 4.07 98.179 9 0.19 9.19 97.96
16 16 0.40 16.40 97.5825 25 0.78 25.78 96.9764 64 2.64 66.64 96.04
100 100 5.48 105.48 94.80256 256 18.82 274.82 93.15
Supply Voltage: 3 V, Load: 1WGrid Resistances: 0.5 Ω (ITRS 2012)DC-DC Converter: LTC 3411-A Linear Technology, 100% Efficiency
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4040ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4141ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Number of Loads
Load Power
(W)Grid Power
(W)
Total Power
(W) Efficiency (%)1 1 0.02 1.02 98.044 4 0.11 4.11 97.329 9 0.39 9.39 95.85
16 16 1.21 17.21 92.9725 25 2.68 27.68 90.3264 64 9.12 73.12 87.53
100 100 18.97 118.97 84.05256 256 63.3 319.3 80.18
Supply Voltage: 3 V, Load: 1WGrid Resistances: 0.5 Ω (ITRS 2012)DC-DC Converter: LTC 3411-A Linear Technology, 80% Efficiency
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4242Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4343ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4444ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4545
Number of Loads
Load Power (W)
PDN Grid Power Loss (W)Low-
Voltage PDN
High-Voltage (100% Eff. Converter)
High-Voltage (80% Eff.
Converter)1 1 0.13 0.01 0.024 4 0.67 0.07 0.119 9 1.69 0.19 0.39
16 16 3.57 0.40 1.2125 25 7.02 0.78 2.6864 64 23.76 2.64 9.12
100 100 49.32 5.48 18.97256 256 169.40 18.82 63.3
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4646ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4747
Number of Loads
Grid Efficiency (%)
Low-Voltage PDN
High-Voltage PDN
(100% Eff. Converter)
High-Voltage PDN
(80% Eff. Converter)
1 88.50 98.58 98.044 85.65 98.17 97.329 84.19 97.96 95.85
16 81.76 97.58 92.9725 78.08 96.97 90.3264 72.93 96.04 87.53
100 66.97 94.80 84.05256 60.18 93.15 80.18
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
4848ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
DC-DC Converter Design:DC-DC Converter Design:EfficiencyEfficiency
PowerPowerAreaArea
Output Drive CapacityOutput Drive CapacityFabricationFabrication
4949ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Input Voltage: 3.3 VInput Voltage: 3.3 V Output Voltage: 1.3 V – 1.6 VOutput Voltage: 1.3 V – 1.6 V
Output Drive Current: 26 mAOutput Drive Current: 26 mA
Efficiency: 75% - 87% Efficiency: 75% - 87%
Input Voltage: 3.6 V & 5.4 VInput Voltage: 3.6 V & 5.4 V Output Voltage: 0.9 VOutput Voltage: 0.9 V
Output Drive Current: 250 mAOutput Drive Current: 250 mA
Efficiency: 87.8% & 79.6%Efficiency: 87.8% & 79.6%
5050
Sources:
B. Maity et al., Journal of Low Power Electronics 2012V. Kursun et al., Multi-voltage CMOS Circuit Design. Wiley, 2006
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
Have the capability of driving output loads of reasonable sizeHave the capability of driving output loads of reasonable size Have power efficiency of 90% or higherHave power efficiency of 90% or higher Meet the tight area requirements of modern high-density ICsMeet the tight area requirements of modern high-density ICs Be fabricated on chip as a part of the SoCBe fabricated on chip as a part of the SoC Have ‘regulator’ capability to convert a range of input Have ‘regulator’ capability to convert a range of input
voltage to the designated output voltagevoltage to the designated output voltage
5151
Future WorkFuture Work
DC-DC Converters
ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .
D. Chinnery and K. Keutzer, D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC and Custom: Tools Closing the Power Gap Between ASIC and Custom: Tools and Techniques for Low Power Designand Techniques for Low Power Design. Springer, 2007.. Springer, 2007.
M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual Low Power Methodology Manual for System-on-Chip Designfor System-on-Chip Design. Springer, 2007.. Springer, 2007.
V. Kursun and E. Friedman, V. Kursun and E. Friedman, Multivoltage CMOS Circuit DesignMultivoltage CMOS Circuit Design. Wiley, 2006. . Wiley, 2006. C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and
Process Compensation Over Different Technology Generations," Process Compensation Over Different Technology Generations," Proc. International Proc. International Symp. Low Power Electronics and DesignSymp. Low Power Electronics and Design, 2003, pp. 116-121., 2003, pp. 116-121.
B. C. Paul, A. Agarwal, and K. Roy, "Low-Power Design Techniques for Scaled B. C. Paul, A. Agarwal, and K. Roy, "Low-Power Design Techniques for Scaled Technologies,“ Technologies,“ Integration, the VLSI JournalIntegration, the VLSI Journal, vol. 39, no. 2, pp. 64-89, 2006., vol. 39, no. 2, pp. 64-89, 2006.
"Linear Technology: LT3411A DC-DC Converter Demo Circuit @ONLINE,“ Nov. 2011."Linear Technology: LT3411A DC-DC Converter Demo Circuit @ONLINE,“ Nov. 2011. M. Pedram and J. M. Rabaey, M. Pedram and J. M. Rabaey, Power Aware Design MethodologiesPower Aware Design Methodologies. Springer, 2002.. Springer, 2002. M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, “On-Chip Power Distribution M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, “On-Chip Power Distribution
Grids with Multiple Supply Voltages for High-Performance Integrated Circuits," Grids with Multiple Supply Voltages for High-Performance Integrated Circuits," IEEE IEEE Trans. Very Large Scale Integration (VLSI) SystemsTrans. Very Large Scale Integration (VLSI) Systems , vol. 16, no. 7, pp. 908-921, 2008. , vol. 16, no. 7, pp. 908-921, 2008.
Q. K. Zhu, Q. K. Zhu, Power Distribution Network Design for VLSIPower Distribution Network Design for VLSI. Wiley-Interscience, 2004.. Wiley-Interscience, 2004.
5252ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21 . . .Spring 2014, Mar 21 . . .