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European Journal of Scientific Research

ISSN 1450-216X Vol.39 No.4 (2010), pp.558-568

EuroJournals Publishing, Inc. 2010http://www.eurojournals.com/ejsr.htm

Implementation and Control of Variable Frequency ISPWM

Technique for an Asymmetric Multilevel Inverter

R.Seyezhai

Department of EEE, SSN College of Engineering, Chennai, Tamilnadu, India

E-mail: [email protected]

Tel: +91-044 27475065; Fax: +91-04427475063

B.L.Mathur

Department of EEE, SSN College of Engineering, Chennai, Tamilnadu, India

E-mail: [email protected]

Tel: +91-044 27475065; Fax: +91-04427475063

Abstract

Multilevel inverter is an effective and practical solution for increasing power andreducing harmonics of ac waveforms. Several multilevel topologies are reported and the

most popular topology is Cascaded Multilevel Inverter (CMLI). This paper focuses on

asymmetric cascaded multilevel inverter employing variable frequency inverted sine PWM

technique (VFISPWM). This technique combines the advantage of inverted rectified sinewave and variable frequency carriers for a seven level inverter for balancing the switch

utilization. A detailed study of the technique was carried out through

MATLAB/SIMULINK for switching losses and THD. Furthermore, a PI controller is usedto control the MLI using the proposed PWM technique. The results were verified

experimentally and FPGA processor is used for PWM. It was noticed that the proposed

modulation strategy results in lower switching losses for a chosen THD as compared to theconventional strategies.

Keywords: Asymmetric Multilevel Inverter, Variable frequency ISPWM, Switching Loss.

1. IntroductionMultilevel inverters are mainly utilized to synthesize a desired voltage wave shape from several levels

of dc voltages. Their main advantaged are low harmonic distortion of the generated output voltage, lowelectromagnetic emissions, high efficiency capability to operate at high voltages and modularity. Three

topologies have been reported for multilevel inverters: Diode- clamped, flying capacitor and cascaded

H-bridge [1].The topology considered for this work is the cascaded H-bridge inverter which requiresseveral independent dc sources. Normally, each phase of a cascaded multilevel inverter requires n dc

sources for 2n+1 level. For many applications, multiple dc sources are required demanding long cables

and this could lead to voltage unbalance among the dc sources. With an aim to reduce the number of dcsources required for the cascaded multilevel inverter for a motor drive, this paper focuses on

asymmetric cascade MLI that uses two unequal dc sources in each phase to generate a seven level

equal step multilevel output [2]. This structure is favourable for high power applications since itprovides higher voltage at higher modulation frequencies (where they are needed) with a low switching

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Implementation and Control of Variable Frequency ISPWM Technique for

an Asymmetric Multilevel Inverter 559

(carrier) frequency. It means low switching loss for the same total harmonic distortion (THD). It also

improves the reliability by reducing the number of dc sources.

For the cascaded multilevel inverter there are several well known sinusoidal pulse widthmodulation strategies [3].Compared to the conventional triangular carrier based PWM, the inverted

rectified sine carrier PWM has a better spectral quality and a higher fundamental output voltage

without any pulse dropping [4]. However, the fixed frequency carrier based PWM affects the switch

utilization in multilevel inverters. In order to balance the switching duty among the various levels ininverters, a variable frequency carrier based PWM has been suggested [5].

This paper however, presents a novel variable frequency inverted rectified sine modulation

technique (VFISPWM) for a seven level inverter. This novel method combines the advantage ofinverted sine and multi frequency carrier signals. The VFISPWM provides an enhanced fundamental

voltage, lower total harmonic distortion (THD) and minimizes the switch utilization among the various

levels in inverters. In this method the control signals have been generated by comparing sinusoidalreference signal with a high frequency inverted sine carrier. The carrier frequencies are so selected that

the number of switching in each band are equal. The proposed modulation technique maximizes the

output voltage and gives a low THD of 5.92%. A PID controller is employed to enhance the performance of the asymmetric MLI using the proposed modulation strategy. A comparative

evaluation between the VFISPWM and the conventional modulation is also presented in terms ofoutput voltage quality, power circuitry complexity, and total harmonic distortion (THD), weighted totalharmonic distortion (WTHD) and implementation cost. Both the MLI circuit topology and its new

control scheme are described in detail and their performance is verified based on simulation and

experimental results.

2. Asymmetric Cascaded Multilevel InverterThe seven - level cascaded multilevel inverter consists of two H-Bridges. The first H-Bridge H1

consists of a separate DC source Vdc, whereas the second H-Bridge H2 consistsof a dc source Vdc/2 as

shown in Fig.1. Let the output of H-Bridge-1 be denoted as v1(t) and the output of H-Bridge-2 be

denoted as v2(t). Hence the total output voltage is given by v(t)=v1(t)+v2(t).By alternately opening andclosing the switches S1,S4 and S2,S3 of H-Bridge-1 appropriately, output of H1v1(t) can be made equal

to +Vdc, 0 or -Vdc. Similarly the output voltage of H-Bridge-2 v2(t) can be made equal to Vdc/2, 0 or

+Vdc/2 by opening and closing the switches of H2 [14].Hence v(t) takes values -3/2Vdc, -Vdc, -1/2Vdc, 0,+1/2Vdc, +Vdc, +3/2Vdc as shown in the Fig.2.

Figure 1: Asymmetric Cascaded Multilevel Inverter

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560 R.Seyezhai and B.L.Mathur

The advantages of the topology are:

Reduced number of dc sources. High speed capability Low switching loss High conversion efficiency.

Figure 2: Output Voltage Waveform of Asymmetric Cascaded Seven Level Inverter.

Time (ms)

Amplitude(V)

3. Proposed Variable Frequency Inverted Sine PWM Technique (VFISPWM)The proposed control strategy replaces the conventional fixed frequency carrier waveform [6] by

variable frequency inverted sine wave. The inverted sine PWM has a better spectral quality and ahigher fundamental voltage compared to the triangular based PWM.But the main drawback is the

marginal boost in the magnitude of lower order harmonics and unbalanced switch utilization. This is

overcome by employing variable frequency inverted sine carrier signals. In order to balance thenumber of active switching among the levels is to vary the carrier frequency based on the slope of the

modulating wave in each band. The frequency ratio for each band should be set properly for balancing

the switching action for all levels. The reference carrier frequency was chosen as 3950Hz as switchinglosses and THD both are low as shown in Fig.3.

Figure 3: Reference Switching Frequency vs. THD (%) & switching Loss (mJ / Cycle) of the Conventional

PWM Technique.

0

2

4

6

8

0 2 4 6 8 10

Switch ing Frequency ( KHz)

THD(%)&WeightedSwitchingLoss

(%)

THD(%)

Sw. Loss (%)

3950Hz

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With the carrier reference frequency of 3950Hz applied to the band-1, the new frequencies for

bands 2 and 3 are assigned proportional to their respective slopes.

Figure 4: Reference modulating wave Three bands for different carrier frequency shown.

1 2 3 4 180 360

Amplitude(V)

Angle- (Degrees)

O

A

B

C

In Fig.4. the modulating wave is defined as

V (t) = Sin (1)

The calculation of the slope values for the three bands is shown below:

radiansSin 00 11 == - (2)

( ) radiansSin 339.03112 ==

- (3)

( ) radiansSin 728.03213 ==

- (4)

( ) radiansSin 5707.1114 ==

12

1

333.01

=== OACBandofSlope - (5)

23

2

333.02

=== ABCBandofSlope - (6)

34

3

333.03

=== BCCBandofSlope - (7)

40400871601321 .:.:CSlope:CSlope:CSlope = - (8)

159634433950321 ::CFrequency:CFrequency:CFrequency = - (9)

Using the slope values of the carrier band, the new frequencies are calculated and the carrier

waveforms are shown in the Fig.5. Also, the new frequency values are verified with the dwell timecalculation of the reference waveform [5].The number of switching actions (8) is balanced for all the

switches in the proposed PWM technique as shown in table I:

Table I: Switching Actions for the PWM Techniques

Parameter Proposed VFISPWM Conventional PWM

Nsw 48 72

THD 5. 92 % 7. 98%

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Figure 5: Carrier and Reference Waveforms for the Proposed Variable Frequency ISPWM.

C1 = 1596Hz

C2 = 3443 Hz

C3 = 3950 Hz

Amplitude(V)

Time (ms)

Figure 6: Generation of gating Pulses for VFISPWM using MATLAB.

Time (s)

Amplitude(V)

The parameters chosen for simulation using the proposed PWM technique is shown below:

Parameters Values Parameters Values

Main DC source voltage (Vdc) 200V Filter (Resonant Arm Type)LC (L = 2.2mH C =

220uF)

Modulation Index (ma) 1.00 Rated Output Frequency 50Hz

New Carrier Frequency 3950Hz,3443Hz & 1596Hz. Reference Voltage 200V

a. PI Control

A PI Controller (proportional-integral controller) is a feedback controller which drives the plant to be

controlled with a weighted sum of the error (difference between the output and desired set-point) andthe integral of that value. The function of PI is to regulate the multilevel inverter so that it stays closeto the nominal operating point in the presence of disturbances and noise. PI controller settings kp andki are designed in this work using Zeigler- Nichols tuning technique. The designed values of kp and ki

are 0.0135 and 18.5 respectively.

4. Simulation ResultsThe cascaded seven-level inverter is simulated using MATLAB/SIMULINK and switching signals are

generated using S-function block by employing the proposed modulation strategy. The simulation is

carried out for different modulation index and carrier frequency values [8]. The performance

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parameters considered for comparing the proposed PWM with the conventional method is the output

voltage quality, THD, WTHD and switching loss [9]. Fig.8.shows the block diagram for the pulse

generation using VFISPWM.Fig.7.and Figs.9. & 10 show the simulated output voltage waveforms andharmonic spectrums of the conventional ISPWM and the proposed MFISPWM for ma = 1.00 and Vdc =

200V. As it can be seen, the proposed ISPWM technique has always lower THD and the phase voltage

waveform shows that the top and bottom levels has less number of switching compared to the

conventional ISPWM.

Figure 7: Simulated Phase Voltage Waveforms for the proposed VFISPWM.

Figure 8: Block diagram of gating pattern (VFISPWM).

Fig.10. presents THD vs. ma graph. These results show that the VFISPWM method givesharmonic reduction for individual harmonic. The main advantage of the proposed technique is that the

number of switching per cycle is same for all the levels. For balancing the switching actions, the choice

of the carrier frequency is very important. Hence, the VFISPWM scheme is more favourable than theconventional ISPWM technique for use in asymmetric multilevel inverter[9].

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Figure 9: Output Phase Voltage Spectrum for the Proposed VFISPWM.

0 10 20 30 40 50 60 70 800

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Magnitu

de(%)ofFunda

mentalComponent

Harmonic order

FundamentalComponent(143.5V)

Figure 10: Output Phase Voltage Spectrum for the Conventional ISPWM.

0 10 20 30 40 50 60 70 800

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Harmonic Order

Magnitude(%)ofFundamentalComponent

Fundamental

Component

(141.2 V)

Figure 11: Variation of THD with modulation index for Fixed frequency (FF) and Variable frequency (VF)

ISPWM.

THD v s m a

4

5

6

7

8

9

10

11

0. 6 0. 65 0. 7 0. 75 0 .8 0. 85 0 .9 0 .95 1

Modulation Index(ma)

THD(%

)

FF IS PWM

HFIS PWM

Fig.12. & 13. shows the simulated closed loop dynamic responses of load voltage and load

current of PI controlled multilevel inverter when the load changes from full load (10ohms) to no load(10k) at t = 0.06secs. Fig.14. shows the dynamic response of load current when the load changes from

no load (10k) to full load (10 ohms) suddenly at t = 0.04seconds with P controller[10]. The filter type

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employed for MLI is resonant arm type filter and the filtered output voltage and current waveform is

shown below:

Figure 12: Transient response of MLI output phase voltage with PI control.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-200

-150

-100

-50

0

50

100

150

200

Time sec

Amplitude(V)

Figure 13: Transient response of MLI output current with PI control.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.

-0.04

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.04

Time (sec)

Am

plitude(V)

data1

Figure 14: Transient response of MLI output current with PI control.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-10

-5

0

5

10

15

Time(Sec)

A

m

plitude(V

)

data1

The steady state response of the MLI is shown below:

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Figure 15: Steady State response of MLI output Phase Voltage.

Time (ms)

Am

plit

ude(V)

The performance parameters considered for evaluating the proposed modulation strategy are:spectral quality of the output voltage, THD, WTHD and switching loss [11] which is shown in Table

II.

S.No Parameters Conventional ISPWM Proposed MFISPWM

1Spectral quality of the output

voltage

Lower Order harmonics (3,5,

7) are higher

Lower Order harmonics (3,5,7) are

reduced.

2 THD (%) 7.98 5.42

3 WTHD (%) 0.104 0.076

4 Switching Loss(mJ /Cycle) 6.38mJ (3950Hz)2.06mJ

(Calculated New Frequencies -1596Hz,3443Hz and 3950Hz)

5THD(%) (PI CONTROL)

Transient state R = 10K to10

3.29 1.62

6THD(%) (PI CONTROL)

Transient state R = 10 to 10K3.69 1.70

It is obvious that VFISPWM technique shows a better performance for the seven-level inverter.

The THD of the VFISPWM is shown with PI control which minimizes the amount of harmonics.

5. Experimental ResultsA seven-level cascaded inverter has been built using smart power module (SPM - 600V, 23A) IGBTs.

One dc source (100V) was used for the single phase hybrid cascaded MLI and the other source (50V)

to generate seven levels. The inverter was first controlled using fixed frequency ISPWM with the

following parameters: ma = 1.00 and mf = 79. FPGA SPARTAN processor is used to implement thegating pattern and PI control. The inverters output line- neutral voltage waveforms for all the three

phases are shown in Fig.16.

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Figure 16: Line neutral voltage for Hybrid MLI with FFISPWM.

The prototype inverter (refer Fig.1.) was tested using the proposed VFISPWM with different

carrier frequencies as discussed in section-IV of this paper. Specifically, the top and bottom bands hada frequency ratio of 36 while the centre and intermediate bands had a frequency index of 79 and 69.

Fig.17. shows the inverters output line- neutral voltage waveforms when using the proposed control

method. This control method balances the switching actions and gives a lower value of THD comparedto the conventional one.

Figure 17: Line neutral voltage for Hybrid MLI with VFISPWM.(mf3 =32, mf2 = 69, mf1 = 79).

50.0V / div

50.0 v / div

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6. ConclusionAsymmetric cascaded multilevel inverter using two unequal dc sources for each phase requires

minimum number of switching devices. An inverted sine wave carrier frequency modulation strategy

gives maximum fundamental voltage for a given THD. A variable frequency carrier modulation

strategy results in reduced switching losses. Advantages of all the above three methods have beenexploited in the proposed technique. The PI controller is tested for regulating output voltage and

minimizing harmonics of the chosen seven level inverter. The proposed system has lower THD and

lower switching loss as compared to that of conventional multilevel inverter.

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