EITF35: Introduction to Structured VLSI Design · · 2013-09-02Lund University/ EITF35/ Liang Liu...
Transcript of EITF35: Introduction to Structured VLSI Design · · 2013-09-02Lund University/ EITF35/ Liang Liu...
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Lund University / EITF35/ Liang Liu 2013
EITF35: Introduction to Structured VLSI Design
Part 1.1.2: Introduction (Digital Systems)
Liang Liu [email protected]
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Outline
Why Digital?• Advantages• Some applications
History & Roadmap Device Technology & Platforms System Representation Design Flow RTL Basics
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Digital is an abstraction • Discrete in time: Sampling• Discrete in value: Quantization
Digital vs. Analog• Flexibility & functionality: easier to store and manipulate information• Reliability: tolerant to noise, mismatch, variations, etc.• Economic: easy to design, and friendly to technology evolvement • Analog interface is needed
real world we use only analog signals i.e. humans can understand only analog signals
0 001 11
2.5 V
0 VClock
time
2.5 V
0 VSignal
time
Digitalization
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Applications 4C:CCCC
Computation
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Applications: CCCC
Communication
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Applications: CCCC
Control
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Consumer
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Outline
Why Digital?• Advantages• Some applications
History & Roadmap Device Technology & Platforms System Representation Design Flow RTL Basics
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Brief History
Transistor Evolution• First Transistor
Bell Labs (1947) Bardeen, Shockley Nobel Prize (1956) Morris Tanenbaum
Integration Evolution• First Integrated circuit
Jack Kilby TI (1960) Nobel Prize (2000)
“a body of semiconductor material ... wherein all the components of the electronic circuit are completely integrated.”
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Technology Evolution
Bipolar•Transistor
1947,Bardeen/Bell Lab•Bipolar junction transistor
1949,William Shockley•Logic gate
1956,Harris•Integrated circuit
1958,Kilby/Noyes•Transistor–transistor logic (TTL)
1962,James L. Buie•High-speed Emitter-coupled logic (ECL)
1974,Masaki
MOSFET (metal-oxide-semiconductor field-effect transistor )
•Bipolar faces power and size limitation•CMOS logic gate
1963, Wanlass•PMOSFET
1970, first practical MOS IC, Calculator
•NMOSFET1970, high-density storay(4K)1972, first microprocessor(4004)1974, 8080 microprocessor
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Technology Evolution (cont.)
Main trend today •Since early 80’s until today, CMOS became dominant. •Again, power consumption is now becoming a problem.
For higher performance, other technologies are used•Bi-CMOS (bipolar-CMOS): High speed memory and gate arrays.•ECL (Emitter-coupled logic): Even higher performance.•SOI (Silicon on insulator): high-performance radio frequency (RF) and radiation-sensitive applications
What’s Next?•3D-IC, FinFET•Integrated photonics circuit•Superconducting electronics•Quantum circuit•Graphene circuit
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Moore’s Law
Electronics, Apr. 19, 1965Gordon Moore (co-founder of Intel) made a prediction that semiconductor technology will double its effectiveness every 18 months
161514131211109876543210
1959
1960
1961
1962
1963
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1965
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LOG 2 O
F THE
NUMB
ER O
FCO
MPON
ENTS
PER I
NTEG
RATE
D FUN
CTIO
N
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Intel 4004:1972
First micro-processor on a single chip
2 300 transistors 0.3 mm x 0.4 mm 4 bit wordsClock: 0.108 MHz
You will have the possibility to design a more powerfulprocessor in one of our courses
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Intel Pentium 4 (2000)
42 000 000 transistors
0.18 micron CMOSClock: 1.5 GHzDie: 20 mm2
Baseband ASIC of a modern mobile phone has easily 10 times more transistors.
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SandyBridge (2009) 32 nm-64 bit 995 000 000
Transistors (23×P4)
~3.5 GHz 216 mm2
22 nm-64 bit 1 400 000 000
Transistors~3.5 GHz 160 mm2
IvyBridge (2011)
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Haswell (2013)
22 nm Tri-gate 3D
transistor 1.4b Transistors~3.5 GHz 177 mm2
Haswell on a wafer
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On-Time 2 Year Cycles
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Source: Intel
Moore’s Law: number of transistors
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Moore’s Law: frequency
Source: CPU DB: Recording Microprocessor History
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Moore’s Law: power density
1
10
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Pow
er D
ensi
ty [
W/
cm²]
4004
8008
8080
8085
8086
286386
486
P6
Pentium® proc
Source: Borkar, De Intel
Rocket Nozzle
Nuclear Reactor
Hot Plate
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Sun’sSurface
i5, i7
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Published every two years (current 2012)
Wide range: material, fabs, equipment, EDA, design, testing, modeling, simulation……
Closely followed by industry: Not an empty prediction, but an actual planning
http://public.itrs.net/
ITRS: The International Technology Roadmap for Semiconductors
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Outline
Why Digital?• Advantages• Some applications
History & Roadmap Device Technology & Platforms System Representation Design Flow RTL Basics
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General-purpose integrated circuits•Microprocessors, digital signal processors, FPGA and memories
Application-specific integrated circuits (ASIC)•Designed for a narrow range of applications•Full-custom ASIC•Standard-cell ASIC
Devices
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ASIC FPGA
Processor
Power
FlexibilityASIC
DSPStd. Proc.
FPGA
Reconfiguringof hardware
Specialization of processor
This Course
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Outline
Why Digital?• Advantages• Some applications
History & Roadmap Device Technology & Platforms System Representation Design Flow RTL Basics
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System Representation
System•SoC: a CPU chip …
Module•Macro cell in a chip:ALU…
Gate•Basic logic block:xor, nor…
Circuit•Transistors
Device•Gate, source, drain
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View a Design in a Proper Way
Abstraction: simplified model of a system• Show the selected features accurate enough • Ignore the others
Intel 4004 (2.3K transistors)Full-custom
Intel Haswell (1.4B transistors) ?
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VLSI Design Flow Evolution of circuit design
•Full-custom⇒Design-automationBased on library cells and IPsTop-down methodology
•Design abstraction⇒“Black box” or “Model”Parameter simplificationAccurate enough to meet the requirement
module HS65_GH_NAND2AX14 (Z, A, B); output Z;input A,B;not U1 (INTERNAL1, B) ;or #1 U2 (Z, A, INTERNAL1) ;specify
(A +=> Z) = (0.1,0.1);(B -=> Z) = (0.1,0.1);
endspecifyendmodule // HS65_GH_NAND2AX14
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Outline
Why Digital?• Advantages• Some applications
History & Roadmap Device Technology & Platforms System Representation Design Flow RTL Basics
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Set of specification:•What does the chip do? •How fast does it run?•How reliable will it be?•How is the silicon area?•How much power will it consume? •……
?
VLSI Design
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An iterative process that transfer the specification to a manufacturable chip through at least five levels of design abstraction.
Behavior Design
Behavior simulation
Behavior, algorithm: C/C++, SystemC, Matlab …
VLSI Design Flow
Specification Function, performance, definition:English
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Register TransferLevel Design
RTL simulation
Logic Design
Gate-level simulationTiming analysisPower analysis
VHDLVerilog
Synthesis
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Circuit Design
Physical Design
Design rule checkingPost layout simulation
Layout
Custom Design
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Verification
Verification•Check whether a design meets the specification and performance goals•Concern the correctness of the initial design and the refinement
Two aspects•Functionality•Performance (timing)
Method of Verification• Simulation
Spot check: cannot verify the absence of errorsCan be computation intensive
• Timing analysisJust check delay
• Formal verificationApply formal math techniques determine its propertyE.g, equivalence checking
• Hardware emulation
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Fabrication
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Fabrication (FUJUTSU 65nm Fab)
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TestingTesting is the process of detecting physical defects of a die or a package occurred at the time of manufacturingTesting and verification are different tasks.Difficult for large circuit
•Need to add auxiliary testing circuit in design•E.g., built-in self test (BIST), scan chain etc.
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VLSI Design Flow: Tools
Algorithm•Matlab
RTL Simulation•Modelsim,Mentor•VCS,Synopsys•VerilogXL,Cadence
Logic Synthesis•Design Compiler,Synopsys•Blast Create,Magma
Transistor Simulation•Hspice/Starsim,Synopsys•Spectra,Cadence•Eldo,Mentor
Mixed-Signal Simulation•AMS Designer,Cadence•ADMS,Mentor•Saber,Synopsys
Place & Route•Astro,Synopsys•Silicon Encounter,Cadence•Blast Fusion,Magma
Layout•Icfb/Dracula,Cadence•ICstation/Calibre,Mentor
FPGA•ISE, Xilinx•Quatus, Altera
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specification
behavior
register-transfer
logic
circuit
layout
English
Executableprogram
HDL
Logic gates
transistors
rectangles
This course
VLSI Design Flow: Summary
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Following slides should fresh up your memory
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Overall VLSI Structure
Scheduling / ordering / sequencing of operationsMapping / allocation:
• Variables -> {Reg1, ... ,RegN}• Operations -> {MUL, ADD, ALU, ... ,}
We will implement something similar in this course
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Two Basic Digital Components
F
Combinational Logic
abc
z
Always: z <= F(a, b, c);
Register
D Q
clk
en
if clk’event and clk=‘1’ thenif en=’1’ thenQ <= D;
i.e. a function that is always evaluated when an input changes.Can be expressed by a truth table.
i.e. a stored variable,Edge triggered D Flip-Flop with enable.
Rising clock edge
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Timing
Only if we guarantee to meet the timing requirements ... do the components guarantee to behave as intended.
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Combinational Logic Timing
Fabc
z
a, b, c
z
fS fF
tprop
• Propagation delay:After presenting new inputsWorst case delay before producing correct output
time
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Setup time:Minimum time input must be stable before clk↑
Register timing
D
Qtime
Register
D Q
clk
en 1
1
2
2
3
en
clk
Hold time:Minimum time input must be stable after clk↑
3
clk↑ = Rising clock edge
Propagation delay (clk_to_Q):Worst case (maximum) delay after clk↑ before new output data is valid on Q.
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Lund University / EITF35/ Liang Liu 2013
Clock Frequency
What is the maximum clock frequency?
Reg
clk
& &
&Reg
clk
RegisterPropagation delay: Tckl-Q 250psSetup time: Tsu 200psHold time: Th 100ps
AND-gatePropagation delay: Tprop 250ps
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250+250*3+200=1.2nsf=833MHz
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Critical path
…begin to explore the construction of digital systems with complex behavior
• Example: K = (A +1 B) *1 (C +2 D *2 E)Combinational circuit:
Critical Path
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Tomorrow
08:00-10:00 in E:AThe controller: Finite State MachineVHDL BasicsAssignment 1
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Control
FSM RegALU ALU
Memory
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Thanks
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