EI2301-IE_Unit 1_Part A and Part B_With answers.pdf
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Transcript of EI2301-IE_Unit 1_Part A and Part B_With answers.pdf
Industrial Electronics – Question Bank with Answers
Unit – 1 Power Semiconductor devices
PART- A (2 MARKS) QUESTIONS & ANSWERS
1. Define Reverse recovery time of POWER DIODE?
The reverse recovery time is defined as the time between the instant forward diode current
becomes zero and the instant reverse recovery current decays to 25 % of its reverse peak value.
2. Compare power MOSFET with BJT.
a. Power MOSFET has lower switching losses but BJT has higher switching losses.
b. Power MOSFET has more on state resistance and conduction losses but BJT has
lower losses
c. MOSFET is voltage controlled device whereas BJT is current controlled device.
d. MOSFET has positive temperature coefficient device whereas BJT is current
controlled device.
3. Applications of IGBT
Medium power applications such as dc & ac motor drives, UPS systems power supplies and
drive for solenoids, relays and contractors.
4. Different methods to turn on the thyristors ?
GATE TRIGGERING , dv/dt triggering, Temperature triggering and Light triggering.
5. Define Latching Current.
The minimum value of anode current which it must attain during turn-on process to
maintain conduction when gate signal is removed.
6. What is forced Commutation?
In some thyristor circuit, the input voltage is dc and the forward current of the thyristor
is forced to zero by an additional circuitry commutation circuit to turn-off the thyristor.
This technique is called forced commutation .
7. Define snubber circuit
A subber circuit consists of a series combination of resistance Rs and Cs in parallel with
the thyristor. It is mainly used for dv/dt protection.
8. Define circuit turn off time
Circuit turn off time is defined as the tine between the instant anode current becomes
zero and the instant reverse voltage due to practical circuit reaches zero.
9. What is meant by secondary breakdown ?
The secondary breakdown is destructive phenomenon, results from the current flow to a
small portion of the base producing localised hotspots.. If the energy in these hot spots is
sufficient, the excessive localized heating ay damage the transistor. Thus seccondary
breakdown is caused by a localised thermal runway, resulting from high current
concentrations.
10. What are the advantages of TRIAC?
Triac can be triggered with +ve / -ve polarity voltages.
A Triac needs a single fuse protection, which also simplifies the construction.
A Triac needs a single heat sink of slightly larger size whereas antiparallel thyristor pair
needs two heat sinks.
Part B
1. Explain the Construction & Working Principle of Power MOSFET
The Power MOSFET technology has mostly reached maturity and is the most popular device
for SMPS, lighting ballast type of application where high switching frequencies are desired
but operating voltages are low. Being a voltage fed, majority carrier device (resistive
behaviour) with a typically rectangular Safe Operating Area, it can be conveniently utilized.
Utilising shared manufacturing processes, comparative costs of MOSFETs are attractive. For
low frequency applications, where the currents drawn by the equivalent capacitances across
its terminals are small, it can also be driven directly by integrated circuits. These capacitances
are the main hindrance to operating the MOSFETS at speeds of several MHz. The resistive
characteristics of its main terminals permit easy paralleling externally also. At high current
low voltage applications the MOSFET offers best conduction voltage specifications as the
RDS(ON)
specification is current rating dependent. However, the inferior features of the
inherent anti-parallel diode and its higher conduction losses at power frequencies and voltage
levels restrict its wider application.
As mentioned in the introduction section, Power MOSFET is a device that evolved from
MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs
were by redesigning lateral MOSFET to increase their voltage blocking capacity. The
resulting technology was called lateral double deffused MOS (DMOS). However it was soon
realized that much larger breakdown voltage and current ratings could be achieved by
resorting to a vertically oriented structure. Since then, vertical DMOS (VDMOS) structure
has been adapted by virtually all manufacturers of Power MOSFET. A power MOSFET
using VDMOS technology has vertically oriented three layer structure of alternating p type
and n type semiconductors as shown in Fig 6.2 (a) which is the schematic representation of a
single MOSFET cell structure. A large number of such cells are connected in parallel (as
shown in Fig 6.2 (b)) to form a complete device. The two n+
end layers labeled “Source” and
“Drain” are heavily doped to approximately the same level. The p type middle layer is termed
the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than
n+
regions on both sides). The n-
drain drift region has the lowest doping density. Thickness
of this region determines the breakdown voltage of the device. The gate terminal is placed
over the n-
and p type regions of the cell structure and is insulated from the semiconductor
body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain
region of all cells on a wafer are connected to the same metallic contacts to form the Source
and the Drain terminals of the complete device. Similarly all gate terminals are also
connected together. The source is constructed of many (thousands) small polygon shaped
areas that are surrounded by the gate regions. The geometric shape of the source regions, to
same extent, influences the ON state resistance of the MOSFET.
Operating principle of a MOSFET At first glance it would appear that there is no path for any current to flow between the source
and the drain terminals since at least one of the p n junctions (source – body and body-Drain)
will be reverse biased for either polarity of the applied voltage between the source and the
drain. There is no possibility of current injection from the gate terminal either since the gate
oxide is a very good insulator. However, application of a positive voltage at the gate terminal
with respect to the source will covert the silicon surface beneath the gate oxide into an n type
layer or “channel”, thus connecting the Source to the Drain as explained next. The gate
region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide
layer and the p-body silicon forms a high quality capacitor. When a small voltage is
application to this capacitor structure with gate terminal positive with respect to the source
(note that body and source are shorted) a depletion region forms at the interface between the
SiO2
and the silicon as shown in Fig 6.4 (a).
The positive charge induced on the gate metallization repels the majority hole carriers from the
interface region between the gate oxide and the p type body. This exposes the negatively
charged acceptors and a depletion region is created.
Further increase in VGS
causes the depletion layer to grow in thickness. At the same time the electric
field at the oxide-silicon interface gets larger and begins to attract free electrons as shown in
Fig 6.4 (b). The immediate source of electron is electron-hole generation by thermal ionization.
The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra
holes are neutralized by electrons from the source.
As VGS
increases further the density of free electrons at the interface becomes equal to the free hole
density in the bulk of the body region beyond the depletion layer. The layer of free electrons at
the interface is called the inversion layer and is shown in Fig 6.4 (c). The inversion layer has all
the properties of an n type semiconductor and is a conductive path or “channel” between the
drain and the source which permits flow of current between the drain and the source. Since
current conduction in this device takes place through an n- type “channel” created by the
electric field due to gate source voltage it is called “Enhancement type n-channel MOSFET”.
The value of VGS
at which the inversion layer is considered to have formed is called the “Gate
– Source threshold voltage VGS
(th)”. As VGS
is increased beyond VGS
(th) the inversion layer
gets some what thicker and more conductive, since the density of free electrons increases
further with increase in VGS
. The inversion layer screens the depletion layer adjacent to it
from increasing VGS
. The depletion layer thickness now remains constant.
2. Explain the Construction & Working Principle of Power TRIAC. Discuss its four
modes of operations Fig. 4.12 (a) and (b) show the circuit symbol and schematic cross section of a triac
respective. As the Triac can conduct in both the directions the terms “anode” and “cathode”
are not used for Triacs. The three terminals are marked as MT1
(Main Terminal 1), MT2
(Main Terminal 2) and the gate by G. As shown in Fig 4.12 (b) the gate terminal is near MT1
and is connected to both N3
and P2
regions by metallic contact. Similarly MT1
is connected to
N2
and P2 regions while MT
2 is connected to N
4 and P
1 regions.
Since a Triac is a bidirectional device and can have its terminals at various combinations of positive
and negative voltages, there are four possible electrode potential combinations as given below 1. MT
2 positive with respect to MT
1, G positive with respect to MT
1
2. MT2
positive with respect to MT1, G negative with respect to MT
1
3. MT2
negative with respect to MT1, G negative with respect to MT
1
4. MT2
negative with respect to MT1, G positive with respect to MT
1
The triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However,
for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used.
Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction mechanism of a triac
in trigger modes 1 & 3 respectively.
In trigger mode-1 the gate current flows mainly through the P
2 N
2 junction like an ordinary thyristor.
When the gate current has injected sufficient charge into P2
layer the triac starts conducting through
the P1
N1 P
2 N
2 layers like an ordinary thyristor.
In the trigger mode-3 the gate current Ig
forward biases the P2
P3
junction and a large number of
electrons are introduced in the P2 region by N
3. Finally the structure P
2 N
1 P
1 N
4 turns on completely.
From a functional point of view a triac is similar to two thyristors connected in anti parallel.
Therefore, it is expected that the V-I characteristics of Triac in the 1st
and 3rd
quadrant of the V-I
plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no
signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (V
BO) of the device. However, the turning on of the triac can be
controlled by applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in the
first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the thyristor
characteristics apply to the triac (ie, latching and holding current). However, in a triac the two conducting paths (from MT
1 to MT
2 or from MT
1 to MT
1) interact with each other in the structure of
the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than
thyristors. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available.
Triacs also have a larger on state voltage drop compared to a thyristor. Manufacturers usually specify
characteristics curves relating rms device current and maximum allowable case temperature as shown
in Fig 4.15. Curves relating the device dissipation and RMS on state current are also provided for
different conduction angles.
3. Explain the Construction & Working Principle of IGBT
The introduction of Power MOSFET was originally regarded as a major threat to the power
bipolar transistor. However, initial claims of infinite current gain for the power MOSFETs were
diluted by the need to design the gate drive circuit capable of supplying the charging and
discharging current of the device input capacitance. This is especially true in high frequency
circuits where the power MOSFET is particularly valuable due to its inherently high switching
speed. On the other hand, MOSFETs have a higher on state resistance per unit area and
consequently higher on state loss. This is particularly true for higher voltage devices (greater than
about 500 volts) which restricted the use of MOSFETs to low voltage high frequency circuits (eg.
SMPS).
Constructional Features of an IGBT Vertical cross section of a n channel IGBT cell is shown in Fig 7.1. Although p channel IGBTs
are possible n channel devices are more common and will be the one discussed in this lesson.
The i-v characteristics of an n channel IGBT is shown in Fig 7.4 (a). They appear qualitatively
similar to those of a logic level BJT except that the controlling parameter is not a base current but
the gate-emitter voltage.
When the gate emitter voltage is below the threshold voltage only a very small leakage current
flows though the device while the collector – emitter voltage almost equals the supply voltage
(point C in Fig 7.4(a)). The device, under this condition is said to be operating in the cut off region. The maximum forward voltage the device can withstand in this mode (marked V
CES in Fig
7.4 (a)) is determined by the avalanche break down voltage of the body – drain p-n junction.
Unlike a BJT, however, this break down voltage is independent of the collector current as shown in Fig 7.4(a). IGBTs of Non-punch through design can block a maximum reverse voltage (V
RM)
equal to VCES
in the cut off mode. However, for Punch Through IGBTs VRM
is negligible (only a
few tens of volts) due the presence of the heavily doped n+ drain buffer layer.
As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active
region of operation. In this mode, the collector current ic
is determined by the transfer
characteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar to
that of a power MOSFET and is reasonably linear over most of the collector current range. The
ratio of ic
to (VgE
– vgE(th)
) is called the forward transconductance (gfs) of the device and is an
important parameter in the gate drive circuit design. The collector emitter voltage, on the other
hand, is determined by the external load line ABC as shown in Fig 7.4(a).
The switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET.
This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig 7.5(b). Also in
a modern IGBT a major portion of the total device current flows through the MOSFET.
Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of
a MOSFET. However, the output p-n-p transistor does have a significant effect on the switching
characteristics of the device, particularly during turn off. Another important difference is in the
gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter
voltage of an IGBT is maintained at a negative value when the device is off.
4. Explain the Construction & Working Principle of SCR
As shown in Fig 4.1 (b) the primary crystal is of lightly doped n-
type on either side of which two p
type layers with doping levels higher by two orders of magnitude are grown. As in the case of power
diodes and transistors depletion layer spreads mainly into the lightly doped n-
region. The thickness
of this layer is therefore determined by the required blocking voltage of the device. However, due to
conductivity modulation by carriers from the heavily doped p regions on both side during ON
condition the “ON state” voltage drop is less. The outer n+
layers are formed with doping levels
higher then both the p type layers. The top p layer acls as the “Anode” terminal while the bottom n+
layers acts as the “Cathode”. The “Gate” terminal connections are made to the bottom p layer.
As it will be shown later, that for better switching performance it is required to maximize the
peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are finely
distributed between gate contacts of the p type layer. An “Involute” structure for both the gate and
the cathode regions is a preferred design structure.
The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in
this figure. With ig = 0, V
AK has to increase up to forward break over voltage V
BRF before significant anode
current starts flowing. However, at VBRF
forward break over takes place and the voltage across the
thyristor drops to VH
(holding voltage). Beyond this point voltage across the thyristor (VAK
) remains
almost constant at VH
(1-1.5v) while the anode current is determined by the external load.
The magnitude of gate current has a very strong effect on the value of the break over voltage as
shown in the figure. The right hand side figure in the inset shows a typical plot of the forward break over voltage (V
BRF) as a function of the gate current (I
g)
After “Turn ON” the thyristor is no more affected by the gate current. Hence, any current pulse (of
required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient to effect
control. The minimum gate pulse width is decided by the external circuit and should be long enough
to allow the anode current to rise above the latching current (IL) level.
The left hand side of Fig 4.3 shows the reverse i-v characteristics of the thyristor. Once the thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding current (I
H). The
gate terminal has no control over the turn OFF process. In ac circuits with resistive load this happens
automatically during negative zero crossing of the supply voltage. This is called “natural
commutation” or “line commutation”. However, in dc circuits some arrangement has to be made to
ensure this condition. This process is called “forced commutation.”
During reverse blocking if ig
= 0 then only reverse saturation current (Is) flows until the reverse
voltage reaches reverse break down voltage (VBRR
). At this point current starts rising sharply. Large
reverse voltage and current generates excessive heat and destroys the device. If ig
> 0 during reverse
bias condition the reverse saturation current rises as explained in the previous section. This can be
avoided by removing the gate current while the thyristor is reverse biased.
Switching Characteristics of a Thyristor During Turn on and Turn off process a thyristor is subjected to different voltages across it and
different currents through it. The time variations of the voltage across a thyristor and the current
through it during Turn on and Turn off constitute the switching characteristics of a thyristor.
Turn on Switching Characteristics A forward biased thyristor is turned on by applying a positive gate voltage between the gate and
cathode as shown in Fig 4.10.
Fig 4.10 shows the waveforms of the gate current (i
g), anode current (i
A) and anode cathode voltage
(VAK
) in an expanded time scale during Turn on. The reference circuit and the associated waveforms
are shown in the inset. The total switching period being much smaller compared to the cycle time, iA
and VAK
before and after switching will appear flat.
As shown in Fig 4.10 there is a transition time “tON
” from forward off state to forward on state. This
transition time is called the thyristor turn of time and can be divided into three separate intervals namely, (i) delay time (t
d) (ii) rise time (t
r) and (iii) spread time (t
p). These times are shown in Fig
4.10 for a resistive load.
Turn off Switching Characteristics Once the thyristor is on, and its anode current is above the latching current level the gate loses
control. It can be turned off only by reducing the anode current below holding current. The turn off time t
q of a thyristor is defined as the time between the instant anode current becomes zero and the
instant the thyristor regains forward blocking capability. If forward voltage is applied across the
device during this period the thyristor turns on again.
During turn off time, excess minority carriers from all the four layers of the thyristor must be removed. Accordingly t
q is divided in to two intervals, the reverse recovery time (t
rr) and the gate
recovery time (tqr
). Fig 4.11 shows the variation of anode current and anode cathode voltage with
time during turn off operation on an expanded scale.
5. Discuss the types of Power DIODES. Mention its rating, applications
As mention in the introduction Power Diodes of largest power rating are required to conduct
several kilo amps of current in the forward direction with very little power loss while
blocking several kilo volts in the reverse direction. Large blocking voltage requires wide
depletion layer in order to restrict the maximum electric field strength below the “impact
ionization” level. Space charge density in the depletion layer should also be low in order to
yield a wide depletion layer for a given maximum Electric fields strength. These two
requirements will be satisfied in a lightly doped p-n junction diode of sufficient width to
accommodate the required depletion layer.
To arrive at the structure shown in Fig 2.3 (c) a lightly doped n-
epitaxial layer of specified
width (depending on the required break down voltage) and donor atom density (NdD
) is
grown on a heavily doped n+
substrate (NdK
donor atoms.Cm -3
) which acts as the cathode.
Finally the p-n junction is formed by defusing a heavily doped (NaA
acceptor atoms.Cm-3
) p+
region into the epitaxial layer. This p type region acts as the anode.
Impurity atom densities in the heavily doped cathode (Ndk
.Cm -3
) and anode (NaA
.Cm -3
) are
approximately of the same order of magnitude (10 19
Cm -3
) while that of the epitaxial layer
(also called the drift region) is lower by several orders of magnitude (NdD
≈ 10 14
Cm-3
). In a
low power diode this drift region is absent. The Implication of introducing this drift region in
a power diode is explained next.
In the previous section it was shown how the introduction of a lightly doped drift region in the p-n
structure of a diode boosts its blocking voltage capacity. It may appear that this lightly doped drift
region will offer high resistance during forward conduction. However, the effective resistance of this
region in the ON state is much less than the apparent ohmic resistance calculated on the basis of the
geometric size and the thermal equilibrium carrier densities. This is due to substantial injection of
excess carriers from both the p+
and the n+
regions in the drift region as explained next.
As the metallurgical p+
n-
junction becomes forward biased there will be injection of excess p type
carrier into the n-
side. At low level of injections (i.e δp
<< nno
) all excess p type carriers recombine
with n type carriers in the n-
drift region. However at high level of injection (i.e large forward current
density) the excess p type carrier density distribution reaches the n-
n+
junction and attracts electron
from the n+
cathode. This leads to electron injection into the drift region across the n-
n+
junction with
carrier densities δn = δ
p. This mechanism is called “double injection”
Power Diodes take finite time to make transition from reverse bias to forward bias condition (switch
ON) and vice versa (switch OFF).
Behavior of the diode current and voltage during these switching periods are important due to the
following reasons.
• Severe over voltage / over current may be caused by a diode switching at different points in the
circuit using the diode.
• Voltage and current exist simultaneously during switching operation of a diode. Therefore,
every switching of the diode is associated with some energy loss. At high switching
frequency this may contribute significantly to the overall power loss in the diode.
It is observed that the forward diode voltage during turn ON may transiently reach a significantly
higher value Vfr
compared to the steady slate voltage drop at the steady current IF.
In some power converter circuits (e.g voltage source inverter) where a free wheeling diode is used
across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be high
enough to destroy the main power switch. V
fr (called forward recovery voltage) is given as a function of the forward di/dt in the
manufacturer’s data sheet. Typical values lie within the range of 10-30V. Forward recovery time (t
fr) is typically within 10 us.
6. Discuss the turn on methods of SCR
Fig 4.10 shows the waveforms of the gate current (i
g), anode current (i
A) and anode cathode
voltage (VAK
) in an expanded time scale during Turn on. The reference circuit and the
associated waveforms are shown in the inset. The total switching period being much smaller compared to the cycle time, i
A and V
AK before and after switching will appear flat.
As shown in Fig 4.10 there is a transition time “tON
” from forward off state to forward on state.
This transition time is called the thyristor turn of time and can be divided into three separate intervals namely, (i) delay time (t
d) (ii) rise time (t
r) and (iii) spread time (t
p). These times are
shown in Fig 4.10 for a resistive load.
Delay time (td): After switching on the gate current the thyristor will start to conduct over the
portion of the cathode which is closest to the gate. This conducting area starts spreading at a finite
speed until the entire cathode region becomes conductive. Time taken by this process constitute the
turn on delay time of a thyristor. It is measured from the instant of application of the gate current to
the instant when the anode current rises to 10% of its final value (or VAK
falls to 90% of its initial
value). Typical value of “td” is a few micro seconds.
Rise time (tr): For a resistive load, “rise time” is the time taken by the anode current to rise from 10% of its final value to 90% of its final value. At the same time the voltage V
AK falls from 90% of
its initial value to 10% of its initial value. However, current rise and voltage fall characteristics are
strongly influenced by the type of the load. For inductive load the voltage falls faster than the current. While for a capacitive load V
AK falls rapidly in the beginning. However, as the current increases, rate
of change of anode voltage substantially decreases.
If the anode current rises too fast it tends to remain confined in a small area. This can give rise to
local “hot spots” and damage the device. Therefore, it is necessary to limit the rate of rise of the ON
state current Adidt⎛⎜⎝⎠ by using an inductor in series with the device. Usual values of maximum
allowable Adidt is in the range of 20-200 A/μs.
Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to
100%. During this time conduction spreads over the entire cross section of the cathode of the
thyristor. The spreading interval depends on the area of the cathode and on the gate structure of the
thyristor.
Forward voltage trigerring
Gate trigerring
LASCR
dv/dt trigerring
di/dt trigerring
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