EFM32 Series 0: Energy Optimization

Power domains of EFM32

Peripheral Reflex System

SecuritySerial Interfaces

Clock Management

I/O Ports Timers and Triggers

Energy Management

High Freq

Crystal Osc

High Freq

RC Osc

Low Freq

Crystal Osc

Low Freq

RC Osc

Voltage

Regulator

Voltage

Comparator

Power-on

Reset

Brown-out

Detector

USART UART

Low

Energy

UART

I2CGeneral

Purpose

I/O

External

Interrupt

Pin

Reset

AES

Accelerator

Ultra Low Freq

RC Osc

Timer/

Counter

Low Energy

Timer

Backup

RTC

Pulse

Counter

Watchdog

Timer

Low Energy

Sensor IF

Auxiliary

RC Osc

External

Bus

Interface

USB

TFT

Driver

Auxiliary

RC Osc

Back-up

Power

Domain

Real Time

Counter

GPIO

Wake-up

32-bit bus

Available down to: EM1

(Sleep)

EM0

(Run Mode)EM2

(Deep Sleep)

EM3

(Stop Mode)

EM4

(Shutoff Mode)

Analog Modules

ADC

LCD

Controller

Analog

Comparator

Operational

Amplifier

DAC

CPU and Memory

ARM Cortex-M3

processor

Memory

Protection

Unit

Embedded

Trace

Macrocell

Flash

Program

Memory

RAM

Memory

Debug

InterfaceDMA

ARM Cortex-M

processor

Memory

Protection

Unit

IDAC

2

Running fast vs walking slowly

Power

Frequency

Dynamic power

Static power

Frequency EM0 Current

32.768 kHz 38 µA

1 MHz 210 µA

14 MHz 2170 µA

28 MHz 4200 µA

3

Running fast vs walking slowly

Frequency EM0 Current Time

32.768 kHz 38 µA 854

1 MHz 210 µA 28

14 MHz 2170 µA 2

28 MHz 4200 µA 1

Power

Frequency

Dynamic power

Static power

4

Running fast vs walking slowly

Frequency EM0 Current Time Energy

32.768 kHz 38 µA 854 1160 µA/MHz

1 MHz 210 µA 28 210 µA/MHz

14 MHz 2170 µA 2 155 µA/MHz

28 MHz 4200 µA 1 150 µA/MHz

Finish faster and sleep longer!

Power

Frequency

Dynamic power

Static power

5

Energy Modes across EFM32 families

Device EM0µA/Mhz

EM1µA/Mhz

EM2µA

EM3µA

EM4nA

EM4+RTCnA

(ULFRCO/LFRCO/LFXO)

EFM32ZG 114 48 0.9 0.5 20 NA

EFM32TG 150 51 1.0 0.6 20 NA

EFM32G 180 45 0.9 0.6 20 NA

EFM32LG ~214¹ ~80¹ ~1.25¹ ~0.84¹ 20 240²/310¹/450²

EFM32GG ~214¹ ~80¹ ~2.00¹ ~1.62¹ 20 240²/310¹/450²

EFM32WG 225 63 0.95 0.65 20 240²/310¹/450²

¹ Different from datasheet (not confirmed) ² Not in datasheet (not confirmed)

Updated datasheets mid February

6

Clocks and Oscillators

LFA LFB

LETI

MER

DIV

LEU

AR

T0

LCD

RTC

PC

NT

DIV

DIV

DIV

HFCOREHFPER

1,7,11,14,21,(28) MHz HFRCO

32 kHzLFRCO

HFCLK

DIV 1-512 DIV 1-512

4-24/32/48 MHzHFXO

32.768 kHzLFXO

TIM

ER

1 kHzULFRC

WDOG

CPU

LFBCLKLFACLK

CG

USA

RT

AD

C

14 MHzAUXHFRCO

LESE

NSE

AES EB

I

DM

A Bus System

Trac

e O

ut

CG

CG

CG

CG

CG

CG

CG

CG

CG

CG

Flas

h W

rite

LEU

AR

T1D

IVC

G

LESE

NSE

CG

7

Prescaling power consumption penalty

8

Sleep with and without retention

Retention of RAM and digital logic

Usually higher leakage current

Sleep

Application

Sleep

Store important data in non-

volatile memory

Reset

Application

C-initialization(static variables)

Application (re)configuration

(from NV memory)

Sleep without retention

Sleep with retention

Wake-upWake-up

Peripheral configuration

9

The power of retention

0

1

2

3

4

5

6

7

8

125 250 500 1000 2000 4000 8000 16000 32000

Ave

rage

cu

rre

nt

(µA

)

Wake-up period (ms)

Deep Sleep w/RTC(128 KB RAM)

Deep Sleep w/RTC(32KB RAM)

Shutoff w/RTC

10

Saving power with instruction cache

All parts except EFM32Gs include a 512 byte instruction cache

Previously accessed instructions are automatically stored in in cache

Lower power and zero wait-states for previously read instructions

Cache hits examples:

EEMBC ULPBench: 91%

EEMBC Coremark: 90%

Prime: 100%

Cache-hit counter in Memory System Controller

Data accessed through external bus interface can also be cached

Great power/speed savings can be acheived

11

EFM32 Bus System

Icode and Dcode busses are combined into 1

12

EFM32 Memory Map

CM3 internal

System

IDCODE

13

Running from RAM

The RAM in itself has 0 wait-states at all clock speeds

BUT, the System Bus always uses 1 wait-state (standard CM3)

The system space is also not cached, so this solution is generally slower and consumes more power than running from flash.

RAM can be accessed through IDCODE bus, by using addresses 0x10000000 and upwards

BUT, bus matrix sets default RAM access to System Bus, so every IDCODE bus access to RAM takes on extra cycle in arbitration to gain access to the RAM.

Can still save power/time vs using flash in conditions with 1 wait-state or more.

14

Program Flow – Sleep and Interrupt

INSTR1

INSTR2

WFI

INSTR4

INSTR5

EM1

INSTR1

INSTR2

INSTR3

RETI

Program ISR

Sleep

Event

15

Program Flow Sleep-on-Exit

INSTR1

INSTR2

INSTR3

RETI

EM1

INSTR1

INSTR2

INSTR3

RETI

ISR1 ISR2

Event 2

Sleep

Event 1

Note: SLEEPONEXIT bit in

SCR must be set!16

Reduce wake-up latency

Wait-for-interrupt (WFI) uses 12-cycles to push and pop state before when running ISR

Wait-for-event (WFE) can be used to skip ISR (and push/pop) and continue in thread mode directly.

Fast wake-up, but interrupt source must be decoded and cleared.

SEVONPEND bit in SCR register must be set and interrupt vector disabled.

17

Other energy saving tips

Analog bias settings

Reduce bias settings for analog peripherals like the ACMP, especially when in EM2 and EM3

Supply voltage level

Supply voltage only affects current minimally as a linear regulator is powering most of the digital logic.

Optimize emlib functions

Some overhead included to optimize for easy of use and different use-case handling

Leave originals unaltered by copying functions

Use PRS and DMA to do more in sleep

18

HFRCO tuning

19

HFRCO tuning

New version of «an0004 EFM32 Clocks and Oscillators»

Released once HFRCO characteristics is ready in datasheets (mid Feb)

Tune HFRCO to any frequency between ~7 MHz to ~26 MHz

LFXO needed as reference for periodic calibration

Function library provided

Voltage and temperature variation still applies

20

These and more energy optimization tips in:an0027 EFM32 Energy Optimizationan0039 EFM32 Interrupt Handling