Efficient Solution of Language Equations Using Partitioned Representations

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Efficient Solution of Language Equations Using Partitioned Representations Alan Mishchenko UC Berkeley, US Robert Brayton UC Berkeley, US Roland Jiang UC Berkeley, US Tiziano Villa DIEGM, University of Udine, Italy Nina Yevtushenko Tomsk State University, Tomsk, Russia

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Efficient Solution of Language Equations Using Partitioned Representations. Alan Mishchenko UC Berkeley, US Robert Brayton UC Berkeley, US Roland Jiang UC Berkeley, US Tiziano Villa DIEGM, University of Udine, Italy - PowerPoint PPT Presentation

Transcript of Efficient Solution of Language Equations Using Partitioned Representations

Efficient Solution of Language Equations Using Partitioned

Representations

Alan Mishchenko UC Berkeley, USRobert Brayton UC Berkeley, USRoland Jiang UC Berkeley, USTiziano Villa DIEGM, University of Udine, ItalyNina Yevtushenko Tomsk State University, Tomsk, Russia

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Overview

• Problem formulation• Example: Traffic light controller• Partitioned representation• Solution based on partitioned representation• Experimental results• Conclusion

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Problem Formulation

FixedFixed

UnknownUnknown

ii oo

uuvv

Spec

Specification Specification S S ((i,oi,o))Fixed Fixed F F ((i,v,u,oi,v,u,o))Unknown Unknown X X ((u,vu,v))

Problem:Problem: Given Given SS and and FF, find , find the Most General Solution the Most General Solution (MGS) (MGS) XX of of

SFX

SXF

Solution:Solution:

FSMFSM

FSMFSMFSM

FSMFSM

FSMFSM

FSMFSM

FSMFSMii11

ii22

oo11

oo22

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Combinational and Sequential Flexibility

• Combinational– Network is a DAG– Node has single output– Node is a logic function

• Sequential– Network is arbitrary– Node has many outputs– Node is an FSM

( ) ( , ) ( )[ ]xCDC Y M X Y ODC X

FSMFSM

FSMFSMFSM

FSMFSM

FSMFSM

FSMFSM

FSMFSMii11

ii22

oo11

oo22

logiclogic

logiclogiclogiclogic

logiclogic

logiclogic

logiclogic

logiclogicii11

ii22

oo11

oo22

SFX

XY

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Computing Most General FSM Solution

Input: Prefix-closed specification S(i,o) and fixed part F(i,v,u,o)

Output: Most general FSM (prefix-closed progressive) solution X

begin01 X := Complete( S )02 X := Determinize( X )03 X := Complement( X )04 X := Support( X, (i,v,u,o) )05 X := Product( Complete(F), X )06 X := Support( X, (u,v) )07 X := Determinize( X )08 X := Complete( X )09 X := Complement( X ) 10 X := PrefixClose( X )11 X := Progressive( X, u ) 12 return X

end

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Example: Traffic Light Controller Synthesis

SFX I O

UV

Fixed

Unknown

F

X

Specification

S

SFX z

v

Traffic Light

Controller

F

X

Specification

S

General Topology This example

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SFX z

v

Traffic Light

Controller

F

X

SpecificationS

Traffic Light Controller (Fixed Part).model fixed.inputs v z.outputs Acc.mv v 2 wait go.mv z 3 red green yellow.mv CS, NS 3 Fr Fg Fy.latch NS CS.reset CSFr.table ->Acc1.table v z CS ->NSwait red Fr Frgo red Fr Fgwait green Fg Fggo green Fg Fywait yellow Fy Fygo yellow Fy Fr.end

z = {red, green, yellow}

v = {wait, go}

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Traffic Light Controller (Specification)

.model spec

.inputs z

.outputs Acc

.mv z 3 red green yellow

.mv CS,NS 4 S1 S2 S3 S4

.table ->Acc1.latch NS CS.reset CSS1.table z CS ->NSred S1 S2red S2 S3green S3 S4yellow S4 S1.end

SFX z

v

Traffic Light

Controller

F

X

SpecificationS

z = {red, green, yellow}

v = {wait, go}

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Traffic Light Controller (Synthesis Script)

echo "Synthesis ..."determinize -lci spec.mva spec_dci.mvasupport v(2),z(3) spec_dci.mva

spec_dci_supp.mvasupport v(2),z(3) fixed.mva fixed_supp.mvaproduct -l fixed_supp.mva

spec_dci_supp.mva p.mvasupport v(2) p.mva p_supp.mvadeterminize -lci p_supp.mva p_dci.mvaprogressive -i 0 p_dci.mva x.mva

echo "Verification ..."support v(2),z(3) x.mva x_supp.mvaproduct x_supp.mva fixed_supp.mva

prod.mvasupport v(2),z(3) spec.mva spec_supp.mvacheck prod.mva spec_supp.mva

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Traffic Light Controller (Solution).model solution.inputs v.outputs Acc.mv v 2 wait go.mv CS, NS 4 \ FrS1 FrS2 FgS3 FyS4.latch NS CS.reset CSFrS1.table ->Acc1.table v CS ->NSwait FrS1 FrS2go FrS2 FgS3go FgS3 FyS4go FyS4 FrS1.end

z = {red, green, yellow}

v = {wait, go}

SFX z

v

Traffic Light

Controller

F

X

SpecificationS

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Partitioned Representation

FixedFixed

UnknownUnknown

ii oo

uuvv

Spec

FSMFSM

FSMFSMFSM

FSMFSM

FSMFSM

FSMFSM

FSMFSMii11

ii22

oo11

oo22Latchesuu

vv

oo

ii

nsns

cscs

Output functions: oj = Oj(i,v,cs)

Transition functions: nsk = NSk(i,v,cs)Communication functions: um= Um(i,v,cs)

Fixed part:

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Computing with Partitioned Representation

• Completion• Complementation• Product computation• Changing support• Determinization (subset construction)

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Completion

o

i

ns1 ns2

cs2 cs1

0 0

00

10

01

10

00

-1 11

01

-0

-1

-0

--

DC

The output relation is

O(i,o,cs) = j[oj Oj(i,cs)]

For each current state cs, the transitions are not defined iff

P(i,o) = cs[O(i,o,cs) & (cs)]

Using partitioned representation, this computation becomes

P(i,o) = cs[j[oj Oj(i,cs)] & (cs)]

This is a partitioned image computation. Any image computation method can be used.

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Complementation

• For non-deterministic automata, requires determinization• For deterministic automata, make non-accepting states

accepting, and vice versa• In the case of partitioned representation, the don’t-care

state becomes acceptable, other states become non-acceptable

00

10

01

10

00

-1 11

01

-0

-1

-0

--

DC

00

10

01

10

00

-1 11

01

-0

-1

-0

--

DC

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Product Computation

• Combine the partitions of the two components

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Changing Support (Lifting and Projecting)

• Expanding support is trivial• Reducing support requires existential

quantification– In general, cannot be done on the partitioned

representation– Therefore, postponed until the determinization step

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Determinization (Subset Construction)

Start with the subset containing only the initial state.For each subset , compute the subsets reachable through (u, v).

Define the acceptance relation:

Compute the condition of the transition is into non-accepting states:

Restrict the transitions to those that are not contained in Q(u, v):

Direct the transition under Q(u, v) to DCN.Complete and redirect the remaining transitions to DCA.

( , , ) ( , , , ) ( , , , ) ( )cs iP u v ns U i v cs u T i v cs ns cs

1 2( , , ) [ ( , , ) ( , )]F Sjk jk

j k

C i v cs O i v cs O i cs

, 1( , ) [ ( , , , ) ( , , ) ( )]i csQ u v U i v cs u C i v cs cs

( , , ) ( , , ) & ( , )P u v ns P u v ns Q u v

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Experimental Results

Name i/o/cs Fcs/Xcs States(X) Mono,s Part,s Ratio

s510 19/7/6 3/3 54 0.2 0.3 0.7 s208 10/1/8 4/4 497 0.8 0.4 2.0 s298 3/6/14 7/7 553 2.7 0.9 3.0 s349 9/11/15 5/10 2626 810.3 37.7 21.5 s444 3/6/21 5/16 17730 CNC 25.9 - s526 3/6/21 5/16 141829 CNC 276.7 -

Name is the ISCAS benchmark namei/o/cs is the number of input/output/state variablesFcs/Xcs is the partitioning of the state variablesStates(X) is the number of states in the solutionMono is the runtime of the monolithic computation in secondsPart is the runtime of partitioned computation is in secondsRatio is improvement due to the proposed method

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Conclusions

• Introduced language solving problems• Showed a simple example• Discussed partitioned representation• Presented experimental results

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Future Work

• Developing methods for finding a particular solution contained in the most general solution

• Developing efficient sequential synthesis methods without state space traversal