Genetic Toggle Switch construction and modeling. Toggle switch design.
eeng428 lecture 013 ch10 switch level modeling · Share: bit.ly/cloudfpga Switch Level Modeling...
Transcript of eeng428 lecture 013 ch10 switch level modeling · Share: bit.ly/cloudfpga Switch Level Modeling...
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Lecture: Switch Level Modeling
Prof. Jakub SzeferDept. of Electrical Engineering, Yale University
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Switch Level Modeling
This lecture is mostly based on contents of Chapter 10, from “The Verilog Hardware Description Language” book [1], 5th edition. Example figures and(modified) code are from the textbook unless otherwise specified.
Topics covered:• Switch level primitives• Strength definitions
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Switch Level Modeling
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Between Logic Level and Analog-Transistor Level
• A system can be modeled at different levels:• Logic level• Switch level• Analog-transistor
level
• The switch level of modeling provides a level of abstraction between the logic and analog-transistor levels of abstraction
• Describe a connection of transistors, wires, capacitors, etc.• Switch level transistors are modeled as being either on or off, conducting or not conducting• Values carried by the interconnections are abstracted to a small number of discrete values, which
are called signal strengths
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Model some electrical properties, but not replacement for circuit-level
simulation and design
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Gate and Switch Level Primitives
• A number of built-in primitives is available in Verilog for switch level modeling
• Use for modeling only, not for synthesizable logic
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Switch level primitives model individual
MOS/CMOS transistors
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Inverting Shift Register Example
• An inverting shift register inverts the value as it is shifted
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Pull-up transistor
Pass transistors
Data stored in charges on the
wires / capacitors
Two-phase clock for shifting
data
tri nets can be high-impedance
trireg nets can store value, a capacitor
supply0 nets model ground connection
transistor level
devices
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Simulating Inverting Shift Register Example
• Simulating switch level designs isvery similar to regular simulation
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Design under test
(DUT)
initial block to do the
simulation
Use tasks, which have timing and
events, to make the code more readable and
modular
Testbench text output
Generate dual phase clock
Side note: simulation will finish without $finish
statement as nothing changes
when initialends
Simulation output
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Strength Modeling and SRAM Cell Example
• In an SRAM cell, two NOT gates form a feedback loop that latches a value to be stored
• Sample SRAM cell contains:• Inverter gates for the feedback loop• A pass transistor or transfer gate• Tristate buffer for writing data• Buffer for reading data
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tri nets can be high-impedance
There are no trireg nets as data is stored in
the feedback loop
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Strength Modeling and SRAM Cell Example
• Example of simulating the SRAM cell
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Strength Definitions
The drive strength of a logic gate is its capability to charge or discharge the capacitance present at its output, i.e., drive the output to 1 or to 0
• There are two types of strengths that can be specified:• The driving strengths are associated with gate
and continuous assignment outputs • The charge storage strengths are associated
with the trireg net type • The strengths may be associated
with either a 1, 0, or x value, e.g. weak0 and weak1
• When a trireg net is declared, a charge storage strength is specified to model the size of the capacitance exhibited by the net
• Need to specify delay for decay, else it never decays
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Resistive and Nonresistive Devices
• The MOS gates can be modeled as either resistive or nonresistive devices• Nonresistive gates (nmos, pmos, cmos, tran, tranif0, and tranifl)
do not affect the signal strength from input to output • Resistive gates (rnmos, rpmos, rcmos, rtran, rtranif0, rtranifl)
do affect and reduce the signal strenght from input to output
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SRAM Cell Simulation Example
• Example of SRAM cell with different strengths• If the strengths are no sufficient, the design will not work• E.g. simulation can tell the designer needed transistor sizes or capacitance sizes needed
for circuit to actually work
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Nonresistive transistors modeled Resistive transistors modeled
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References
1. Donald E. Thomas and Philip R. Moorby. " The Verilog Hardware Description Language, Fifth Edition.” Springer. 2002
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