EEL5708/Bölöni Lec 8.1 9/19/03 September, 2003 Lotzi Bölöni Fall 2003 EEL 5708 High Performance...

EEL5708/BölöniLec 8.1

9/19/03

September, 2003

Lotzi Bölöni

Fall 2003

EEL 5708High Performance Computer Architecture

Lecture 5

Intel 80x86


9/19/03

Acknowledgements

• All the lecture slides were adopted from the slides of David Patterson (1998, 2001) and David E. Culler (2001), Copyright 1998-2002, University of California Berkeley


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Opinions…

• The x86 isn’t all that complex – it just doesn’t make a lot of sense.

Mike JohnsonLeader of 80x86 Design at AMD

Microprocessor Report (1994)

• Sour grapes?• In the industry “execution” is at least as

important as bright ideas• Intel, Microsoft: good at execution


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Golden handcuffs

• 1978 – 8086 assembly language compatible extension of the successful 8080 8-bit microprocessor

• 1980 – 8087 floating point coprocessor. The architects decided to go with an extended stack architecture (!)

• 1982 – 80286 – new addressing mode (protected), backwards compatibility maintained (real addressing)


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Golden handcuffs (cont’d)

• 1985 – 80386 – Extension to 32 bits. New registers, 32 bit instructions. – New instructions make 386 an almost general purpose

register machine. – New addressing mode (segmented addressing)– Backwards compatibility maintained!

• 1989 – 80486 = 386 + 387• 1992-2002 Pentium, II, III, IV. Only 4

instructions added• The basic instruction set seems that it is

stabilized.


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Multimedia extensions

• 1997 – MMX (57 instructions, operating on the existing floating point registers).

• 1999 – SSE (four way single precision 32 bit floating point parallelism on 128 bit registers)

• 2001 – SSE2 (two way double precision 64 bit parallelism on 128 bit registers). – It allows compilers to use these registers for floating

point, instead of the x87 stack architecture


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Register set

• See figure D.1


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Instruction set

• Two operand instructions (first operand is also the destination)

• Allowed combinations:

Dest / 1 st operand 2nd operandRegister Register

Register Immediate

Register Memory

Memory Register

Memory Immediate


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Addressing modes

• Absolute [d]• Register indirect [R]• Based [Rb+d]• Indexed [R+Ri]• Based indexed with displacement [R+Ri+d]• Based with scaled indexed• Based with scaled indexed and displacement

[R+(2^I)*Ri+d]


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Segmented addresses

• Addressing is not absolute: they are relative to segments

• Original role: to access 20 bit address space with 16 bit registers

• Now, their main role is memory protection. Segments memory protection modes

• Four segment registers: CS, DS, SS, ES• Every time we address something, we need to

make sure which segment we mean (but there are defaults)


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Segmented addressing (cont’d)

• See figure D.3


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X86 Integer Instructions

• Data movement instructions: move, push, pop• Arithmetic and logic instructions: test, shift,

integer, decimal arithmetic• Control flow: jumps, branches, calls, returns• String instructions: string move, compare


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X86 integer instructions, examples

• See figure D.4, D.5


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X86 mathematical instructions

• 80 bit registers, operating like a stack– Loads push numbers on this stack– Operations find operands as top two elements and push

result– Stores can pop elements off the stack– There are also some instructions for addressing in the

stack

• Double precision floating point (64 bit)• Long integers (64 bit)


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X86 mathematical operations

• Four classes of instructions

• Data movement instructions: load, load constant, store

• Arithmetics: +, -, *, /, square root, absolute value

• Comparison – sending the result to CPU, to be used in branches

• Transcendental instructions: sine, cosine, logarithms, exponentiation


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Instruction format

• Complex, with many different instruction formats

• Ranges from 1 byte to 17 bytes.• Components

– Prefixes (repeat, lock, segment override…)– Opcode– Address specifiers – Displacement (8, 16 or 32 bit)– Immediate (8, 16 or 32 bit)


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Comparisons

• Shortage of general purpose registers• Performs about 2-4 times as many memory

accesses for floating point than RISC, 1.25 times for integer

• “Extremely painful addressing scheme”• Problem with the floating point scheme (stack

is too small). SSE2 fixes this.

EEL5708/Bölöni Lec 8.1 9/19/03 September, 2003 Lotzi Bölöni Fall 2003 EEL 5708 High Performance...

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