EEL-3705EEL-3705Digital Logic DesignDigital Logic Design

Spring 2006 SemesterSpring 2006 Semester

Professor R.J. PerryProfessor R.J. Perry

AnnouncementsAnnouncements

FSU First-Day Mandatory Attendance PolicyFSU First-Day Mandatory Attendance Policy

FAMU First-Week Mandatory Attendance PolicyFAMU First-Week Mandatory Attendance Policy

ECE Course Prerequisite PolicyECE Course Prerequisite Policy

ECE Academic Dishonesty PolicyECE Academic Dishonesty Policy

Today’s AgendaToday’s Agenda

Today’s AgendaToday’s Agenda Sign-in sheetSign-in sheet EEL-3705 Course Outline and ObjectivesEEL-3705 Course Outline and Objectives ECE Prerequisite Policy FormECE Prerequisite Policy Form HW#1HW#1 EEL-3705 Best PracticesEEL-3705 Best Practices EEL-3705 Software DistributionEEL-3705 Software Distribution Design MethodologyDesign Methodology Design AbstractionDesign Abstraction EEL-3705 Design ExampleEEL-3705 Design Example Chapter 1– Number SystemsChapter 1– Number Systems

Course Outline and Course Outline and ObjectivesObjectives

Course NotesCourse Notes

All slides will be available onlineAll slides will be available online

Exam, HW, and Quiz solutions onlineExam, HW, and Quiz solutions online

HW#1HW#1Due 1/18/2006Due 1/18/2006

Individual assignmentIndividual assignmentIf needed, enroll in course webpageIf needed, enroll in course webpageReview Course OutlineReview Course OutlineRead Chapter 0Read Chapter 0Complete Online Quiz #1Complete Online Quiz #1Download HW grading sheetDownload HW grading sheet““Digitally Drop” Word Document Digitally Drop” Word Document

Include your Name, Home University, Email Address, Intended Include your Name, Home University, Email Address, Intended major, and a brief essay (less than one page) on “Why you want major, and a brief essay (less than one page) on “Why you want to be an electrical or computer engineer?”to be an electrical or computer engineer?”

Send email to course instructor after dropping Send email to course instructor after dropping assignmentassignmentSubmit grading sheet on 1/18/2006Submit grading sheet on 1/18/2006

Homework AssignmentsHomework AssignmentsTwo weeks to complete an assignmentTwo weeks to complete an assignment No excuse for: network down, printer out of toner, No excuse for: network down, printer out of toner,

computer locks up, etc.computer locks up, etc.

HW assignments will “overlap”HW assignments will “overlap” Average one assignment due every 1 ½ weeks.Average one assignment due every 1 ½ weeks.

HW’s will build upon one anotherHW’s will build upon one another You may use solutions from previous HW’sYou may use solutions from previous HW’s

Homework assignments will be customizedHomework assignments will be customized Solutions will be given for a “general” problemSolutions will be given for a “general” problem Individual online quizzes with most assignmentsIndividual online quizzes with most assignments

You must have You must have workingworking design for full credit design for full credit

Homework AssignmentsHomework Assignments

HW’s are “self-correcting” for the “right answer.” HW’s are “self-correcting” for the “right answer.” I’ll check for the “correct” solution.I’ll check for the “correct” solution.

HW must be HW must be onon time time Digital Drop Box (time stamped)Digital Drop Box (time stamped) Both you and your partner must digitally submit.Both you and your partner must digitally submit. Only one copy of handwritten notes needed per Only one copy of handwritten notes needed per

group.group. Only one HW grading sheet needed per group.Only one HW grading sheet needed per group. HW is due at the BEGINNING of class!!!!!HW is due at the BEGINNING of class!!!!!

EEL-3705EEL-3705 HW#2 HW#2

Due: 1/25/2006Due: 1/25/2006

Reading Assignment: Reading Assignment: Chapter 1 except for section 1.2.2Chapter 1 except for section 1.2.2

Online Assignment: Quizzes #2Online Assignment: Quizzes #2 Quiz A: Bin2Dec and Dec2Bin conversionsQuiz A: Bin2Dec and Dec2Bin conversions Quiz B: Two’s complement calculationsQuiz B: Two’s complement calculations Quiz C: Binary addition Quiz C: Binary addition Quiz D: Binary subtractionQuiz D: Binary subtraction

Book/Take-home Assignment: noneBook/Take-home Assignment: none

Quartus II Assignment: noneQuartus II Assignment: none

Comments:Comments: Use % in front of binary results on online quizzesUse % in front of binary results on online quizzes

Design ProjectsDesign Projects

Design projects DO NOT replace regular Design projects DO NOT replace regular homework assignments.homework assignments. You may have both due during the same You may have both due during the same

week.week.

Hardware MUST work for more than ½ Hardware MUST work for more than ½ creditcredit

TPS QuizzesTPS Quizzes

In-class quizzes. In-class quizzes.

Designed to “keep you awake.”Designed to “keep you awake.”

Mostly group quizzes Mostly group quizzes

No make-up quizzes will be givenNo make-up quizzes will be given Used to monitor attendanceUsed to monitor attendance I will drop the three lowest quiz gradesI will drop the three lowest quiz grades

Definition:Definition:System Design ProcessSystem Design Process

Requirements SpecificationRequirements Specification

ConceptualizationConceptualization

AnalysisAnalysis

SynthesisSynthesis

VerificationVerification

DocumentationDocumentation

Iteration

EEL-3705: System Design ProcessEEL-3705: System Design ProcessRequirements SpecificationRequirements Specification

Given by me: HW, Project, Exam, etc. Given by me: HW, Project, Exam, etc.

ConceptualizationConceptualization Developed by you and your groupDeveloped by you and your group

Iteration Design CycleIteration Design CycleDesign Logic CircuitDesign Logic CircuitDraw Logic CircuitDraw Logic CircuitDebug Circuit ErrorsDebug Circuit ErrorsExamine output resultsExamine output resultsDebug Logical ErrorsDebug Logical ErrorsExamine hardware results*Examine hardware results*Debug Hardware Errors*Debug Hardware Errors*

Iteration

EEL-3705: System Design ProcessEEL-3705: System Design Process

DocumentationDocumentation ““Digitally dropped” into Blackboard Site Digitally dropped” into Blackboard Site

This could take one hour or thirty hours dependingon your skills. I will help you avoid “landmines”

EEL-3705 EEL-3705 Best PracticesBest Practices

Or, How do you get an A in this Or, How do you get an A in this class?class?

Collaborative LearningCollaborative Learning

Learning methodology in which students are not only responsible for their own learning but for the learning of other members of the group.

EEL-3705EEL-3705Best PracticesBest Practices

Keep up with the course!!!Keep up with the course!!! Coming to class.Coming to class.

HW is 5% which is equal to ½ a letter gradeHW is 5% which is equal to ½ a letter gradeFor example, w/o HW, you need 90 of 95 points (or For example, w/o HW, you need 90 of 95 points (or 95%) for an A 95%) for an A

Reading assignments.Reading assignments. HW assignments.HW assignments. QuizzesQuizzes Project assignmentsProject assignments

Complete the Assignments!!!Complete the Assignments!!! You will be allowed to work in groups, butYou will be allowed to work in groups, but

EEL-3705EEL-3705Best PracticesBest Practices

The The onlyonly way to learn way to learn to design logic circuits to design logic circuits

is to is to design design logic logic circuitscircuits. .

In other words,In other words,practice makes practice makes

perfect.perfect.

EEL-3705Best Practices

Or,Or,you will you will NOTNOT learn learn how to design by how to design by

watching me watching me designdesign

EEL-3705Best Practices

EEL-3705EEL-3705 Software Distribution Software Distribution

Quartus 5.0 Web EditionQuartus 5.0 Web Edition

MS Windows Digital Logic Design MS Windows Digital Logic Design SoftwareSoftware Schematic Capture EditorSchematic Capture Editor ComplierComplier Design SimulatorDesign Simulator Hardware DownloaderHardware Downloader

Available on COE networkAvailable on COE network

Download link available on Blackboard siteDownload link available on Blackboard site

Design MethodologyDesign Methodology

Definition: Definition: Engineering Design Engineering Design

MethodologyMethodologyA systematic approach to achieve the A systematic approach to achieve the desired goal of a solution to the problem desired goal of a solution to the problem (i.e. working design) using proven (i.e. working design) using proven principles or practices.principles or practices.Must follow EEL-3705 “Best Practices” Must follow EEL-3705 “Best Practices” design methodology for full credit on design methodology for full credit on assignments assignments

“Right Answers”

Design MethodologyDesign Methodology

“Best Practices Solution”

Violates “Best Practices”

“Right answer” but not correct solution.

Design AbstractionDesign Abstraction

How do we “describe” a system?How do we “describe” a system?

Design AbstractionDesign Abstraction

Example: Design a “system” which will complement input A

AF(x)

A and Y are single bit values

AA YY

00 11

11 00

We can “describe” this design using a logical Truth Table

Y = A

Levels of Design AbstractionLevels of Design Abstraction

Our goal in ECE is physical or hardware implementationsof the design.

DesignSpecs

a11

a22

3a3

4a4

b1

b2

b3

b4

5

6

7

8

Vcc1

0

GND

0

Hard-ware

DesignProcess

In ECE, we “design” at several levels of “abstraction”

Levels of Design AbstractionLevels of Design Abstraction

SystemSystem: Assembly Language: Assembly Language

BehavioralBehavioral: VHDL: VHDL

LogicalLogical: Gates: Gates

Electronic CircuitElectronic Circuit: Transistors: Transistors

Integrated CircuitIntegrated Circuit: IC Layout: IC Layout

FabricationFabrication: IC Processing: IC Processing

Levels of Design AbstractionLevels of Design Abstraction

System Level: EEL-4746 (M68HC11)

A ASMCode

M68HC11 Assembly Language

COMA STAA Y

Example: Design a “system” which will complement input A

Y = A

Levels of Design AbstractionLevels of Design Abstraction

Behavioral Level: EEL-4712

ANot A

VHDL

Y <= not A;

Example: Design a “system” which will complement input A

Y = A

Levels of Design AbstractionLevels of Design Abstraction

Gate Level: EEL-3705 Digital Logic Design

A

Inverter or NOT gate

Example: Design a “system” which will complement input A

Y = A

Levels of Design AbstractionLevels of Design Abstraction

Circuit Level: EEL-3300 Electronics I

A

CMOS Technology

Example: Design a “system” which will complement input A

Vdd PFET

NFET

Y = A

Levels of Design AbstractionLevels of Design Abstraction

Digital IC Design: EEL-4313 Digital IC Design

A

CMOS Technology

Example: Design a “system” which will complement input A

VDD GND

Y = A

Levels of Design AbstractionLevels of Design Abstraction

Fabrication Level: EEL-4330 Microelectronics Eng

NWELL

N+ N+P+P+

PSUB

Summary of LevelsSummary of Levels

SystemSystem: Assembly Language: Assembly Language

BehavioralBehavioral: VHDL: VHDL

LogicalLogical: Gates: Gates

Electronic CircuitElectronic Circuit: Transistors: Transistors

Integrated CircuitIntegrated Circuit: IC Layout: IC Layout

FabricationFabrication: IC Processing: IC Processing

SummarySummary

All “levels” give you the All “levels” give you the samesame result. result.

We will learn how to use the “logical” or We will learn how to use the “logical” or gate level to its most effectiveness this gate level to its most effectiveness this semester.semester.

EEL-3705EEL-3705Digital Logic DesignDigital Logic Design

Microprocessor-Based SystemMicroprocessor-Based System

CPUMemoryI/O

Interface

BUS

Microprocessor e.g. Pentium 4

To I/O

Write software to control the system!!!!

Digital Logic Based SystemDigital Logic Based SystemSensor

Subsystem

MemorySubsystem

DigitalLogicCore

OutputDisplay

InputInterface

Design the “Digital Logic Core” to control the system!!!!!!

Design Design ExampleExample

Example 2– 2-bit Up CounterExample 2– 2-bit Up Counter

State DiagramState Diagram

S0

s3

S2

S1

Reset

Y=0

Y=1

Y=2

Y=3

Clock is implied

Example – 2-bit Up CounterExample – 2-bit Up Counter

State Table State Table

psps nsns yy

S0S0 S1S1 00

S1S1 S2S2 11

S2S2 S3S3 22

S3S3 S0S0 33

S0 = 00S0 = 00

S1 = 01S1 = 01

S2 = 10S2 = 10

S3 = 11S3 = 11

Let

Let S0 = reset state

State Value Assignment

Output Vector

Example – 2-bit Up CounterExample – 2-bit Up Counter

Truth Table Truth Table

ps1ps1 ps0ps0 ns1ns1 ns0ns0 y1y1 y0y0

00 00 00 11 00 00

00 11 11 00 00 11

11 00 11 11 11 00

11 11 00 00 11 11

Example – 2-bit Up CounterExample – 2-bit Up Counter

Excitation EquationsExcitation Equations

1 1 0

0 0

1 1

0 0

s s s

s s

s

s

n p p

n p

Y p

Y p

Moore Finite State MachineMoore Finite State Machine

REG

CL

F

CL

H Ypsns

X

clock

reset

Input Vector Output Vector

NextState

PresentState

Feedback Path

Clock

Rese

t

,s s

s

n F X p

Y H p

State Equations

Logic DiagramLogic Diagram

F Logic

H Logic

Reg Block

Y Vector

No X Vector in this ExampleNo H Logic needed

Logic DiagramLogic Diagram

Course ProjectCourse Project

Temperature SensorsTemperature Sensors

Course ProjectCourse Project Design a simple temperature sensor using Design a simple temperature sensor using

digital logic digital logic

ADC YourDesign

TempSensor Display

ADC = 8-bit Analog to Digital ConverterConverts an analog signal into a digital signal

Temp Sensor = Temp to voltage transducer (analog)Your design = “talks” to the ADCDisplay = LED based seven-segment display