EEG Machine
description
Transcript of EEG Machine
EEG Machine
ByThe All-American
Boys Featuring Slo-Mo
Motaz AlturayefShawn Arni
Adam BiermanJon Ohman
High Level Block Diagram
CPU
PC/FOURIERWAVEFORM
MONITOR
RAM
FLASHAUDIO/VIDEO
OUTPUTS
USER INPUTS
ELECTRODEINPUTS
Processor Schematic
FPGA Daughter Board
JTAG
Power
A2D
FPGA Pins
Bank 1 Bank 2
Bank 3 Bank 4
RS232
Push Buttons, Switches & LEDs
Sample Code using Nios II
• IP Core– Ex. SPI
Void A2D_T (unsigned char ch){while (true) {
if(IOWR_ALTERA_AVALON_SPI_STATUS(base, data) &0x040){IOWR_ALTERA_AVALON_SPI_TXDATA(base,
data)}
}}
Testing
• Memory Storage– Inputs stored then flash LEDs– FFT analysis to Nios II console
• RS232– TX & RX LEDs, PC use
• User Output– Flash On-board LED with Goggles
Electrode Input Schematic
1
82
3
4
5
6
7
Differential Pre-Amp 2INA105KU
2.5k
R1 Input 21Res3
50.5
RGain 2Res3
2.5k
R1 Input 22Res3
100pF
C21 InputCap Semi
100pF
C22 InputCap Semi
100pF
C23 DiffCap Semi
100pF
C24 GroundCap Semi
GND GND GND GND
GND
8
5
2
3
4
6
71 Input 21OPA27GU
8
5
2
3
4
6
71 Input 22OPA27GU
Contact
Con21
Contact
Con22
1
82
3
4
5
6
7
Differential Pre-Amp 1INA105KU
2.5k
R1 Input 11Res3
50.5
RGain 1Res3
2.5k
R1 Input 12Res3
100pF
C11 InputCap Semi
100pF
C12 InputCap Semi
100pF
C13 DiffCap Semi
100pF
C14 GroundCap Semi
GND GND GND GND
GND
8
5
2
3
4
6
71 Input 11OPA27GU
8
5
2
3
4
6
71 Input 12OPA27GU
Contact
Con11
Contact
Con12
8
5
2
3
4
6
71 VinvOPA27GU
12
VccPos
1K
R1Vinv
Res1
1K
R2Vinv
Res1
GNDGNDGND
VccNeg
VccPos
8
5
2
34
671 Summer
OPA27GU
100
Rsum1
Rsum1
100
Rsum2
Rsum2
10000
Rgs
Res1
GND
5626
Rlp1
Res15626
Rlp2
Res1
8
5
2
3
4
6
71 LowPassOPA27GU
.2uF
Clp2Cap
.4uF
Clp1
Cap
1K
RBRes1
1K
RA
Res1
GND
GND
100pF
Cs1
Cap
100pF
Cs2
Cap
100pF
Cf1
Cap
100pF
Cf2
Cap
GND
GND
GND
GND
12
Output
Header 2GND
Part Selection
• Op-Amp Choice:– Burr-Brown OPA27
• Ultra low-noise amplifiers
• Differential Amp Choice:– Burr-Brown INA105
• Ultra low-noise amplifiers
• Resistor Choice– Using 1% tolerance, should be well matched enough
• Have .1% tolerance options picked out if necessary
Filter Selection
• Using Sallen-Key low-pass filter– Corner at 100Hz– 40dB/dec decrease– Simple, easily expanded if necessary– Should filter out high frequency noise components
to neural signal
• Filter not designed to filter out all environmental noise
Power
• Input circuit powered separately from rest of device– Safety:
• Don’t want any risk with a person attached to one end
– Noise:• High frequency components of processor could infect
power lines– Introduce artifacts into signal
Power cont’d
• Input board powered by 9V battery– Voltage inverted to provide negative voltage for
amplifier operation
8
5
2
34
671 Vinv
OPA27GU
12
VccPos
1K
R1Vinv
Res1
1K
R2Vinv
Res1
GNDGNDGND
VccNeg
VccPos
Testing
• Testing will be done on PCB – Voltage injections at specific input sites– Measure response for each stage functionality
• Expect to see:– Amplification of 100x– Single summed output signal– Frequencies over 100Hz are not passed– Noise levels are minimized
Design Change to Contact
• No headband– Movement and friction will introduce too many
artifacts
• Conductive paste will be necessary– Metal/Skin interface is not good enough to
conduct strong signals
• Epoxy cast contact with double-sided adhesive to form “well” for paste
Risks to Design/Implementation• Cannot get usable signal from head contacts
– Purchase commercial contacts• Low-Pass Filter not sufficient at eliminating
excess signal information– Cascade to increase effectiveness– Use Different Design
• Too much noise on the signal line– Increase contact surface area
• Increase signal strength– Isolate board through effective shielding
Output Component Changes
• Previous output components:– Audio CODEC– Monitor to display visual stimulus
• Current output components:– Separate ADC and DAC
• Input signal is not being output as auditory stimulus
– LED mounted glasses or goggles for visual stimulus• Eliminates the need for VGA circuit
ADC Architectures
Analog to Digital Converter16-Bit ResolutionLow Noise PerformanceLow Power ConsumptionSigma-Delta ArchitectureSerial SPI CommunicationConstant Output
Digital to Analog Converter16 Bit ResolutionSerial I2C Interface4 Channel OutputLow Power OperationOutput Directly to
Headphones
Visual Stimulus
Example of Glasses
Testing
• Mount ADC to through-hole adapter• Input sinusoidal signal• View output on multi-meter• Mount DAC to through-hole adapter• Input digital values from FPGA flash• View output on oscilloscope
LabView code for PSD
• The test used a .wav file • The left graph is the time domain • The right graph is the power
spectrum.
Test Results
Serial interface
Buck conveter
•Buck converter used to supply enough current to the board. (LM2676-3.3)•VCCIO will power VCCIO1, VCCIO2, VCCIO3 and VCCIO4.•VCC33 will power the ADC and the DAC chips. •MAX232 need 3.3v so will use VCC33•Memory
Power for Daughter Board
Voltage Regulator and Clock
•Voltage regulator with 1.2v output (LM1117-1.2-0.8A)•VCC12 is the input for VCCD_PLL1, VCCD_PLL2, VCCA_PLL1 and VCCA_PLLA. •The clock is 50MHz
Schedule
Questions?