EEE 312 ELECTRONICS II & EEE 282 INTRO. TO DIGITAL ELECTRONICS Spring 2015

Homework 1 Due on March 12th to ODTUCLASS with Electronic Submission (out of 100 pts.)

Use the silicon diode large signal model in Problems 1-4. VBE = VF=0.7 for all problems.

1. (12 pts.) Simplified circuit models for a system driver, receiver, and the interconnect are

depicted below. The output DC voltage specifications for the driver are as follows: VOL of 0.4 V at

IOL=-4 mA (current going into the driver), and VOH of 1.8 V at IOH=0.5 mA (current going out of the

driver). The receiver has VIL(max) = 0.8 V, and VIH(min) = 1.2 V. [Hint: Assume pull-up (to Vcc) and

pull-down (to GND) resistor models for the driver when it is transmitting 1 and 0 respectively.]

a) (2 pts.) Estimate the margin (in voltage) at the receiver input for 0 transmission, after

system interconnect voltage drop is taken into account.

b) (2 pts.) Estimate the margin (in voltage) at the receiver input for 1 transmission, after

system interconnect voltage drop is taken into account.

c) (4 pts.) Estimate tpHL and tpLH as measured at the receiver input for 0 and 1 transmission

respectively. Assume the driver switches instantaneously between 0 and 1

d) (4 pts.) Estimate the total average power dissipation in the system if the driver output

switches (between 0 and 1) with 50% duty cycle at an effective signaling frequency of 100

MHz.

50

+2 V

+2 V

ReceiverSystem

InterconnectDriver

50 pF300

150

2. (6 pts.) Determine vo1, vo2, and I for the

following network.

1 k 0.47 k

I

vo2

vo1

20 V

3. (8 pts.) Determine the voltage transfer

characteristic, VO vs. VA, for the provided

negative OR gate if VB=0 V and VA varies

between -5 V and 0 V.

VoVB

VA

1 k

4. (8 pts.) Determine the voltage transfer

characteristic, VO vs. VA, for the provided

negative AND gate if VB=-5 V and VA varies

between -5 V and 0 V.

Vo

VA

VB

2.2 k

5. (10 pts.) Sketch iR and VO

for the given network,

for the input shown. t

Vi

+

-

10 V

-10 V

10 k

iR

Vi

+

-

VO

5.3 V 7.3 V

6. (8 pts.) For the provided network,

determine the range of Vi that will

maintain VL at 8 V and not exceed the

maximum power rating of the Zener

diode.

91

RSVi

0.22 kRLPZmax = 400 mW

VZ = 8 V

7. (8 pts.) For the given circuit, determine (VBE=0.7 V): a) IBQ b) ICQ

c) VCEQ

d) VC

e) VB

f) VE

g) Power dissipation

h) Saturation current, ICsat

VE

VB+

-

VC

1.8 k510 k

VCEQIBQ

16 V

ICQ

=120

8. (6 pts.) If the base resistor in Problem 6 is increased to 910 k, find the new Q-point and

resulting values of ICQ and VCEQ.

9. (6 pts.) For the given circuit, determine:

a) IC b) VE

c) VCC

d) VCE

e) VB

f) R1 VE

VB+

-

VCC

R1

VCE =100

10.6 V

IC

20

2.7 k

1.2 k8.2 k

10. (8 pts.) For the given network, determine:

a) IB b) IC

c) VCE

d) VC +

-

VCE

IC

12 k

VC

IB

9.1 k

15 k

+16 V

-12 V

=80

11. (14 pts.) A new type of RTL logic NOR gate has a fanout of 5, and the following component

values: VCC = 5 V, RC = 470 , RB = 1.5 k, and min = 20.

a) (6 pts.) Calculate the following specifications: Noise margins NMH and NML, VoL, VoH (at

N=5), VinLmax, and VinHmin.

b) (4 pts.) Draw the voltage transfer characteristic (Vo vs Vin ) for the gate.

c) (4 pts.) Determine the absolute maximum fanout with zero noise margin.

12. (6 pts.) The high noise margin, NMH, for the

following gate is 1 V. What is the fanout, if the

model parameters are: VBEcutin = 0.5 volts, VBEsat = 0.8

volts, VCEsat = 0.2 volts, = 12

+5 V

400

2 k2 k

VO

VA VB