[EEE TRANSACTIONS ON COMPUTERS~ VOL. c-30, NO.4, APRIL ...hj/guest_editor/1.pdf · [EEE...
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[EEE TRANSACTIONS ON COMPUTERS~ VOL. c-30, NO.4, APRIL 1981 245 1 ~ ~ , .i Interconnection Networks for Parallel and Distributed Processing: An Overview C URRENT integrated Circuit technology is making fea- sible computer systems consisting of hundreds or thousands of processors. One of the most difficult problems in the design of large-scale paraUel and distributed computer systems is the choice of a communications network. An effi- cient method is needed for linking the system's processors, memories, and other devices to each other. As can be observed from the papers in this Special Issue, there are many different ~pproaches to the solution of this problem. Thebest ",sohition" for a particular system is a function of the system's intended applications, size, speed requirements, cost constraints, etc. The topic of this Special Issue spans the '''traditional'' categories of computer architecture, computer communica- tions, distributed computing, and paraUel processing. Fur- thermore; a variety of aspects of interconnection networks are considered here, from a ~etwork's mathematical graph theo- retical basis to a network's VLSI implementation. The emphasis of the papers in this Special Issue is on local interconnection networks which could, conceptually, fit in a single room and could connect a very large number of pro- cessors.The two basic types of approaches explored are shared bus networks (e.g., tree, hypercube, Chordal Ring) and mul- ,tistag,e networks (e.g., omega, b~my~n,delta). The methods used to evaluate the networks include both mathematical analyses and simulation studies. The impact of VLSI tech- nology on network implementation is also examined. . The use and VLSI implementation of the binary tree as an interconnection network is described in the paper by Horowitz and Zorat. An algorithm for mapping an arbitrary binary tree onto' the plane is presented and analyzed in terms of the' amount of chip area required. The problem of routing infor- mation among the nodes of the tree in an environment where some nodes maybe faulty is investigated. The average message handling capacity of the binary tree is compared to that of the' linear array and the square grid interconnection schemes. . In the paper by W,uand Liu, a cluster ~tructure is proposed as a conceptual interconnection scheme for-large multimi- crocomputer systems. A cluster structure. is a hierarchical organization with levels of subclusters. By specifying various structural parameters" different networks can be modeled. Examples of networks the au~hors consider as special cases of cluster structures are the hypercube and tree. The problems . of traffic conjestion and message delay for three cluster structures are.analyzed and compared. Methods to find opti- mal structural topologies that minimize interconnection lim- Itations, .subject to given constraints, are presented. .' Wittie's paper introduces "dual-bus hypercubes" as a method for interconnecting thousands of dual-port single-chip microcomputers into a "room-sized information processing system." It is assumed that each node in this network of mi- crocomputers is'a chip consistiqg of memory and a pair of , , processors for tasks and input/output. The nodes. are connected by sharing communications buses. Each node is connected to two buses; and each bus can beatiached to up to W nodes. This forms aD-dimensional W-wide hypercube of N = WD nodes. . " The performance of the hypercube is discussed and compared to ni11eother interconnection network schemes. The paper by Dias and Jump presents both analytical and simulation studies of delta networks in an asynchronous packet switched communications environment. Delta networks in- , clude such well-known muitistage networks .as the omega and the indirect binary n-cube, whose operation in an SIMD (synchronous) environment has been studied. The use of these networks in an MIMD (asynchronous) environment is cur- rently receiving much attention. This paper compares the performance of buffered delta networks with unbuffered delta networks and crossbar switches. .. .' . The' VLSI, performance, characteristics of banyan and crossbar co~munications networks are compared in the paper by FrankHp.;'It is assumed that the entire network resides on a single VLSI chip and operates in a circuit switched mode. The type of banyan network considered is the SW-banyan (8 = F = 2,), whi~h includes multistage networks such as the omega and indirect binary n~cube(the same class as considered by Dias and Jump)'. The criteria used for comparison are the chip implementation area required for the network and the time delay imposed by the network. These criteria are com- bined~o form an overaU spaG.e-timeperformance measure. Chordal Rings are pres'ented as a means of providing com- munications for a local net~ork of message-connected mi- \crocomputers in the paper by Arden anp Lee. The Chordal Ring is a ring structured network in which each node has an additional link (a chord) to some other node across the ring. From a theoretical point of view, Chordal Rings are considered as a family of regular graphs of degree three. The operation of these networks in an asynchronous environment. is explored. A distributed routing control scheme which is adaptive and fail-soft is presented. ' . A pi network, which is a concatenation of two omega net- works, is proposed by Yew and L~wrie in their papei'. The omega network is a multistage interconnection network in the same family as the SW -banyan and delta discussed above. This paper is concerned with the data permuting capability of a network, i.e., the ability to connect, in a one-to-one fashion, all inputs to aU outputs simultaneously. In order to perform certain permutations, data must be passed through the omega network more than once. A multiple-pass control algorithm for the omega is presented and applied to the pi network. . Various properties of the pi network and the control algorithm are explored. . The paper by Wirsching and Kishi describes a simulation program called CONET, used for studying interconnection ! . '. J i ;1 i J !I E I ;, , I r i Ii 0018-9340/81/0400-0245$00.75 @ 1981 IEEE
Transcript of [EEE TRANSACTIONS ON COMPUTERS~ VOL. c-30, NO.4, APRIL ...hj/guest_editor/1.pdf · [EEE...
[EEE TRANSACTIONS ON COMPUTERS~ VOL. c-30, NO.4, APRIL 1981 245
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Interconnection Networks for Parallel andDistributed Processing: An Overview
CURRENT integrated Circuit technology is making fea-sible computer systems consisting of hundreds or
thousands of processors. One of the most difficult problemsin the design of large-scale paraUel and distributed computersystems is the choice of a communications network. An effi-cient method is needed for linking the system's processors,memories, and other devices to each other. As can be observedfrom the papers in this Special Issue, there are many different~pproaches to the solution of this problem. Thebest ",sohition"for a particular system is a function of the system's intendedapplications, size, speed requirements, cost constraints, etc.
The topic of this Special Issue spans the '''traditional''categories of computer architecture, computer communica-tions, distributed computing, and paraUel processing. Fur-thermore; a variety of aspects of interconnection networks areconsidered here, from a ~etwork's mathematical graph theo-retical basis to a network's VLSI implementation.
The emphasis of the papers in this Special Issue is on localinterconnection networks which could, conceptually, fit in asingle room and could connect a very large number of pro-cessors.The two basic types of approaches explored are sharedbus networks (e.g., tree, hypercube, Chordal Ring) and mul-
,tistag,e networks (e.g., omega, b~my~n,delta). The methodsused to evaluate the networks include both mathematicalanalyses and simulation studies. The impact of VLSI tech-nology on network implementation is also examined. .
The use and VLSI implementation of the binary tree as aninterconnection network is described in the paper by Horowitzand Zorat. An algorithm for mapping an arbitrary binary treeonto' the plane is presented and analyzed in terms of the'amount of chip area required. The problem of routing infor-mation among the nodes of the tree in an environment wheresome nodes maybe faulty is investigated. The average messagehandling capacity of the binary tree is compared to that of the'linear array and the square grid interconnection schemes.
. In the paper by W,uand Liu, a cluster ~tructure is proposedas a conceptual interconnection scheme for-large multimi-crocomputer systems. A cluster structure. is a hierarchicalorganization with levels of subclusters. By specifying variousstructural parameters" different networks can be modeled.Examples of networks the au~hors consider as special cases ofcluster structures are the hypercube and tree. The problems
. of traffic conjestion and message delay for three clusterstructures are.analyzed and compared. Methods to find opti-mal structural topologies that minimize interconnection lim-Itations, .subject to given constraints, are presented. .'
Wittie's paper introduces "dual-bus hypercubes" as amethod for interconnecting thousands of dual-port single-chipmicrocomputers into a "room-sized information processingsystem." It is assumed that each node in this network of mi-crocomputers is 'a chip consistiqg of memory and a pair of
, ,
processors for tasks and input/output. The nodes. are connectedby sharing communications buses. Each node is connected totwo buses; and each bus can beatiached to up to W nodes. Thisforms aD-dimensional W-wide hypercube of N = WD nodes.. "
The performance of the hypercube is discussed and comparedto ni11eother interconnection network schemes.
The paper by Dias and Jump presents both analytical andsimulation studies of delta networks in an asynchronous packetswitched communications environment. Delta networks in- ,
clude such well-knownmuitistage networks .as the omega andthe indirect binary n-cube, whose operation in an SIMD(synchronous) environment has been studied. The use of thesenetworks in an MIMD (asynchronous) environment is cur-rently receiving much attention. This paper compares theperformance of buffered delta networks with unbuffered deltanetworks and crossbar switches. .. .' .
The' VLSI, performance, characteristics of banyan andcrossbar co~munications networks are compared in the paperby FrankHp.;'It is assumed that the entire network resides ona single VLSI chip and operates in a circuit switched mode.The type of banyan network considered is the SW-banyan (8= F = 2,), whi~h includes multistage networks such as theomega and indirect binary n~cube(the same class as consideredby Dias and Jump)'. The criteria used for comparison are thechip implementation area required for the network and thetime delay imposed by the network. These criteria are com-bined~o form an overaU spaG.e-timeperformance measure.
Chordal Rings are pres'ented as a means of providing com-munications for a local net~ork of message-connected mi-
\crocomputers in the paper by Arden anp Lee. The ChordalRing is a ring structured network in which each node has anadditional link (a chord) to some other node across thering. From a theoretical point of view, Chordal Rings areconsidered as a family of regular graphs of degree three. Theoperation of these networks in an asynchronous environment.is explored. A distributed routing control scheme which isadaptive and fail-soft is presented. ' .
A pi network, which is a concatenation of two omega net-works, is proposed by Yew and L~wrie in their papei'. Theomega network is a multistage interconnection network in thesame family as the SW-banyan and delta discussedabove. Thispaper is concerned with the data permuting capability of anetwork, i.e., the ability to connect, in a one-to-one fashion,all inputs to aU outputs simultaneously. In order to performcertain permutations, data must be passed through the omeganetwork more than once. A multiple-pass control algorithmfor the omega is presented and applied to the pi network. .
Various properties of the pi network and the control algorithmare explored. .
The paper by Wirsching and Kishi describes a simulationprogram called CONET, used for studying interconnection
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0018-9340/81/0400-0245$00.75 @ 1981 IEEE
HQward Jay Siegel (M'77) was born in NJ, on January 16, 1950. He received the S.B. de-gree in electrical engineering and the S.B. degree in management from the MassachusettsInstitute of Technology, Cambridge, MA, in 1972, the M.A. and M.S.E. degrees in 1974,and th~ Ph.D. degree in 1977, all in electrical engineering and computer science fromPrincetonUniversity,Princeton,NJ. .
In 1976 he joined the School of Electrical Engineering, Purdue University, West La-fayette, IN, where he is currently an Assistant Professor. Since January 1979 he has alsobeen affiliated with Purdue's Laboratory for Applications of Remote Sensing. His researchinterests include parallel/distributed processing, multi microprocessor systems; imageprocessing, and speech processing. His current activities include the design of PASM, alarge-scale multi microprocessor system for image processing and pattern recognition.
Dr. Siegel is a member of the Association for Computing Machinery (ACM). He waschairman of the Workshop on Interconnection Networks for Parallel and Distributed
. Processing held in April 1980, which was cosponsored by the IEEE Computer Society and the ACM. He is currently a ViceChairman of both the IEEE Computer SocjetyTCCA(Technical Cpmmittee on Computer Architecture), and TCDP (TechnicalCommittee on Distributed Processing), the Vice Chairman'of ACM SIGARCH (Special Interest Group on Computer Ar-chitecture), and an IEEE Computer Society Distinguished Visitor. He is amember of Eta Kappa Nu and Sigma Xi., , . . .
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networks. The simulator is based on a model that assumes 16processors connected to one side of a network and 16memorymodules connected to the other side. Input to the model con-sists of lists of READ/WRITErequests to memory modules.Variations in systemorganization, conflictarbitration schemes,bus width, etc., that can be supported and compared byCONET are e,Xplained.The use of the model is demonstratedby showing results obtained for a full ~rossbar n~twork andomega-type networks.
The papers in this Special Issue on Intercomiection Net-works were originally presented at the Workshop on Inter-connection Networks for Parallel and Distributed Processing.The workshop was held April 21-22, 1980, at Purdue Uni-versity, West Lafayette, IN. It was cosponsored by the IEEEComputer Society Technical Committees on Computer Ar-chitecture (TCCA), Computer Communication (TCCC), and.Distributed Processing (TCDP), and the ACM Special In-terest Group on Computer Architecture (SIGARCH), andheld in cooperation with the School of Electrical Engineeringof PurdueUniversity. .
There were 44 papers submitted to the Workshop. Peer
review was used.to choose the papers to be included. For each
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IEEE TRANSACTIONS ON COMPUTERS. VOL. C-30. NO.4. APRIL 1981
paper at least three reviews were received. As a result of.thisprocess, 13 regular papers and six short papers were selectedand presented at the Workshop. Authors of the$e papers 'wereinvited to revise their manuscripts based on the discussions andcomments made at the workshop, and submit them to theSpecial Issue (where they underwent an entire new round ofreviewing).
I would like to acknowledge the efforts of the programcommittee of the Workshop: K. E. Batchei, T. Feng, D. H.Lawrie; G. J. Lipovski, G. M. Masson, S. D. Smith, H. S.Stone, K. J. Thurber, and C. R. Vick. Interested readers arereferred to the Workshop Proceedings (IEEE CatalogNumber 80CH1560-2) for additional papers on intercon~nection networks.
Lastly~ and most importantly, I wish to thank the authorsand referees for this Special Issue for their. cooperation inmeeting the tight schedule for publication. I a,lsothank Dr. T.Booth, Editor of this TRANSACTIONS,for his guidance andassistance. It was their efforts that made this Special Issuepossible.
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HOWARD JAY SIEGEL. ...
Guest Editor
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