EECS130 Integrated Circuit Devices

Professor Ali Javey10/30/2007

MOSFETs– Lecture 4

Reading: Chapter 17, 19

Announcements

• The next HW set is due on Thursday.• Midterm 2 is next week!!!!

Threshold and Subthreshold

Subthreshold Current

I ds

(μA

/μm

)

Vgs

• The leakage current that flows at Vg <Vt is called the subthreshold current. Previously we had assumed that current is zero, but in reality that’s not the case.

90nm technology. Gate length: 45nm for NMOS, 50nm for PMOS

• The current at Vgs =0 and Vds =Vdd is called Ioff.

Intel, T. Ghani et al., IEDM 2003

ηϕ 1

=+

=depoxe

oxe

g

s

CCC

dVd

Cdep

ψS

Cox

Vg

• Subthreshold current ∝

ns (surface inversion carrier concentration)• ns ∝

eqϕs/kT

• ϕs (surface potential) varies with Vg through a capacitor network

In subthreshold, ϕs = constant +Vg /η

ϕS

Ef

Vg

Subthreshold Leakage Current

( ) / kTVqkTqs

gss eendsI ηϕ /constant/ kTqVgse η/∝∝∝∝ +

Cdep

ϕs

Cox

VG

dep

oxeC

Cη = 1 +

• Subthreshold current changes 10x for η·60mV change in Vg. Reminder: 60mV is (ln10)·kT/q

•Subthreshold swing, S : the change in Vgs corresponding to 10x change in subthreshold current. S = η·60mV, typically 80-100mV

kTqVgse η/∝dsI

Subthreshold Leakage Current

is determined only by Vt and subthreshold swing.

• Practical definition of Vt : the Vgs at which Ids = 100nA×W/L

=> ( ) kTVVqldsubthresho

tgeL

WnAI /100)( − ( ) SVV tg

LW /10100 −××=××≈ η

Vgs

Log (Ids )

Vt

100×W/L(nA)

Ioff

W SVtL

/10100 −××Ioff (nA) =Vds =Vdd

Subthreshold Swing (S)

• Smaller S is desirable (lower Ioff for a given Vt ). Minimum possible value of S is 60mV/dec.

• What are 3 ways to lower swing?

• Limitations

⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅=

oxe

dep

CC

mVS 160

Subthreshold Swing (S)

S =

Theoretical limit for S for a MOSFET is 60 mV/decade. New device concepts are being explored to make new generation of transistors that beat the 60 mV/decade limit.

Velocity Saturation

sat

sv

EEE

+=

1

μ

• velocity saturation haslarge and deleterious effect on the Ion of MOSFETS

E << Esat : v = μs EE >> Esat : v = μs Esat

room temperature

Velocity Saturation

where vsat is the carrier saturation velocity

Measured MOSFET IV – Velocity Saturation

What is the main difference between the Vg dependences of the long- and short-channel length IV curves?

0 1 2 2.5Vds (V)

0.0

0.1

0.2

0.3

0.4

I ds (

mA

/μm

)

L = 0.15 μm Vgs = 2.5V

Vgs = 2.0V

Vgs = 1.5V

Vgs = 1.0V

Vt = 0.4 V

Vds (V)I d

s (μ A

/μm

)

L = 2.0 μm Vgs = 2.5V

Vgs = 2.0V

Vgs = 1.5V

Vgs = 1.0V

0.0

0.01

0.02

0.03

Vt = 0.7 V

With velocity saturation Without velocity saturation

Ballistic Devices• If the channel is short enough (below the mean

free path length scales), then the carriers can travel from source to drain without going through any significant scattering events. This is called ballistic transport. Carriers can often gain an average velocity over vsat . This phenomena is known as velocity overshoot.

• State-of-the-art Si MOSFETs are operating at ~40% the ballistic limit.

Series Resistance of S/D

• So far we have been assuming that there is no potential drop in S/D. For miniaturized/scaled devices that is not the case and the parasitic resistance of S/D plays an important role in the IV characteristics.

S/D Series Resistance

Series resistance is highly undesirable and can cause severe performance degradation.

MOSFET Technology Scaling

Technology Scaling ― Small is Beautiful

• New technology node every three years or so. Defined by minimum metal line width.• All feature sizes, e.g. gate length, are ~70% of previous node.

YEAR 1992 1995 1997 1999 2001 2004 2007 2010

Technology Generation

0.5μm

0.35μm

0.25μm

0.18μm

0.13μm

90nm

65nm

45nm

MOSFET Technology Scaling

Vt Roll-off

65nm technology. EOT=1.2nm, Vdd =1VK. Goto et al., (Fujitsu) IEDM 2003

• Vt roll-off: Vt decreases with decreasing Lg .

• It determines the minimum acceptable Lg because Ioff is too large if Vt becomes too small.

Why Does Vt Decrease with L?― Potential Barrier Concept

• When L is small, smaller Vg is needed to reduce the barrier to 0.2V, i.e. Vt is smaller.

• Vt roll-off is greater for shorter L

~0.2V

Vds

Ec

Vgs =0V

Vgs =Vt-long

Vgs =0V

Vgs =Vt-short

Long Channel Short Channel

N+ Source

N+ Drain

Vg =0V

Vg =Vt

• Vds dependence

Energy-Band Diagram from Source to Drain

• L dependence

long channel

Vds

short channel

source/channel barrier

long channel

short channel Vgs

log(Ids )

VdsVds =0

Vds =VddVds =Vdd

Reducing the Gate Insulator Thickness and Toxe

• Oxide thickness has been reduced over the years from 300nm to 1.2nm.

• Why reduce oxide thickness?– Larger Cox to raise Ion

– Reduce subthreshold swing– Control Vt roll-off

• Thinner is better. However, if the oxide is too thin– Breakdown due to high electric field– Leakage current

Tunneling Leakage Current

• For SiO2 films thinner than 1.5nm, tunneling leakage current has become the limiting factor.

• HfO2 has several orders lower leakage for the same EOT.

Replacing SiO2 with HfO2 ---High-k Dielectric

• HfO2 has a relative dielectric constant (k) of ~24, six times large than that of SiO2 .

• For the same EOT, the HfO2 film presents a much thicker (albeit a lower) tunneling barrier to the electrons and holes.

• Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated.

(After W. Tsai et al., IEDM’03)

Challenges of High-K Technology• The challenges of high-k dielectrics are

– chemical reactions between them and the silicon substrate and gate,

– lower surface mobility than the Si/SiO2 system– too low a Vt for P-channel MOSFET (as if there is

positive charge in the high-k dielectric).

• A thin SiO2 interfacial layer may be inserted between Si-substrate and high-k film.