EE/CS 120A Lab 4

LAB 3 report due on

this Friday 2:00pm

Lab 3

Last week

Part1 (optional)

BCD to 7 Segment LED display

BCD

Control which one will be turned on

Implement on FPGA

Lab 4

This week

Flight Attendant Call System (demo & simulation)

Rising-edge Detector (demo & simulation)

LED Display Time-Multiplexing Circuit (simulation)

Lab 4 report due on Next Friday 2:00pm

2/13/2015 2:00pm

Check out connecting wires

Room: 137 Palve

Flight Attendant Call System

3 inputs: Call, Cancel and CLK

1 output: LED

Caution

Function generator (rightmost)

Square waveform

Output voltage CANNOT greater than 3.3V

Set between 3-3.3V

Otherwise, it will burn your FPGA!!

Lab manual:

Truth table (transition table)

schematic

Equations

UCF file

simulation (for Question part)

Flight Attendant Call System

Rising-edge Detector

2 inputs: signal input and CLK

1 output: LED

If the CLK is slow enough, why we only can use switch, instead of button?

Design by yourself:

State diagram

truth table(transition table)

Equations

Schematic

simulation

UCF

Demo

Rising-edge Detector

Hint: At least 3 states

Double think

Don’t go to

www.ee.ucr.edu/~lliao/teaching

How to display different number on each 7 segment LED?

Answer: time multiplexing

LED Display Time-Multiplexing Circuit

NOTICE!!

Here “0” means on “1”means off

For more information, read lab1 manual

LED Display Time-Multiplexing Circuit

HEX_TO_LEDSEG (lab manual)

Mux (ISE)

Decoder (ISE)

Wire splitter (slides)

Clock_counter_4state (by yourself)

LED Display Time-Multiplexing Circuit

VHDL code on lab manual

LED Display Time-Multiplexing Circuit

MUX

Can be found on “symbol”by

typing “M4_1E”

Rename it as Mux(7:0) to make

It can receive bus data

LED Display Time-Multiplexing Circuit

Decoder

Can be found on “symbol”by

typing “D2_4E”

LED Display Time-Multiplexing Circuit

Wire_spliter

Design by yourself

See next slides

How to create a wire spliter

LED Display Time-Multiplexing Circuit

Clock_counter_4state

Design by yourself

Further reading

On ilearn

Important

Read it before part 3

Common mistake

Set right FPGA parameters when create

new project

Remember create different project for

each part !!

Circuit &UCF

Loading bit file

Lab manual

Show me

THANKS

Research Lab

Email:WCH 234lliao003@ucr.edu