MOSFET SECOND ORDER EFFECTS

GATE OXIDE THICKNESS REDUCTION

Loren K. Schwappach

EE660 Modern Electronic Design

2 November 2011

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Why Shrink MOSFETS

70% Reduction of Line Width Results in 50% Reduction in Area (i.e. 0.7x0.7=0.49): Significantly Reduces Cost per Circuit

Other Parameters Reduced as a Result: Power Supply Voltage Gate Oxide Thickness

Changes Together Allow: Reduced Circuit Delays Historically Circuit Speed Has Increased 30% At Each

Tech Node

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Factors Affecting Scaling

Requires Threshold Voltage Reduction Improves Propagation Delays

Low Threshold Affects Noise Margins and Sub-Threshold Conduction

Gate Oxide Thickness Reduction Increases Gate Leakage Due to Electron Tunneling and Hot Carrier Injection from Substrate to Gate

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Scaling Parameters

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Reducing the Gate Insulator Thickness

SiO2: Preferred Gate Insulator from the Beginning TOX=300nm for 10um technology to 1.2nm for 65nm

technology Thinner Oxides Result in Faster Circuits! Oxide Thickness has been Scaled Roughly in Proportion

to Line Width

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Problems Resulting From Reduced TOX

Oxide Breakdown Caused By Electric Field Loss of Inversion Charge Due to Polysilicon Gate

Depletion and Inversion Layer Quantization Effects

Long Term Operation at High Field and High Temperatures Breaks Weaker Atomic Bonds: Creating Oxide Charge and VT Shifts

SiO2 thinner than 1.5nm suffers from Extreme Tunneling Leakage Would Drain Battery of a Cell Phone in Minutes!

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Transistor Leakage

Increases in Leakage Power with Technology Scaling

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How Are Defects Injected in Oxide Pinch-off Region Near Drain-Substrate Junction of

n-channel MOSFET

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PhotoInjection of Hot-Carriers

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Gate Leakage

Reduction in Oxide Thickness Results in Higher Electric Field

Electrons can Tunnel Through Oxide, Causing Leakage

Occurs when VOX < the Tunneling Barrier Height

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Solutions to Shrinking TOX

High-k dielectrics to replace SiO2

Example: HfO2 has Dielectric Constant (k) of 24 (Six Times That of SiO2)

Other Candidates Include ZrO2 and Al2O3

Often Requires Inserting Thin SiO2 Interfacial layer Between Silicon Substrate and High-k Dielectric to Reduce Unwanted Chemical Reactions

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Modifying the SPICE Model

Note: PSPICE Levels 2-4 are only Accurate for Models >1um

Recommended PSPICE Level 5 Model (Used for Short Channel Effects Correction) and Accounting for COX

Scaling Factor from Ex 23 was .36 Going from 5V to 1.8V Circuit (Adjusted VTO Accordingly)

Original COX Set to 7E-4 (Default) COX = EOX/TOX

Results to Analyze: How COX*2 Changes Effect Circuit Power Usage How COX*2 Changes Effect Circuit Speed

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Schematic

G N D _ 0

G N D _ 0

0

V D D 11 . 8 V d c

G N D _ 0

V G a t e

1 . 8 V d c

V D D 21 . 8 V d c

G N D _ 0

N M O S 2

M b re a k n 2

L = . 3 6 uW = 1 4 . 4 u

P M O S 2

M b re a k p 2

L = . 3 6 uW = 3 0 u

G N D _ 0 G N D _ 0

V o u t 2

C 24 0 p

N M O S 1

M b re a k n 1

L = . 3 6 uW = 1 4 . 4 u

P M O S 1

M b re a k p 1

L = . 3 6 uW = 3 0 u

G N D _ 0 G N D _ 0

V o u t 1

C 14 0 p

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NMOS1 and PMOS1 Models

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NMOS2 and PMOS2 Models

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Results

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Results

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Results

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Results

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Conclusions

PSPICE Proved Useful For Analyzing Second Order Oxide Thickness Effects

Lowering the Gate Oxide Thickness Reduced Power Usage (By 1mV During Switching)

Lowering the Gate Oxide Thickness Also Decreased the Max Switching Frequency (6.3MHz to 6MHz)

Scaling Parameters and Model Level Played a Huge Impact for Obtaining Usable PSPICE Results

Gate Oxide Thickness Has a Tremendous Impact On the Power and Frequency of a Circuit

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Questions?

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References

http://etd.library.vanderbilt.edu/available/etd-12032003-100902/unrestricted/Thesis.pdf

http://www.smdp.iitkgp.ernet.in/PDF/TCAD/AKM.pdf